JP6011651B2 - Semiconductor integrated circuit for process evaluation - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit for process evaluation suitable as a TEG (Test Element Group) used for evaluation of a semiconductor manufacturing process.

  When developing a fine semiconductor process or setting up a new semiconductor manufacturing plant, the most important thing is to clean up garbage in the clean room at an early stage, take measures against defects, and optimize the processing (lithography) process. In order to obtain a product that satisfies the target quality at a high yield, the characteristics of the transistor are brought close to ideal characteristics and variations in the characteristics of the transistor are suppressed. At present, so-called process level TEG is used in order to investigate the state of occurrence of processing defects due to dust and defects due to processing limits. As an example of this type of process level TEG, a TEG provided with a large-scale metal wiring pattern, in which the wiring width and wiring interval of each part are variously changed from a processing limit dimension to a dimension sufficiently larger than that, There is. By manufacturing this TEG, measuring the measurement points of open (disconnection) defects of metal wiring and short-circuiting defects between metal wirings, and performing statistical processing on the measurement results The dependence of the probability of occurrence of defects on the dimensions of the wiring width and wiring spacing is examined. On the other hand, in order to investigate whether the manufacturing process related to the transistor is good or bad (whether the manufacturing process is in a state where an ideal transistor can be manufactured), for example, a TEG composed of a single transistor is used. A number of TEGs with various single transistors with various dimensions changed from the processing limit to a sufficiently larger dimension are manufactured, the dimensions of each single transistor of these TEGs are measured, and the electrical characteristics of each transistor , And statistical processing of the measurement results of the dimensions of each part and the electrical characteristics of each transistor is performed. In addition, there exist patent documents 1-3 as technical literature regarding evaluation of the manufacturing process using TEG, for example.

Japanese Patent Laid-Open No. 7-014900 JP 2001-237377 A JP 2007-299885 A

  In the process evaluation technology using the process level TEG described above, in order to obtain large-scale measurement data used for statistical processing, it is necessary to measure open defects and short defects for a large number of process levels TEG. It takes. In addition, if there is a defect, it is necessary to identify the location where the open defect or short-circuit defect occurs in order to find out the cause, but it is difficult to determine where the defect has occurred, and rely on visual inspection. There is only. Also, when performing process evaluation using a single transistor TEG, it is necessary to measure several hundred pieces for each dimension in order to obtain large-scale measurement data used for statistical processing. It takes an enormous amount of time.

  In addition, the recent demand for low voltage, which is a market requirement for semiconductor integrated circuits, makes the process optimization work more difficult. That is, when the power supply voltage of the semiconductor integrated circuit is lowered, it becomes difficult to manufacture a semiconductor integrated circuit that satisfies the required quality at a high yield unless extremely strict process control is performed. This is because, when the power supply voltage is lowered, a slight deviation from the ideal state of the electrical characteristics of the transistor makes the operation margin of each part in the circuit short and impedes the function of the semiconductor integrated circuit. In order to solve this problem, it is not necessary to realize a clean environment free of dust and to realize a stable machining process that does not cause machining defects. Subtle process control is required to converge to an ideal state while suppressing variations in electrical characteristics.

  However, when such process control is performed by evaluating the electrical characteristics of a single transistor as in the past, an enormous number of transistors are used in order to accurately investigate variations in transistor characteristics due to variations in process parameters on the production line. It is necessary to evaluate the electrical characteristics of the single transistor, and the man-hours for that purpose are enormous. For this reason, there has been a problem that it takes a long time to make a mass production of a semiconductor integrated circuit operating at a low voltage with a high yield, and the start of mass production is delayed.

  The present invention has been made in view of the circumstances described above, and provides a semiconductor integrated circuit for process evaluation capable of collecting information as a judgment material for delicate process control in a short time. With the goal.

  According to the present invention, a memory such as a RAM (Random Access Memory) or a ROM (Read Only Memory) is used as a process evaluation semiconductor integrated circuit. These memories have a configuration in which a large number of memory cells are spread over a wide area in a chip. Normally, each memory cell is made with a minimum element size and arranged in a chip with a minimum interval. Therefore, it is difficult to normally manufacture all memory cells unless the process is in good condition. In that sense, it can be said that a memory having a large number of memory cells is the best process evaluation semiconductor integrated circuit suitable for evaluating the quality of a process. In the memory, each memory cell can be individually accessed. For this reason, if some of the memory cells in the memory are defective, processed, open, short, or defective due to the electrical characteristics of the transistor, access to the memory cell is normal. By confirming that this is not done, the defective memory cell can be identified. Therefore, it is possible to investigate the cause by investigating the defective memory cell.

  A feature of the present invention is that, in addition to such a memory as a process evaluation semiconductor integrated circuit, the transistor electrical characteristics deviate from the standard state with respect to the memory as the process evaluation semiconductor integrated circuit. Is provided with means for conspicuous the degree of influence (specifically, lack of operation margin of each part in the circuit).

  A first typical example to which the present invention is applied is an SRAM (Static Random Access Memory). This SRAM is a memory with the strongest demand for low voltage. On the other hand, the SRAM is a memory that is sensitive to variations in the electrical characteristics of the transistors, and a slight deviation from the standard state of the electrical characteristics of the transistors causes a malfunction. In that sense, the SRAM is very easily affected by the quality of the process state, and is extremely suitable as a semiconductor integrated circuit for process evaluation.

  In a preferred embodiment of the present invention, in order to make the influence of the deviation of the electrical characteristics of the transistor from the standard state conspicuous, a power supply system for supplying a power supply voltage to the memory cell in the SRAM, A power supply system that supplies a power supply voltage to the circuit is separated, and the power supply voltage supplied to the memory cell can be controlled independently of the power supply voltage for other circuits.

  According to this aspect, it is possible to measure whether or not access to each memory cell is normally performed by reducing only the power supply voltage for the memory cell. This measurement can be easily performed using, for example, an LSI tester.

  Here, under a situation where the power supply voltage to the memory cell is low, the operation margin of the memory cell is reduced, and the electrical characteristics of the transistors constituting the memory cell are slightly deviated from the standard state. May not work properly. Since there are a large number of memory cells in the SRAM, there are memory cells that do not operate normally due to a slight deviation from the standard state of the transistor electrical characteristics when the power supply voltage decreases. Can appear. The location of such a memory cell can be easily confirmed by measurement using an LSI tester. When a memory cell that causes a malfunction under low voltage and a memory cell that does not malfunction even under a low voltage are found, detailed electrical characteristics of the transistors of both memory cells may be measured. By performing this measurement, it is possible to understand the difference in the electrical characteristics of the transistor between a memory cell that causes a malfunction and a memory cell that does not, and a process for manufacturing an SRAM satisfying the required quality at a high yield. Decision materials for control can be acquired in a short time.

  In another aspect of the present invention, the SRAM is provided with means for controlling the operating condition of the sense amplifier for reading data from the memory cell via the bit line. More specifically, in one embodiment, the SRAM is provided with means for variably controlling the magnitude of the load connected to the memory cell via the bit line when reading data from the memory cell. If the load connected to the memory cell via the bit line becomes heavy, the sense amplifier may not operate normally due to a slight deficiency in the driving capability of the transistors constituting the memory cell. Therefore, also in this aspect, it is possible to obtain, in a short time, judgment materials for process control for manufacturing an SRAM satisfying the required quality with a high yield.

  In another aspect, the SRAM is provided with means for variably controlling the generation timing of the internal control signal for controlling the operation timing of the sense amplifier when reading data from the memory cell. According to this aspect, when the sense amplifier is operated at a stricter timing than usual, a malfunction in the sense amplifier is likely to occur due to a slight deviation from the standard state of the electrical characteristics of the transistors constituting the sense amplifier. Therefore, also in this aspect, it is possible to obtain, in a short time, judgment materials for process control for manufacturing an SRAM satisfying the required quality with a high yield.

  In another aspect of the present invention, means for arbitrarily controlling a row selection voltage for activating a transfer gate of a memory cell to be accessed is provided in the SRAM.

  According to this aspect, when the row selection voltage is lowered, the operation margin of the transfer gate of the memory cell is reduced, and the malfunction of the memory cell is likely to occur due to the deviation of the electrical characteristics of the transfer gate from the standard state. . Therefore, also in this aspect, it is possible to obtain, in a short time, judgment materials for process control for manufacturing an SRAM satisfying the required quality with a high yield.

  Various means for making the row selection voltage variable are conceivable. In a preferred aspect, the power supply system for the power supply voltage for the row decoder that generates the row selection voltage is separated from the power supply system for the power supply voltage for other circuits, and the power supply voltage for the row decoder is independent of the power supply voltage for the other circuits. A controllable configuration is employed. In another preferred embodiment, a configuration is adopted in which an output stage that outputs a row selection voltage in the row decoder is a level shifter, and a power supply voltage for the level shifter can be controlled from outside the SRAM. Instead of supplying the voltage supplied to the circuit for outputting the row selection voltage from the outside of the SRAM, a step-down circuit for stepping down the power supply voltage or a step-up circuit for stepping up the power supply voltage is provided in the chip, thereby stepping down or stepping up the voltage. The supplied power supply voltage may be supplied to a circuit that outputs a row selection voltage.

  A second typical example to which the present invention is applied is a mask ROM. In this mask ROM, a memory cell is constituted by one transistor. Therefore, it is possible to construct a mask ROM composed of a huge number of memory cells. In that sense, the mask ROM is a very suitable process evaluation semiconductor integrated circuit.

  In a preferred aspect of the present invention, when reading data from the memory cell, the reference current is applied to the mask ROM having a sense amplifier that determines the read data from the memory cell by comparing the current flowing through the memory cell with the reference current. Means for switching is provided.

  According to this aspect, by determining whether or not the data reading from each memory cell in the mask ROM is normally performed while switching the reference current, the output current of the transistors constituting each memory cell is determined. You can check the size. Therefore, according to this aspect, it is possible to obtain, in a short time, judgment materials for process control for manufacturing a mask ROM that satisfies the required quality with a high yield.

  In another aspect of the present invention, there is provided means for switching a row selection voltage for a mask ROM having a row decoder that applies a row selection voltage to a transistor that constitutes a memory cell to be read when data is read from the memory cell. Provide.

  According to this aspect, by determining whether or not data reading from each memory cell in the mask ROM is normally performed while switching the row selection voltage, the output current of the transistors constituting each memory cell is determined. Dependence on the row selection voltage can be examined. Therefore, according to this aspect, it is possible to obtain, in a short time, judgment materials for process control for manufacturing a mask ROM that satisfies the required quality with a high yield.

  In a further preferred aspect of the present invention, the mask ROM is provided with both means for switching the reference current and means for switching the row selection voltage. According to this aspect, by determining whether or not data reading from each memory cell in the mask ROM is normally performed while switching the combination of the reference current and the row selection voltage, the transistors constituting each memory cell The type of output current characteristics can be examined. Therefore, according to this aspect, it is possible to obtain, in a short time, judgment materials for process control for manufacturing a mask ROM that satisfies the required quality with a high yield.

It is a block diagram which shows the general structural example of SRAM which is a 1st example of application of this invention. 3 is a circuit diagram showing a specific circuit configuration of the SRAM. FIG. It is a circuit diagram which shows the structural example of one memory cell in the SRAM cell array of the SRAM. It is a figure which illustrates the measuring method of SNM (Static Noise Margin; static noise margin) of a memory cell. It is a figure which illustrates the measurement result of SNM of a memory cell. 1 is a circuit diagram showing a configuration of an SRAM which is a first embodiment of a process evaluation semiconductor integrated circuit according to the present invention; FIG. FIG. 5 is a circuit diagram showing a configuration of an SRAM sense amplifier which is a second embodiment of a semiconductor integrated circuit for process evaluation according to the present invention; It is a wave form diagram which shows the waveform of each part at the time of the read access in the same embodiment. It is a figure which shows the control circuit in the same embodiment. It is a circuit diagram which shows the structural example of the same control circuit. It is a circuit diagram which shows the structural example of mask ROM which is the 2nd example of application of this invention. It is a figure which shows the example of the gate voltage-drain current characteristic of the transistor which comprises a memory cell in the mask ROM. It is a circuit diagram which shows the structural example of the sense amplifier of the same mask ROM. FIG. 5 is a circuit diagram showing a configuration of a load circuit for switching a reference current to be compared with a current flowing in a memory cell to be accessed in a mask ROM which is a second embodiment of a semiconductor integrated circuit for process evaluation according to the present invention; . 4 is a diagram showing another example of a circuit that switches a reference current to be compared with a current flowing in a memory cell that is an access target in the embodiment. FIG. 4 is a circuit diagram illustrating a configuration example of a row selection circuit that generates a row selection voltage to be applied to a memory cell to be accessed in the embodiment. FIG.

Embodiments of the present invention will be described below with reference to the drawings.
<First Application Example of the Invention>
FIG. 1 is a block diagram showing a general configuration example of an SRAM which is a first application target example of the present invention. In FIG. 1, an SRAM cell array 100 is a circuit in which memory cells each storing 1-bit information are arranged in a matrix. The control circuit 900 is a circuit that generates various internal control signals for performing write access and read access to a desired memory cell in accordance with various control signals given from the outside. The SRAM is roughly classified into an asynchronous SRAM and a synchronous SRAM. In the case of an asynchronous SRAM, the control circuit 900 is supplied with, for example, a chip enable signal CEB, an output enable signal OEB, and a write enable signal WEB. In this case, the control circuit 900 generates an internal control signal for executing write access in response to both the write enable signal WEB and the chip enable signal CEB becoming active levels (in this example, L level). In addition, the control circuit 900 generates an internal control signal for executing read access in response to both the output enable signal OEB and the chip enable signal CEB becoming active levels (in this example, L level). In the case of a synchronous SRAM, a clock CLK instructing the synchronization timing is given to the control circuit 900. The control circuit 900 generates various internal control signals for write access and read access based on the clock CLK.

  The input / output buffer 500 is a 16-bit input / output circuit having both an input buffer function and an output buffer function. Input / output buffer 500 functions as an input buffer under the control of control circuit 900 at the time of write access, and writes 16-bit write data input via data input / output terminals I / O0 to I / O15. Supply to circuit 600. In read access, the input / output buffer 500 functions as an output buffer under the control of the control circuit 900, and the 16-bit read data output from the sense amplifier 400 is used as data input / output terminals I / O0 to I / O15. Output from.

  The column gate 700 is an aggregate of a plurality of switches interposed between the write circuit 600 and the sense amplifier 400 and the SRAM cell array 100, and includes 16 memory cells corresponding to arbitrary addresses in the SRAM cell array 100. It serves to interconnect the write circuit 600 and the sense amplifier 400.

  Write circuit 600 applies 16-bit write data supplied via input / output buffer 500 to 16-bit memory cells in SRAM cell array 100 connected via column gate 700 at the time of write access. A circuit for writing. The sense amplifier 400 is a circuit that reads data from 16-bit memory cells in the SRAM cell array 100 connected via the column gate 700 and outputs the data to the input / output buffer 500 during read access.

  The address input circuit 800 is supplied with 24-bit address data A0 to A23 for specifying the addresses of the 16 memory cells to be accessed at the time of write access and read access. When a write access or a read access is performed, the address input circuit 800 holds address data A0 to A23 for specifying a memory cell to be accessed under the control of the control circuit 900.

  The address data A0 to A23 output from the address input circuit 800 are separated into row address data (upper bit data) and column address data (lower bit data), the row address data is sent to the row decoder 200, and the column address data is sent to the column address data. This is supplied to the column decoder 300. The row decoder 200 selects each memory cell belonging to the row specified by the row address among the memory cells constituting the SRAM cell array 100. The column decoder 300 causes the column gate 700 to select a memory cell belonging to the column specified by the column address among the memory cells belonging to the row selected by the row decoder 200 in the SRAM cell array 100, and the write circuit 600 and the sense amplifier 400 is a circuit to be connected to 400.

  FIG. 2 is a circuit diagram illustrating a detailed internal configuration of the SRAM shown in FIG. In FIG. 2, in order to prevent the drawing from becoming complicated, not all the memory cells of the SRAM cell array 100 shown in FIG. 1, but the data input / output terminals I / O0 to I / O15 shown in FIG. The memory cell matrix Mmn-0 in the range of the storage destination of the 0th bit of the 16-bit data inputted / outputted through the index (the index “0” in Mmn-0 is the 0th to 15th bits). Only 0) is shown. 2, in order to prevent the drawing from becoming complicated, among all the switches constituting the column gate 700, the memory cell matrix Mmn-0, the write circuit 600, and the sense amplifier 400 are interposed. Only the switch to be shown is shown.

  As shown in FIG. 2, the memory cell matrix Mmn-0 used as the 0th bit storage area is configured by m + 1 rows and n + 1 columns of memory cells Mij (i = 0 to m, j = 0 to n). Yes. In the memory cell matrix Mmn-0, for each column, a pair of bit lines BITj and BITjB are wired along the arrangement direction of m + 1 memory cells Mij (i = 0 to m) belonging to the column. Each time, word lines are wired along the arrangement direction of n + 1 memory cells Mij (j = 0 to n) belonging to the row.

  The row decoder 200 in FIG. 1 includes m + 1 row selection circuits 200-i (i = 0 to m) shown in FIG. Each of the row selection circuits 200-i (i = 0 to m) is connected to a word line of each row of the memory cell matrix Mmn-0. Each of the row selection circuits 200-i (i = 0 to m) has an active level when the row number i ′ indicated by the row address matches the row number i associated with the row selection circuit 200-i. A NAND gate 201 that outputs (L level) and an inverter 202 that outputs a row selection voltage WLi obtained by inverting the output signal of the NAND gate 201 to a word line. By the action of these row selection circuits 200-i (i = 0 to m), the row selection voltage corresponding to the row number i ′ indicated by the row address among the row selection voltages WLi (i = 0 to m) corresponding to each row. Only WLi ′ is set to the H level, and other row selection voltages WLi (i ≠ i ′) are set to the L level. This is a row selection operation performed by the row decoder 200.

  The column gate 700 has n + 1 pairs of switches CGj and CGjB (j = 0 to n) as a switch group corresponding to the memory cell matrix Mmn-0. The n + 1 pairs of switches CGj and CGjB (j = 0 to n) are each configured by an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor; field effect transistor having a metal oxide semiconductor structure; hereinafter simply referred to as a transistor). Has been. One end of each of the switch pair CGj and CGjB (j = 0 to n) is connected to the bit line pair BITj and BITjB (j = 0 to n) corresponding to each column of the memory cell matrix Mmn-0. The other end is commonly connected to a global bit line pair DL and DLB corresponding to the 0th bit.

  The column decoder 300 in FIG. 1 is composed of n + 1 column selection circuits 300-j (j = 0 to n) shown in FIG. This column selection circuit 300-j (j = 0 to n) is associated with each column of the memory cell matrix Mmn-0, and the switch pair (transistor pair) CGj and CGjB (j = 0 to n). A column selection voltage COLj (j = 0 to n) is supplied to each gate. Each of the column selection circuits 300-j (j = 0 to n) has an active level when the column number j ′ indicated by the column address matches the column number j associated with the column selection circuit 300-j. A NAND gate 301 that outputs (L level) and an inverter 302 that inverts the output signal of the NAND gate 301 and outputs the inverted signal to the gates of the switch pair CGj and CGjB as the column selection voltage COLj. By the operation of these column selection circuits 300-j (j = 0 to n), the switch pair corresponding to the column number j ′ indicated by the column address among the switch pairs (transistor pairs) CGj and CGjB (j = 0 to n). Only (transistor pair) CGj ′ and CGj′B are ON, and the other switch pair (transistor pair) CGj and CGjB (j ≠ j ′) are OFF. Accordingly, only the bit line pair BITj ′ and BITj′B in the column corresponding to the column number j ′ indicated by the column address is connected to the global bit line pair DL and DLB via the switch pair (transistor pair) CGj ′ and CGj′B. Is done.

At the time of write access, the write circuit 600 is connected to the bit line pair BITj ′ and BITj′B through the bit line pair BITj ′ and BITj′B thus connected to the global bit line pair DL and DLB. Write data (the 0th bit here) is written to one memory cell selected based on the row address among the m + 1 memory cells. In read access, the sense amplifier 400 is connected to the bit line pair BITj ′ and BITj′B via the bit line pair BITj ′ and BITj′B thus connected to the global bit line pair DL and DLB. Data (here, the 0th bit) is read out from one memory cell selected based on the row address among the m + 1 memory cells that have been output, and output to the input / output buffer 500.
Although only the configuration of the portion related to the storage of the 0th bit has been described above, the configuration of the portion related to the storage of the other 1st to 15th bits is the same.

  FIG. 3 is a circuit diagram showing a specific configuration example of one memory cell in the SRAM cell array 100. In FIG. 3, BL and BLB are any bit line pair in the bit line pair BITj and BITjB (j = 0 to n) in FIG. 2, and WL is the row selection voltage WLi (i = 0 to m).

  As shown in FIG. 3, the memory cell has P-channel transistors P1 and P2 and N-channel transistors N1, N2, Ta1, and Ta2. Here, the P-channel transistor P1 and the N-channel transistor N1 are inserted in series between the high-potential-side power supply VDD and the low-potential-side power supply VSS, and constitute a CMOS inverter. The P-channel transistor P2 and the N-channel transistor N2 are also inserted in series between the high potential side power supply VDD and the low potential side power supply VSS, and constitute a CMOS inverter. These CMOS inverters use each other's output signal as an input signal, and constitute a flip-flop. The N channel transistor Ta1 is interposed between the bit line BL and a connection point between both drains of the P channel transistor P1 and the N channel transistor N1. The N channel transistor Ta2 is interposed between the bit line BLB and a connection point between both drains of the P channel transistor P2 and the N channel transistor N2. These N-channel transistors Ta1 and Ta2 are turned on when a row selection voltage WL of H level is applied to the gate through the word line at the time of write access and read access, and the bit line BL and bit line BLB are turned on by the transistor P1. And N1 and a common connection point of the transistors P2 and N2, respectively.

Write access to this memory cell is performed as follows.
(1) The column decoder 300 shown in FIGS. 1 and 2 connects the bit line pair corresponding to the column to which the memory cell belongs to the write circuit 600 via the column gate 700.
(2) A pair of bit lines in which the write circuit 600 shown in FIGS. 1 and 2 applies a positive / reverse two-phase bit signal corresponding to the write data “1” / “0” via the column gate 700. Output to BL and BLB. More specifically, when the write data is “1”, the write circuit 600 outputs an H-level positive-phase bit signal to the bit line BL and an L-level negative-phase bit signal to the bit line BLB. When the write data is “0”, an L level positive phase bit signal is output to the bit line BL and an H level negative phase bit signal is output to the bit line BLB.
(3) The row decoder 200 shown in FIGS. 1 and 2 sets the row selection voltage WL for the memory cell to the H level, and then returns to the L level. As a result, the potential at the connection point of both drains of the transistors P1 and N1 becomes the potential of the bit line BL, and the potential at the connection point of both drains of the transistors P2 and N2 becomes the potential of the bit line BLB. Maintained in the memory cell.

On the other hand, read access to the memory cell is performed as follows.
(1) The column decoder 300 shown in FIGS. 1 and 2 connects the bit line pair corresponding to the column to which the memory cell belongs to the global bit line pair DL and DLB via the column gate 700.
(2) A precharge circuit (not shown) applies a precharge potential to the global bit line pair DL and DLB and the bit line pair BL and BLB connected to the global bit line pair DL and DLB via the column gate 700.
(3) The row decoder 200 shown in FIGS. 1 and 2 sets the row selection voltage WL for the memory cell to the H level, and turns on the transistors Ta1 and Ta2 of the memory cell. Here, when the memory cell stores “1”, since the transistor N1 is OFF and the transistor N2 is ON, the potentials of the bit line BLB and the global bit line DLB decrease from the precharge potential. To do. On the other hand, when the memory cell stores “0”, since the transistor N1 is ON and the transistor N2 is OFF, the potentials of the bit line BL and the global bit line DL are decreased from the precharge potential. .
(4) The sense amplifier 400 shown in FIGS. 1 and 2 differentially amplifies the potential difference between the global bit lines DL and DLB, thereby outputting a signal Dout corresponding to the data stored in the memory cell.

In the access operation to the memory cell described above, there are variations in parameters or electrical characteristics of each transistor constituting the memory cell, specifically, threshold voltage Vt, mutual conductance gm, mobility μ, or beta value β of each transistor. Influence. In addition, since both the source and the drain of the transistors Ta1 and Ta2 are not fixed, the variation in the back gate bias characteristics of these transistors affects the access operation to the memory cell.
The above is the details of the SRAM which is the first application target example of the present invention. The first to fourth embodiments described below are embodiments in which the present invention is applied to such an SRAM.

<First Embodiment>
Among the characteristics of each part of the SRAM, there is a memory cell SNM that is easily affected by transistor characteristic variations (characteristic variations caused by process parameter variations). In this embodiment, attention is paid to this SNM.

  FIG. 4 is a diagram illustrating an example of an SNM measurement method. FIGS. 5A to 5D illustrate SNM measurement results. 5A to 5D, the horizontal axis indicates the voltage V0 at the common connection point of the transistors P1 and N1, and the vertical axis indicates the voltage V1 at the common connection point of the transistors P2 and N2.

  In the measurement method illustrated in FIG. 4, in the memory cell shown in FIG. 3, the high potential side power supply voltage VDD of the SRAM is 1.0 V, the voltage of the N well to which the P channel transistors P1 and P2 belong is 1.0 V, and the low potential side The power supply voltage VSS is 0V, the voltage of the P well to which the N channel transistors N1 and N2 belong is 0V, the row selection voltage for the word line WL is the same voltage as the power supply voltage VDD, and the P well to which the N channel transistors Ta1 and Ta2 as transfer gates belong. Measurements 1 and 2 are performed with a voltage of 0V. Here, in measurement 1, the bit line BL is opened, the bit line BLB is fixed to the same voltage as the power supply voltage VDD, and the voltage V0 at the connection point between both drains of the transistors P1 and N1 is changed from 0 V to VDD (in FIG. 4). In the example, the change in the voltage V1 at the common connection point of the transistors P2 and N2 when the voltage is raised to 1.0 V) is observed. The broken lines in FIGS. 5A to 5D show how the voltage V1 changes in accordance with the change in the voltage V0 obtained in the measurement 1. FIG. In measurement 2, the bit line BLB is opened, the bit line BL is fixed to the same voltage as the power supply voltage VDD, and the voltage V1 at the connection point of both drains of the transistors P2 and N2 is changed from 0 V to VDD (example in FIG. 4). The voltage V0 at the common connection point of the transistors P1 and N1 when the voltage is raised to 1.0V) is observed. The solid lines in FIGS. 5A and 5C show how the voltage V0 changes in accordance with the change in the voltage V1 obtained in the measurement 2. FIG.

  In FIGS. 5A to 5D, the dashed curve and the solid curve are each called a butterfly curve. These two butterfly curves cross each other on the way, and the positional relationship between the top and bottom and the left and right is switched. In each of FIGS. 5A to 5D, two squares are drawn that fit in two regions sandwiched between the broken butterfly curve and the solid butterfly curve. The size of this square is the size of the SNM. More specifically, the square between the two butterfly curves in the region where the broken butterfly curve is at the upper right and the solid butterfly curve is at the lower left is a noise that increases the voltage V0 at the connection point of the drains of the transistors P1 and N1. When this occurs, it is an SNM (hereinafter referred to as a first SNM for convenience) indicating an allowable value of the noise level that does not invert the stored contents of the memory cell. The square between the two butterfly curves in the region where the solid butterfly curve is at the upper right and the broken butterfly curve is at the lower left is when noise that raises the voltage V1 at the connection point of the drains of the transistors P2 and N2 occurs. , An SNM (hereinafter referred to as a second SNM for convenience) indicating an allowable value of the noise level that does not invert the stored contents of the memory cell.

  FIGS. 5A and 5C illustrate the SNM characteristics when the power supply voltage VDD of the SRAM is 1.0 V, respectively. In the example shown in FIG. 5 (a), the beta value β and the threshold voltage Vt of each transistor constituting the memory cell are balanced, and the first SNM and the second SNM are approximately the same. Is also large enough. Therefore, in this memory cell, stable write access and read access are possible.

  However, the butterfly curve depends on the balance of the beta values and the threshold voltage of each of the transistors P1, N1, P2, and N2. For example, in FIG. 5A, when the beta ratio βp / βn between the beta value βp of the transistor P2 and the beta value βn of the transistor N2 increases, the broken butterfly curve projects in the upper right direction. Conversely, when the beta ratio βp / βn decreases, the broken butterfly curve retreats in the lower left direction. Further, when the transistor N2 and the threshold voltage Vtn increase and the threshold voltage Vtp of the transistor P2 decreases, the voltage V0 at which the broken butterfly curve rapidly falls increases. Conversely, when the transistor N2 and the threshold voltage Vtn decrease and the threshold voltage Vtp of the transistor P2 increases, the voltage V0 at which the broken butterfly curve suddenly falls decreases.

  Further, in the process of increasing the voltage V0 from 0V to VDD, when the transistor N2 is turned on, a current flows into the transistor N2 via the transistor Ta2. Therefore, the voltage V1 does not fall down to the VSS level (0V), but the VSS level. Float from. If the current flowing through the transistor Ta2 is constant, the floating of the voltage V1 from the VSS level at this time increases as the threshold voltage Vtn of the transistor N2 is higher or the beta value βn of the transistor N2 is lower.

  Thus, the broken butterfly curve is affected by changes in threshold voltages and beta values of the transistors P2 and N2. On the other hand, the solid butterfly curve is mainly affected by changes in the balance of the beta values and the balance of the threshold voltages of the transistors P1 and N1. Thus, since the butterfly curve is affected by changes in the threshold voltage and beta value of each transistor, the first and second SNMs are also affected by changes in the threshold voltage and beta value of each transistor.

  In the example shown in FIG. 5C, an imbalance occurs between the threshold voltage Vt or the beta value of each transistor constituting the memory cell, and the first SNM is sufficiently large, but the second SNM Is slightly smaller.

  As described above, when the characteristics (specifically, the threshold voltage VT and the beta value) of the transistors constituting the memory cell vary, the sizes of the first and second SNMs vary. However, when the power supply voltage VDD of the SRAM is as high as 1.0 V, the degree of influence on the first and second SNMs of the characteristic variation of each transistor constituting the memory cell is relatively small. For this reason, it is relatively easy to suppress the characteristic variation of each transistor constituting the memory cell so that both the first and second SNMs are sufficiently large.

  However, as the power supply voltage VDD of the SRAM decreases, the degree of influence on the first and second SNMs of the characteristic variation of each transistor constituting the memory cell increases. FIGS. 5B and 5D show an example of this. In the example of FIGS. 5B and 5D, the power supply voltage VDD of the SRAM is 0.5V. In the example shown in FIG. 5B, since the power supply voltage VDD is 0.5 V, the first and second SNMs are considerably small, but the characteristics of the transistors constituting the memory cell are balanced. Therefore, the first and second SNMs are sized to enable normal write access and read access. However, in the example shown in FIG. 5D, there is a subtle imbalance in the characteristics of the transistors constituting the memory cell, and the second SNM is almost eliminated due to the influence. As described above, when the operation margin is insufficient, the write access and the read access are hindered.

  Thus, when the power supply voltage VDD of the SRAM decreases, the degree of influence of the transistor characteristic variation on the SNM increases, and the first SNM and the sufficiently large SNM due to a slight deviation from the ideal state of the transistor characteristics. The second SNM cannot be obtained, and malfunction is likely to occur. The present embodiment utilizes this point.

  FIG. 6 is a circuit diagram showing a configuration of an SRAM which is an example of a process evaluation semiconductor integrated circuit according to the present embodiment. As is clear from comparison with FIG. 2, in the SRAM according to the present embodiment, the power supply system that supplies the power supply voltage to the memory cell and the power supply system that supplies the power supply voltage to circuits other than the memory cell are separated. The power supply voltage supplied to the memory cell can be controlled independently of the power supply voltage for other circuits.

  Power supply terminals VDD (C) and VSS (C) in FIG. 6 are power supply terminals (bonding pads) dedicated to memory cells. The sources of P channel transistors P1 and P2 of all memory cells constituting SRAM cell array 100 are connected to power supply terminal VDD (C), and the sources of N channel transistors N1 and N2 of all memory cells are connected to power supply terminal VSS ( C).

  Further, power supply terminals VDD and VSS in FIG. 6 are power supply terminals for circuits other than memory cells in the SRAM. Circuits other than the memory cell such as the control circuit 900, the address input circuit 800, the row decoder 200, the column decoder 300, the write circuit 600, the sense amplifier 400, and the input / output buffer 500 in FIG. 1 are connected via the power supply terminals VDD and VSS. Receive power supply voltage. Therefore, in each memory cell, the row selection voltage applied to the word line WL has the same voltage value as the voltage VDD applied to the power supply terminal VDD or the same voltage value as the voltage VSS applied to the power supply terminal VSS. Each voltage applied to the bit lines BL and BLB at the time of write access has the same voltage value as the voltage VDD applied to the power supply terminal VDD or the same voltage value as the voltage VSS applied to the power supply terminal VSS. The precharge voltage applied to the bit lines BL and BLB at the time of read access has the same voltage value as the voltage VDD applied to the power supply terminal VDD.

  In this embodiment, such SRAM is used for process evaluation as follows, for example. First, the power supply terminal VDD for a circuit other than the memory cell is fixed at, for example, a potential of 1.0 V, and the potential of the power supply terminal VSS (C) dedicated to the memory cell and the power supply terminal VSS for the circuit other than the memory cell is set to 0 V. The variable power supply voltage applied between the power supply terminals VDD (C) and VSS (C) dedicated to the memory cell is decreased stepwise from the normal voltage value (eg, 1.0 V) by a predetermined voltage (that is, the power supply The potential of the terminal VDD (C) is lowered stepwise), and at each power supply voltage, test data is written to and read from all the memory cells constituting the SRAM cell array 100, and the SRAM cell array 100 is read. It is determined whether or not write access and read access to each memory cell are normally performed (first measurement). ).

  Next, the power supply terminal VSS for a circuit other than the memory cell is fixed to, for example, a potential of 0 V, and the potential of the power supply terminal VDD (C) dedicated to the memory cell and the power supply terminal VDD for a circuit other than the memory cell is set to, for example, the potential. The variable power supply voltage applied between the power supply terminals VDD (C) and VSS (C) dedicated to the memory cell is lowered step by step from the normal voltage value (for example, 1.0V) by a predetermined voltage. That is, the potential of the power supply terminal VSS (C) is increased stepwise), and at each power supply voltage, the test data is written to and read from all the memory cells constituting the SRAM cell array 100, It is confirmed whether or not write access and read access to each memory cell in the SRAM cell array 100 are normally performed. The second measurement).

  In these first and second measurements, the power supply voltage VDD-VSS for the circuits other than the memory cells is not changed in order to evaluate the memory cells separately from other circuits, that is, write to the memory cells. The control signal for access and the control signal for read access should be generated at a sufficient level so that the write access and read access will not fail due to causes other than the characteristic failure of the memory cell itself. It is.

  Here, the number of memory cells constituting the SRAM cell array 100 is enormous and distributed over a wide range of SRAM chips. Therefore, the transistors of each memory cell in the chip have a relatively large characteristic variation, and due to the characteristic variation of the transistors of each memory cell, the first and second SNMs of each memory cell also vary. If the power supply voltage applied between the power supply terminals VDD (C) and VSS (C) is reduced, the degree of influence of the transistor characteristic variation on the first and second SNMs increases, and therefore the SRAM cell array 100. The memory cell in which the first or second SNM is insufficient among all the memory cells constituting the memory cell and normal write access or read access is not performed in any of the first measurement or the second measurement described above Begins to occur.

  In this way, a memory cell in which normal write access or read access is not performed when the power supply voltage is lowered and a memory cell in which normal write access and read access are performed even if the power supply voltage is lowered are specified, The detailed characteristics (threshold voltage, drive capability, etc.) of each transistor of both memory cells are measured. By performing such a measurement, it is possible to specify the characteristics of the transistor that are an impediment to obtaining a normal and stable SRAM operation.

  Therefore, according to the present embodiment, an SRAM or other semiconductor that satisfies the target quality is obtained by measuring the semiconductor integrated circuit for process evaluation by changing only the power supply voltage applied to the memory cell, and utilizing the result for adjusting the process conditions. The process conditions of the semiconductor manufacturing process can be optimized so that the integrated circuit can be manufactured with a high yield.

  In the embodiment described above, the high-potential side power supply terminal is separated into VDD (C) and VDD, and the low-potential side power supply terminal is separated into VSS (C) and VSS in the memory cell and other circuits other than the memory cell. However, only one of the high-potential side power supply terminal and the low-potential side power supply terminal is separated by a memory cell and another circuit other than the memory cell. The cell and the circuit other than the memory cell may be shared. Further, instead of providing a dedicated power supply terminal for the memory cell as described above, a step-down circuit capable of controlling the output voltage value by an external control signal is provided in the SRAM chip, and the power supply voltage between the power supply terminals VDD and VSS is reduced. A power supply voltage stepped down by a circuit may be applied to the memory cell.

Second Embodiment
In the SRAM, the sense amplifier 400 is a circuit that is susceptible to variations in transistor characteristics. When the operating point of the sense amplifier 400 is changed, the degree of influence of transistor characteristic variations on the operation of the sense amplifier 400 can be changed. The present embodiment provides a semiconductor integrated circuit for process evaluation using this point.

  FIG. 7A is a circuit diagram showing a configuration example of the SRAM sense amplifier according to the present embodiment. The sense amplifier includes a first stage amplifier 410, an equalizing switch 420, a second stage amplifier 430, an equalizing switch 440, and load circuits 413 and 414.

  In FIG. 7A, as described in the first embodiment, the global bit line pair DL and DLB are connected to the column gate 700 and the bit line pair BL and BLB (see FIGS. 2 and 3) at the time of read access. To the transistors Ta1 and Ta2 (see FIG. 3) of the memory cell to be accessed.

  The first-stage amplifier 410 is generated between the global bit lines DL and DLB when the transistors Ta1 and Ta2 of the memory cell to be accessed connected to the global bit line pair DL and DLB are turned on during read access. An amplifier that differentially amplifies the potential difference. In this example, the first-stage amplifier 410 includes a first differential amplifier 411 and a second differential amplifier 412. The first differential amplifier circuit 411 and the second differential amplifier circuit 412 have two N-channel transistors between the common source of each differential transistor pair and the low-potential side power supply line. An enable signal EN1 is applied to the gate of one of these N-channel transistors. In the other N-channel transistor, a positive bias voltage BIAS having a predetermined magnitude is applied to the gate and is always ON. The first differential amplifier circuit 411 is activated only while the enable signal EN1 is at the H level, and the potential difference V (between the potential V (DL) of the global bit line DL and the potential V (DLB) of the global bit line DLB. DL) −V (DLB) is differentially amplified, and a signal resulting from the differential amplification is output to the sense line SEN. The second differential amplifier circuit 412 is activated only during a period when the enable signal EN1 is at the H level, and the potential difference between the potential V (DLB) of the global bit line DLB and the potential V (DL) of the global bit line DL. V (DLB) −V (DL) is differentially amplified, and a signal resulting from the differential amplification is output to the sense line SENB.

  The equalizing switch 420 is a transfer gate in which a P channel transistor to which an equalizing signal EQ1B is applied to the gate and an N channel transistor to which the equalizing signal EQ1 is applied to the gate are connected in parallel, and is interposed between the global bit lines DL and DLB. Yes. Here, the equalizing signal EQ1B is a signal obtained by inverting the level of the equalizing signal EQ1.

  Second-stage amplifier 430 includes flip-flop 431 and N-channel transistors 432 and 433. Here, the flip-flop 431 includes two CMOS inverters 431a and 431b using the output signals of the counterparts as input signals, and the sources and low potential sides of the two N-channel transistors in the two CMOS inverters. An N-channel transistor 431c interposed between the power supply VSS and the power supply VSS. Here, the output terminal of the CMOS inverter 431a and the input terminal of the CMOS inverter 431b are connected to the output bit line OUT, and the output terminal of the CMOS inverter 431b and the input terminal of the CMOS inverter 431a are connected to the output bit line OUTB. The enable signal EN2 is applied to the gate of the N-channel transistor 431c. The N-channel transistor 432 is a transistor that is turned on only when the enable signal EN2B applied to the gate is at the H level and connects the sense line SENB to the output bit line OUT. The N-channel transistor 433 is a transistor that is turned on only when the enable signal EN2B supplied to the gate is at the H level and connects the sense line SEN to the output bit line OUTB. Here, the enable signal EN2B is a signal obtained by inverting the level of the enable signal EN2.

  The equalizing switch 440 is a transfer gate in which a P-channel transistor to which the equalizing signal EQ2B is supplied to the gate and an N-channel transistor to which the equalizing signal EQ2 is supplied to the gate are connected in parallel, and is interposed between the sense lines SEN and SENB. . Here, the equalizing signal EQ2B is a signal obtained by inverting the level of the equalizing signal EQ2.

  FIG. 7B is a circuit diagram showing a configuration example of each of the load circuits 413 and 414. The load circuits 413 and 414 are circuits having the same configuration in which four P-channel transistors are connected in parallel as shown in the figure, and are interposed between the high-potential-side power supply VDD and the global bit line DL (DLB). Has been. Here, the precharge signal Pre and the load adjustment signals T1B, T2B, and T3B are respectively supplied to the gates of the four P-channel transistors constituting the load circuit 413 (414). The precharge signal Pre is a signal that is set to the L level when precharging the global bit line DL (DLB) and the bit line BL (BLB) connected thereto. The P channel transistor to which the precharge signal Pre is supplied to the gate constitutes a precharge circuit. The load adjustment signals T1B, T2B, and T3B are L level, load when each P-channel transistor to which each is applied is used as a load of a memory cell connected to the global bit line DL (DLB) and the bit line BL (BLB). This signal is set to H level when not.

  FIG. 8 is a waveform diagram showing signal waveforms at various parts during read access. Prior to the read access, the precharge signal Pre for each P channel transistor in the load circuit 413 (414) is set to the L level, and the global bit line DL (( DLB) and the bit line BL (BLB) connected thereto are precharged with the power supply voltage VDD. At the time when this precharge is performed, equalizing signals EQ1 and EQ2 are set to H level (equalizing signals EQ1B and EQ2B are set to L level), global bit lines DL and DLB are short-circuited by equalizing switch 420, and sense lines SEN and SENB is short-circuited by the equalizing switch 440. At the time when this precharge is performed, the enable signals EN1 and EN2 are at the L level (enable signals EN1B and EN2B are at the H level), and the first and second differential amplifiers 411 and 412 and the flip-flop 431 are inactive. The active state is short-circuited between the sense line SENB and the output bit line OUT and between the sense line SEN and the output bit line OUTB.

  Thereafter, the precharge signal Pre is canceled (set to H level), and the row selection voltage WL for the memory cell to be accessed is raised. As a result, the transistors Ta1 and Ta2 of the memory cell to be accessed are turned on, and the drains of the N-channel transistors N1 and N2 of the memory cell are connected to the global bit lines DL and DLB via the bit lines BL and BLB (see FIG. 3). Connected to each.

  Then, with a slight delay from the cancellation of the precharge signal Pre, the equalizing signal EQ1 is canceled (the equalizing signal EQ1 is set to L level and the equalizing signal EQ1B is set to H level), and the equalizing switch 420 is turned OFF. At this time, when the N channel transistor N1 connected to the global bit line DL is ON among the N channel transistors N1 and N2 of the memory cell described above, the potential of the global bit line DL starts to decrease. On the other hand, when the N-channel transistor N2 connected to the global bit line DLB is ON, the potential of the global bit line DLB starts to decrease.

  Next, after a predetermined time t1 from the cancellation of the equalizing signal EQ1, the enable signal EN1 rises to the H level, and the first and second differential amplifiers 411 and 412 of the first stage amplifier 410 are activated. At this time, if there is a sufficient potential difference (usually about 100 mV) between the bit lines DL and DLB, the first and second differential amplifiers 411 and 412 differentially amplify the potential difference between the global bit lines DL and DLB. Is done normally.

  Next, with a little delay from the rise of the enable signal EN1, the equalizing signal EQ2 is canceled (the equalizing signal EQ2 is set to L level and the equalizing signal EQ2B is set to H level), and the equalizing switch 440 is turned OFF. As a result, the sense lines SEN and SENB are driven by the first and second differential amplifiers 411 and 412, a potential difference is generated between the sense lines SEN and SENB, and this potential difference starts to increase. Accordingly, a potential difference also occurs between the output bit line OUT short-circuited to the sense line SENB via the N-channel transistor 432 and the output bit line OUTB short-circuited to the sense line SEN via the N-channel transistor 433. And this potential difference begins to increase.

  Next, the enable signal EN2 is raised to H level (enable signal EN2B is lowered to L level) with a delay of a predetermined time t2 from the cancellation of the equalizing signal EQ2, the flip-flop 431 is activated, and the output bit Lines OUT and OUTB are disconnected from sense lines SENB and SEN, respectively. At this time, a sufficient potential difference (usually about 300 mV) is generated between the output bit lines OUT and OUTB. Therefore, positive feedback for increasing the potential difference is performed between the two CMOS inverters 431a and 431b of the flip-flop 431. One of the output bit lines OUT and OUTB is at the H level (= VDD), and the other is at the L level (= VSS). As described above, the flip-flop 431 is activated by the enable signal EN2 to amplify and hold the potential difference generated between the output bit lines OUT and OUTB to a sufficient level.

  The above is the normal read access operation in the SRAM. A feature of the semiconductor integrated circuit for process evaluation according to the present embodiment is that a circuit that prevents the sense amplifier from performing such normal read access and increases the difficulty of normal read access is provided. More specifically, the first feature of the present embodiment resides in load circuits 413 and 414 having a function of adjusting the weight of a load connected to the bit lines DL and DLB during read access.

  When all of the load adjustment signals T1B, T2B, and T3B applied to the load circuits 413 and 414 are at the H level, after the precharge signal Pre and the equalizing signal EQ1 are released, the ON-state transistors connected to the global bit lines DL and DLB are There is no one. Therefore, for example, when the N channel transistor N1 is ON in the memory cell to be accessed, the load of the N channel transistor N1 is only the stray capacitance of the bit line BL and the global bit line DL. Therefore, after the equalizing signal EQ1 is canceled, the potential of the global bit line DL decreases with a large gradient, and the potential difference between the global bit lines DL and DLB at the rising edge of the enable signal EN1 is the first and second differentials. The amplifiers 411 and 412 are large enough to operate normally.

  However, for example, when the load adjustment signal T1B is set to L level, one P channel transistor in the load circuit 413 is connected to the global bit line DL after the precharge signal Pre and the equalizing signal EQ1 are released, and the load circuit 414 One P-channel transistor is connected to the global bit line DLB. Therefore, for example, when the N channel transistor N1 is ON in the memory cell to be accessed, the drain current of one P channel transistor in the load circuit 413 flows into the N channel transistor N1, so that much. The driving capability of the N-channel transistor N1 that can be used to discharge the charged charges of the global bit line DL and the bit line BL is reduced. Therefore, the gradient of the potential of the global bit line DL after the cancellation of the equalizing signal EQ1 is reduced, and the potential difference between the global bit lines DL and DLB at the rising edge of the enable signal EN1 is that all of the load adjustment signals T1B, T2B, T3B are H Compared to the level, it becomes smaller.

  Further, for example, when the load adjustment signal T2B is also set to the L level in addition to the load adjustment signal T1B, two P-channel transistors in the load circuit 413 are connected to the global bit line DL, and 2 in the load circuit 414 is set. P channel transistors are connected to global bit line DLB. Accordingly, the gradient of the potential of the global bit line DL or DLB after the cancellation of the equalizing signal EQ1 is further reduced, and the potential difference between the global bit lines DL and DLB at the rising edge of the enable signal EN1 is that only the load adjustment signal T1B is at the L level. It is even smaller than some cases. When all of the load adjustment signals T1B, T2B, and T3B are at the L level, the potential difference between the global bit lines DL and DLB at the rise of the enable signal EN1 is that the load adjustment signals T1B and T2B are at the L level. It is even smaller than the case.

  As the number of P-channel transistors in the load circuits 413 and 414 connected to the global bit lines DL and DLB is increased in this way, the burden on the N-channel transistor N1 or N2 of the memory cell to be accessed during read access increases. When there is a memory cell in the SRAM cell array 100 (see FIG. 1) where the drive capability of the N-channel transistor N1 or N2 is low, the read access to the memory cell is likely to fail.

  Therefore, in this embodiment, by setting various load adjustment signals T1B, T2B, and T3B, the load on the memory cell is increased stepwise, and the read access to each memory cell of the SRAM cell array 100 is normally performed under each load condition. Make a measurement to see if it is done. By performing such a measurement, it is possible to find a deficiency in driving capability of some memory cells that cannot be found in a light load state. In addition, a memory cell that lacks such driving capability is found, the characteristics of the transistors that make up the memory cell are measured, and the results are used to adjust the process conditions. The process conditions of the semiconductor manufacturing process can be optimized so that the semiconductor integrated circuit can be manufactured with a high yield.

  The second feature of the present embodiment is that the SRAM is provided with timing control means for variably controlling the generation timing of the internal control signal for read access. More specifically, the enable signal EN1 is released from the cancellation of the equalizing signal EQ1. This is in that a function for adjusting the interval time t1 until start-up is provided. When the interval time t1 is short, a sufficient potential difference does not occur between the global bit lines DL and DLB when the enable signal EN1 rises when the drive capability of the N-channel transistor N1 or N2 of the memory cell to be accessed is low. , Read access is likely to fail. Therefore, in the present embodiment, measurement is performed to determine whether or not read access to each memory cell of the SRAM cell array 100 is normally performed under the condition of each interval time t1 while the interval time t1 is shortened stepwise, for example. . By performing such a measurement, it is possible to find deficiencies in the drive capability of some memory cells that cannot be found when the interval time t1 is long.

  Further, when the interval time t1 is shortened, not only the subtle deficiency of the driving capability of the memory cell but also the variation in the wiring resistance of the bit lines BL and BLB can be easily detected. More specifically, in the SRAM chip, the wiring resistance of the bit line between the memory cell located near the sense amplifier and the sense amplifier is small, but the memory cell located far from the sense amplifier and the sense amplifier The wiring resistance of the bit line between them is large. In addition, there is a variation in the wiring width of the bit line. When the wiring width of the bit line is wide, the wiring resistance is low, and when the wiring width is narrow, the wiring resistance is high. In this way, when the wiring resistance of the bit line varies, if the interval time t1 is shortened, when data is read from the memory cell connected to the sense amplifier via the high wiring resistance, the enable signal EN1 rises. A sufficient potential difference does not occur between the global bit lines DL and DLB, and the possibility that read access will fail increases. Therefore, it is possible to easily investigate the variation in the wiring resistance of the bit line by shortening the interval time t1 and reading data from the memory cell.

  The third feature of the present embodiment is that the SRAM is provided with other timing control means for variably controlling the generation timing of the internal control signal for read access, more specifically, from the cancellation of the equalizing signal EQ2. This is in that a function for adjusting the interval time t2 until the rise of the enable signal EN2 is provided. When the interval time t2 is short, for example, when the driving capability of the differential amplifier 411 or 412 is low, a sufficient potential difference does not occur between the sense lines SEN and SENB at the rise of the enable signal EN2, and the read access ends in failure. The possibility increases. Therefore, in the present embodiment, measurement is performed to determine whether or not read access to each memory cell of the SRAM cell array 100 is normally performed under the condition of each interval time t2 while shortening the interval time t2 stepwise, for example. . By performing such measurement, it is possible to find a read access failure that cannot be found when the interval time t2 is long.

  Next, a circuit configuration example for realizing the first to third features will be described. In the present embodiment, a control circuit 900a shown in FIG. 9 is provided as a control circuit (corresponding to the control circuit 900 in the first embodiment) for generating an internal control signal for write access and read access. In this example, the control circuit 900a is a control circuit for a synchronous SRAM, and is supplied with a clock CLK for instructing the synchronization timing. The control circuit 900a is supplied with a mode designation signal MODE composed of a plurality of bits and delay time signals T1 and T2. In the present embodiment, one of the following modes is designated by setting each bit of the mode designation signal MODE.

(1) Normal mode This normal mode is a normal operation mode of the SRAM. In this normal mode, the load adjustment signals T1B, T2B, T3B are all set to an inactive level (H level in this example). The interval times t1 and t2 shown in FIG. 8 are fixed to a standard length that enables stable and normal read access.

(2) Variable load mode In this variable load mode, at least one of the load adjustment signals T1B, T2B, T3B is set to an active level (in this example, L level). More specifically, the load variable mode includes a first mode in which only the load adjustment signal T1B is at an active level, a second mode in which the load adjustment signals T1B and T2B are at an active level, a load adjustment signal T1B, All of T2B and T3B are divided into the third mode in which the active level is set. Whether the operation mode is the first to third modes is determined by the value of each bit of the mode signal MODE.

In the load circuit 413 (414) shown in FIG. 7B, when the size of each transistor to which the load adjustment signals T1B, T2B, and T3B are applied is different (that is, when the weight as the load is different), the mode is changed. Depending on the setting of each bit of the signal MODE, the signal values of the load adjustment signals T1B, T2B, and T3B may be changed as follows. In the following example, the weights of the respective transistors to which the load adjustment signals T1B, T2B, and T3B are applied are 1, 2, and 4, respectively.
<Each mode composing load variable mode>
T1B T2B T3B Total load weight
L H H 1
H L H 2
L L H 3
H H L 4
L H L 5
H L L 6
L L L 7

(3) Internal Timing Variable Mode This internal timing variable mode is a mode for changing the interval times t1 and t2 shown in FIG. More specifically, in the state where the internal timing variable mode is designated by the mode designation signal MODE, the control circuit 900a sets the interval time t1 to the length designated by the delay time signal T1, and sets the interval time t2 by the delay time signal T2. The specified length.

(4) External Timing Input Mode This external timing input mode is a mode in which each externally applied signal is output as enable signals EN1 and EN2. More specifically, in a state where the external timing input mode is designated by the mode designation signal MODE, the control circuit 900a outputs a specific bit signal of the delay time signal T1 as the enable signal EN1, and a specific bit of the delay time signal T2. Is output as an enable signal EN2. Therefore, in this external timing input mode, the interval time t1 shown in FIG. 8 can be arbitrarily adjusted by adjusting the timing of the rising edge of the signal of the specific bit of the delay time signal T1 given from the outside. Further, the interval time t2 shown in FIG. 8 can be arbitrarily adjusted by adjusting the timing of the rising edge of the signal of the specific bit of the delay time signal T2 given from the outside.

  FIG. 10 shows a configuration example of a circuit for realizing the internal timing variable mode and the external timing input mode in the control circuit 900a. In this example, the delay unit 901 is a circuit that delays the clock CLK by a predetermined time and outputs it as the precharge signal Pre shown in FIG. The delay unit 902 is a circuit that delays the precharge signal Pre by a predetermined time and outputs it as the equalizing signal EQ1 shown in FIG. The delay unit 903 is a variable delay time circuit. When the internal timing variable mode is designated by the mode designation signal MODE, the delay unit 903 delays the equalizing signal EQ1 by the interval time t1 designated by the delay time signal T1, It outputs as the enable signal EN1 shown in FIG. The delay unit 903 outputs a signal of a specific bit of the delay time signal T1 as the enable signal EN1 when the external timing input mode is specified by the mode specifying signal MODE. The delay unit 904 is a circuit that delays the enable signal EN1 by a predetermined time and outputs it as the equalizing signal EQ2 shown in FIG. The delay unit 905 is a variable delay time circuit. When the internal timing variable mode is specified by the mode specifying signal MODE, the delay unit 905 delays the equalizing signal EQ2 by the interval time t2 specified by the delay time signal T2, It outputs as the enable signal EN2 shown in FIG. The delay unit 905 outputs a signal of a specific bit of the delay time signal T2 as the enable signal EN2 in a state where the external timing input mode is specified by the mode specifying signal MODE.

  As the delay units 903 and 905, for example, a configuration having a plurality of inverters and switching the number of inverters to function as a delay circuit according to the delay time signal T1 or T2 is conceivable.

<Third Embodiment>
In the present embodiment, the power supply system for the power supply voltage to the output stage circuit (inverter 202 in FIG. 2) of the row decoder 200 that generates the row selection voltage WL in the SRAM configuration of FIGS. Is separated from the power supply system of the power supply voltage. More specifically, in this embodiment, the power supply terminals VDD (C) and VSS (C) for the output stage circuit of the row decoder 200 are separated from the power supply terminals VDD and VSS for other circuits, and the power supply terminal VDD ( The row selection voltage can be arbitrarily adjusted by making the power supply voltage applied to C) and VSS (C) variable. Here, the output stage circuit (inverter 202 in FIG. 2) is preferably a level shifter.

  In the present embodiment, for example, the write access and the read access to each memory cell are performed while changing the power supply voltage of the power supply terminal VDD (C), that is, the H level (= VDD (C)) of the row selection voltage stepwise. . Here, if each memory cell constituting the SRAM cell array 100 has a threshold voltage of the transistor Ta1 or Ta2 (see FIG. 3) is high or a mutual conductance gm is small and the driving capability is insufficient, the row selection is performed. When the voltage value of the H level is lowered, the possibility that the write access and read access to such a memory cell will fail increases. Therefore, a memory cell in which such write access or read access has failed and a memory cell that is not so are identified, and the characteristics of the transistors of both memory cells are measured and compared. Also in this embodiment, the same effect as the first embodiment and the second embodiment can be obtained.

  Instead of supplying the voltage supplied to the circuit for outputting the row selection voltage from the outside of the SRAM in this way, a step-down circuit for stepping down the power supply voltage or a step-up circuit for stepping up the power supply voltage is provided in the chip. The step-down or boosted power supply voltage may be supplied to a circuit that outputs a row selection voltage.

<Fourth embodiment>
In this embodiment, the power supply voltage supply system of the circuit for precharging the bit lines DL and DLB is separated from the power supply voltage supply system for other circuits in the SRAM configuration of FIG. More specifically, in this embodiment, the power supply terminal VDD (C) for the circuit that generates the precharge voltage is supplied to the power supply terminal VDD (C) separately from the power supply terminals VDD for other circuits. By making the power supply voltage variable, the precharge voltage can be arbitrarily adjusted.

  In this embodiment, for example, read access to each memory cell is performed while changing the precharge voltage stepwise. Here, in the case where each of the memory cells constituting the SRAM cell array 100 has insufficient driving capability of the transistor N1 or N2 (see FIG. 3), if the voltage value of the precharge voltage is lowered, At the time of read access to the memory cell, a sufficient potential difference does not occur between the bit lines DL and DLB after the precharge and the equalization of the bit line pair are canceled, and there is a high possibility that the read access will fail. Therefore, the memory cell in which such read access has failed and the memory cell that is not so are identified, and the characteristics of the transistors of both memory cells are measured and compared. Also in this embodiment, the same effect as the first to third embodiments can be obtained.

  Instead of supplying the voltage supplied to the circuit for outputting the precharge voltage from the outside of the SRAM in this way, a step-down circuit for stepping down the power supply voltage or a step-up circuit for stepping up the power supply voltage is provided in the chip. The step-down or boosted power supply voltage may be supplied to a circuit that outputs a precharge voltage.

<Second application target example of the present invention>
FIG. 11 is a circuit diagram illustrating a configuration example of a mask ROM which is a second application target example of the invention. The mask ROM shown in FIG. 11 is a 16-bit width mask ROM and includes sense amplifiers 400′-0 to 400′-15 for outputting 16-bit read data Dout0 to Dout15. The mask ROM also includes 16 data storage areas 100′-0 to 100′-15 that store data of the 0th to 15th bits, respectively. Here, the storage area of the 0th bit is configured by memory cells M′ij-0 (i = 0 to m, j = 0 to n) in m + 1 rows and n + 1 columns. In the memory cell matrix M′ij-0 (i = 0 to m, j = 0 to n), for each column, m + 1 memory cells M′ij-0 (i = 0 to m) belonging to the column. One bit line BITj-0 is wired along the arrangement direction of n + 1, and for each row, along the arrangement direction of n + 1 memory cells M′ij-0 (j = 0 to n) belonging to the row. The word lines are wired. Each memory cell M′ij-0 is composed of one N-channel transistor, and the source of the N-channel transistor which is the memory cell M′ij-0 in the i-th row and j-th column is a low potential. The gate is connected to the i-th row word line. The state of the drain of the N-channel transistor that is the memory cell M′ij-0 in the i-th row and j-th column differs depending on whether the memory content of the memory cell is “0” or “1”. It is connected to the line BITj-0 or is open. The data storage area 100′-0 corresponding to the 0th bit has been described above, but the same applies to the data storage areas 100′-1 to 100′-15 corresponding to the 1st to 15th bits.

  Similar to the SRAM example described above, m + 1 row selection circuits 200-i (i = 0 to m) constitute a row decoder for decoding row addresses, and n + 1 column selection circuits 300-j (j = 0 to n) constitute a column decoder for decoding the column address. Each of the row selection circuits 200-i (i = 0 to m) is connected to the word line of each row of the memory cell matrix M'mn-0 to M'mn-15. By the action of these row selection circuits 200-i (i = 0 to m), the row selection voltage WLi ′ corresponding to the row number i ′ indicated by the row address among the row selection voltages WLi (i = 0 to m) for each row. Only the row selection voltage WL-i (i ≠ i ′) is set to the L level. This is the row selection operation performed by the row decoder.

  The column gate 700 ′ is an n + 1 pair of switches CGj-0 (a switch group corresponding to a memory cell matrix M′ij-0 (i = 0 to m, j = 0 to n) storing 0th bit data. j = 0 to n). The n + 1 switches CGj-0 (j = 0 to n) are each composed of an N-channel transistor. Here, each end of the switch CGj-0 (j = 0 to n) is connected to the bit line BITj corresponding to each column j of the memory cell matrix M′ij-0 (i = 0 to m, j = 0 to n). The other ends are commonly connected to the global bit line DL0 corresponding to the 0th bit, respectively. The column gate 700 ′ includes memory cell matrices M′ij−1 (i = 0 to m, j = 0 to n) to M′ij-15 (i = 0 to m, j = 0 to n). The configuration of these switch groups is the same as that of the switch group corresponding to the memory cell matrix M′ij-0 (i = 0 to m, j = 0 to n).

  The column selection circuit 300-j (j = 0 to n) includes memory cell matrices M′ij-0 (i = 0 to m, j = 0 to n) to M′ij-15 (i = 0 to m, j). = 0 to n), and the column selection voltage COLj is connected to each gate of switches (transistors) CGj-0 (j = 0 to n) to CGj-15 (j = 0 to n). (J = 0 to n) are supplied.

  The sense amplifiers 400′-0 to 400′-15 determine the magnitude of current flowing into each memory cell to be accessed through each of the global bit lines DL0 to DL15, thereby determining the data storage areas 100′-0 to 100′-0. Each read data from 100′-15 is determined, and the determination result is output as read data Dout0 to Dout15.

In general, in a mask ROM, a transistor having a minimum size is used as a memory cell, and the data storage areas 100′-0 to 100′-15 are configured by spreading the memory cells at an allowable limit. Therefore, the mask ROM can be scaled up, and a huge number of memory cells can be mounted on the mask ROM. Therefore, the semiconductor integrated circuit for process evaluation according to the present invention is optimal.
The fifth embodiment described below is an embodiment of a semiconductor integrated circuit for process evaluation in which the present invention is applied to a mask ROM.

<Fifth Embodiment>
In order for the read operation of the sense amplifiers 400′-0 to 400′-15 to be performed normally in the mask ROM of FIG. 11, the characteristics of the transistors of the memory cells connected to the bit lines must be normal. However, the influence of manufacturing variations appears on the characteristics of the transistors constituting the memory cell. FIG. 12 shows an example. In FIG. 12, the gate voltage VCG for a transistor which is a memory cell is shown, and the vertical axis shows the drain current Id of the transistor when a constant drain-source voltage is applied. Here, the characteristic 3 shows the characteristics of a standard transistor, the characteristics 1 and 5 show the characteristics when the threshold voltage Vth is abnormal, and the characteristics 2 and 4 are characteristics when the mutual conductance gm is abnormal. Is shown.

  Here, in order to determine which of the characteristics 1 to 5 the characteristics of the transistor apply, for example, the gate voltage for the transistor is changed to Va, Vb, and Vc shown in FIG. The current Id flowing through the transistor is compared with three types of reference currents Id1, Id2, and Id3, and Id belongs to a range of 0 to Id1, a range of Id1 to Id2, a range of Id2 to Id3, or a range exceeding Id3 May be determined using a sense amplifier.

  This determination method will be described with a specific example. It is assumed that the characteristic of the transistor is, for example, characteristic 3. In this case, assuming that the sense amplifier has a function of comparing and determining the drain current flowing through the transistor that is the memory cell to be accessed with each of the reference currents Id1 to Id3, when the gate voltage is Va, the drain current is greater than Id1. The sense amplifier outputs a determination result indicating that the drain current is between Id1 and Id2 when the gate voltage is Vb, and the sense amplifier outputs a determination result that the drain current is between Id1 and Id2 when the gate voltage is Vc. The sense amplifier outputs a determination result indicating that is over Id3. Thus, based on each determination result output from the sense amplifier, it can be determined that the characteristic of the transistor corresponds to characteristic 3.

  In the present embodiment, a first improvement for causing the sense amplifiers 400′-0 to 400′-15 to perform a comparison determination between the current flowing in the memory cell via the bit line and the above-described plurality of types of reference currents; The mask ROM is configured by adding the second improvement for making the row selection voltage (that is, the gate voltage for the memory cell transistor) output from the row selection circuit 200-i (i = 0 to m) variable. Thus, it is possible to determine whether the output current characteristic (gate voltage-drain current characteristic) of a transistor belongs to any one of the above characteristics 1 to 5 for a huge number of memory cells.

  First, the first improvement will be described. FIG. 13 shows an example of a general configuration of a sense amplifier (corresponding to the sense amplifiers 400'-0 to 400'-15 in FIG. 11) to be first improved. As illustrated in FIG. 13, the sense amplifier includes a differential amplifier 499.

  In FIG. 13, on the left side of the differential amplifier 499, a circuit that forms a current path for the memory cell M′ij to be accessed at the time of read access is illustrated. In other words, this circuit is composed of a load circuit 471, an N-channel transistor 472, a column gate switch CGj, and a memory cell M'ij that are inserted in series between the high-potential-side power supply VDD and the low-potential-side power supply VSS. Here, the load circuit 471 is a current mirror circuit composed of a P-channel transistor, and generates a comparison voltage SAIN depending on the drain current flowing in the memory cell M′ij. The N-channel transistor 472 has a predetermined bias voltage BIAS1 applied to its gate and is always ON.

  On the right side of the differential amplifier 499, a circuit for generating the reference voltage SAREF is shown. In other words, this circuit is composed of a load circuit 481, N-channel transistors 482 and 483, and a REF circuit 484 inserted in series between the high-potential power supply VDD and the low-potential power supply VSS. Here, the N-channel transistor 482 is a transistor having the same size as the N-channel transistor 472, and is supplied with the same gate voltage BIAS1 as that of the N-channel transistor 472. The N-channel transistor 483 is an N-channel transistor having the same size as the column gate switch CGj, and is supplied with the gate voltage COLREF at the same level as the column selection voltage COL applied to the switch CGj. The REF circuit 484 is a circuit that generates a reference current, and includes an N-channel transistor having the same size as the memory cell M′ij. The N-channel transistor constituting the REF circuit 484 has a current different from the drain current flowing through the memory cell M′ij when the memory cell M′ij is accessed (for example, 1 / of the current flowing through the standard memory cell M′ij). 2), a gate voltage WLREF at a level different from the row selection voltage WL is applied. The load circuit 481 is a current mirror circuit composed of a P-channel transistor, and generates a reference voltage SAREF depending on a drain current (that is, a reference current) flowing through the REF circuit 484.

  The differential amplifier 499 performs differential amplification between the comparison voltage SAIN generated by the load circuit 471 and the reference voltage SAREF generated by the load circuit 481. When the comparison voltage SAIN is lower than the reference voltage SAREF (ie, the current that flows from the load circuit 471 to the memory cell M′ij side is greater than the reference current that flows from the load circuit 481 to the REF circuit 484 side). Output signal OUTB is set to H level. Further, the differential amplifier 499 is configured such that when the comparison voltage SAIN is higher than the reference voltage SAREF (that is, the current flowing from the load circuit 471 to the memory cell M′ij side is greater than the reference current flowing from the load circuit 481 to the REF circuit 484 side). Is also small), the output signal OUTB is set to L level. Based on the output signal OUTB, signals corresponding to the read data Dout0 to Dout15 shown in FIG. 11 are generated. The differential amplifier 499 includes an N-channel transistor 499c between the connection point between the sources of the N-channel transistors 499a and 499b constituting the load circuit of the differential transistor pair and the low potential side power source VSS. A predetermined bias voltage BIAS2 is applied to the gate of N channel transistor 499c. The N-channel transistor 499c serves to adjust the operating point of the differential amplifier 499 so that the differential amplifier 499 performs differential amplification between the comparison voltage SAIN and the reference voltage SAREF with an optimum gain.

  In the present embodiment, in order to perform the first improvement, a load circuit 450 shown in FIG. 14 is provided in the mask ROM as the load circuit 471 in FIG. In this load circuit 450, the drains and gates of P-channel transistors 451 to 454 are commonly connected to the drain of N-channel transistor 472 in FIG. 13, and this common connection point serves as a node for generating comparison voltage SAIN. Yes. P channel transistors 455 to 458 are interposed between the sources of the P channel transistors 451 to 454 and the high potential side power supply VDD. Here, the precharge signal Pre and the current selection signals Id1B, Id2B, and Id3B are supplied to the gates of the P-channel transistors 455 to 458, respectively. These precharge signal Pre and current selection signals Id1B, Id2B, and Id3B are internal control signals generated for read access by a control circuit (not shown). In the present embodiment, this control circuit generates current selection signals Id1B, Id2B, and Id3B in accordance with a mode designation signal supplied from the outside of the mask ROM.

  The precharge signal Pre is set to the L level for a predetermined time after the column selection voltage COL is set to H level for read access to the memory cell M′ij and before the row selection voltage WL is set to H level. Is done. While this precharge signal Pre is at the L level, P channel transistors 455 and 451 are turned on, and global bit line DL and bit line BIT are charged to a precharge voltage (a voltage in the vicinity of power supply voltage VDD). While this precharge is performed, the current selection signals Id1B, Id2B, and Id3B are all set to the H level by the control circuit.

  When precharge signal Pre is set to H level and row selection voltage WL is set to H level, one of current selection signals Id1B, Id2B, and Id3B is set to L level. Which of the current selection signals Id1B, Id2B, and Id3B is set to the L level is determined based on the content of the mode designation signal supplied to the control circuit. When the current selection signal Id1B is set to the L level, the P-channel transistor 456 is turned on, so that the P-channel transistor 452 functions as a current mirror. When the current selection signal Id2B is at L level, the P channel transistor 453 functions as a current mirror, and when the current selection signal Id3B is at L level, the P channel transistor 454 functions as a current mirror. The ratio of the transistor sizes of the P-channel transistors 452, 453, and 454 serving as current mirrors is the ratio of the reference currents Id1: Id2: Id3 shown in FIG.

  Here, for simplicity, for example, the reference current value of the REF circuit 484 is Id1 in FIG. 12, and the size of the P channel transistor 452 in the load circuit 450 is the size of the P channel transistor constituting the current mirror in the load circuit 481. Is the same.

  First, it is assumed that the current selection signal Id1B is set to the L level during reading from the memory cell M′ij. At this time, when the current flowing from the P channel transistor 452 of the load circuit 450 into the memory cell M′ij is smaller than the reference current Id1 flowing from the load circuit 481 into the REF circuit 484, the comparison voltage SAIN is higher than the reference voltage SAREF. The output signal OUTB of the differential amplifier 499 becomes L level. On the other hand, when the current flowing into the former memory cell M′ij is larger than the latter reference current Id1, the comparison voltage SAIN is lower than the reference voltage SAREF, and the output signal OUTB of the differential amplifier 499 is H Become a level.

  Next, it is assumed that the current selection signal Id2B is set to the L level at the time of reading from the memory cell M′ij. In this case, in the load circuit 450, a P-channel transistor 453 having a transistor size Id2 / Id1 times that of the P-channel transistor 452 functions as a current mirror. Therefore, when the current flowing from the load circuit 450 to the memory cell M′ij is smaller than the reference current Id2 that is Id2 / Id1 times the reference current Id1 flowing from the load circuit 481 to the REF circuit 484, the comparison voltage SAIN is the reference voltage. It becomes higher than SAREF, and the output signal OUTB of the differential amplifier 499 becomes L level. On the other hand, when the former current is larger than the latter reference current Id2, the comparison voltage SAIN is lower than the reference voltage SAREF, and the output signal OUTB of the differential amplifier 499 becomes H level.

  Next, it is assumed that the current selection signal Id3B is set to the L level at the time of reading from the memory cell M′ij. In this case, in the load circuit 450, the P-channel transistor 454 having a transistor size Id3 / Id1 times that of the P-channel transistor 452 functions as a current mirror. Therefore, when the current flowing from the load circuit 450 into the memory cell M′ij is smaller than the reference current Id3, the output signal OUTB of the differential amplifier 499 becomes L level, and the former current is larger than the latter reference current Id3. The output signal OUTB of the differential amplifier 499 becomes H level.

  As described above, by using the load circuit 450 shown in FIG. 14, each of the reference currents Id1 to Id3 shown in FIG. 12 is compared with the current flowing in the memory cell M′ij, and the first improvement is made. Can be realized.

As modes for realizing the first improvement, the modes shown in FIGS. 15A, 15B, and 15C may be considered. In the embodiment shown in FIG. 15A, the source node BITREF of the N-channel transistor 483 shown in FIG. 13 is connected to a bonding pad, and a constant current source outside the mask ROM is connected to this bonding pad. One of the currents Id1, Id2, and Id3 is supplied to the load circuit 481 by the source. In the mode shown in FIG. 15B, a current supplied from an external constant current source via a bonding pad is led to a source node BITREF of an N channel transistor 483 via a current mirror 461 provided in the mask ROM. It is a configuration. The embodiment shown in FIG. 15C is different from the embodiment shown in FIG. 15B in that three resistors R1, R2, R3 and three P-channel transistors are provided inside the mask ROM instead of using an external constant current source. A constant current circuit 462 including 462a, 462b, and 462c is provided, and a constant current obtained from the constant current circuit is led to a source node BITREF of the N-channel transistor 483 through a current mirror. Here, the sources of the P-channel transistors 462a, 462b, and 462c are connected to a reference voltage source that generates a predetermined voltage, and the drains of the P-channel transistors 462a, 462b, and 462c have resistors R1, R2, and R3, respectively. Each is connected to a current mirror. Then, current selection signals Id1B, Id2B, and Id3B are given to the gates of the P-channel transistors 462a, 462b, and 462c, and any of the resistors R1, R2, and R3 is used as a constant current source that supplies current to the current mirror 461. Can be switched.
In any aspect, the same effect as the embodiment of FIG. 14 can be obtained.

  Next, the second improvement will be described. In the present embodiment, the row selection circuits 200-0 to 200-m in FIG. 11 are the objects of the second improvement. That is, in this embodiment, the configuration of each of the row selection circuits 200-1 to 200-m is shown in FIG. One row selection circuit 200 a shown in FIG. 16 includes a NAND gate 201 and a level shifter 210.

  The NAND gate 201 is supplied with a power supply voltage between the high-potential-side power supply VDD and the low-potential-side power supply VSS, and a row address given from an address input circuit (not shown) indicates a row associated with the row selection circuit 200a. When the output signal is an active level (VSS) and the row is not shown, the gate is an inactive level (VDD).

  The level shifter 210 includes N channel transistors 211 and 212 and P channel transistors 213 and 214. Here, the N-channel transistor 211 has a source connected to the low potential side power supply VSS and a gate connected to the output terminal of the NAND gate 201. The P-channel transistor 213 has a drain connected to the drain of the N-channel transistor 211 and a source connected to the row decoder power supply terminal PAD (WL). A connection point between the drains of the N-channel transistor 211 and the P-channel transistor 213 is a node for outputting the row selection voltage WL. N-channel transistor 212 is a transfer gate interposed between the output terminal of NAND gate 201 and the gate of P-channel transistor 213, and power supply voltage VDD is applied to the gate. The P-channel transistor 214 has a drain connected to the gate of the P-channel transistor 213, a source connected to the row decoder power supply terminal PAD (WL), and a gate supplied with a row selection voltage WL.

  In such a configuration, when the output signal of the NAND gate 201 is at an inactive level (VDD), the N-channel transistor 211 is turned on, so the P-channel transistor 214 is turned on and the P-channel transistor 213 is turned off. For this reason, the row selection voltage WL becomes an inactive level (VSS). On the other hand, when the output signal of the NAND gate 201 becomes the active level (VSS), the N-channel transistor 211 is turned OFF and the P-channel transistor 213 is turned ON, and the row selection voltage WL is at the active level, that is, the row decoder power supply terminal PAD (WL ) To the level of the power supply voltage VWL. Then, when the row selection voltage WL becomes the power supply voltage VWL, the P-channel transistor 214 is turned off.

  Thus, in the row selection circuit 200a, the active level of the row selection voltage WL becomes the power supply voltage VWL given from the outside via the row decoder power supply terminal PAD (WL). Therefore, if this row selection circuit 200a is employed as the row selection circuits 200-1 to 200-m in FIG. 11, the power supply voltage VWL applied to the row decoder power supply terminal PAD (WL) is, for example, Va, Vb, Vc in FIG. The row selection voltage WL applied to each memory cell M′ij (the gate voltage for the N channel transistor that is the memory cell M′ij) is Va, by performing read access to each memory cell M′ij while changing It can be changed like Vb and Vc.

  According to the present embodiment, by applying the first improvement and the second improvement described above to the mask ROM, the row selection voltage WL applied to each memory cell M′ij is changed to Va, Vb, Vc. On the other hand, read access is made to each memory cell M′ij, the current flowing through each memory cell M′ij is compared with the reference currents Id1, Id2, and Id3 in FIG. 12, and the comparison result is obtained. Can do. Such a measurement can be easily performed using an LSI tester. On the LSI tester side, the gate voltage-drain current characteristic of each memory cell M′ij is any one of characteristics 1 to 5 illustrated in FIG. 12 based on the comparison result obtained from the sense amplifier of the mask ROM. Can be determined. Such discrimination processing can be realized by causing an LSI tester to execute a simple program. As described above, according to the present embodiment, the type of the gate voltage-drain current characteristics of a huge number of memory cells constituting the mask ROM can be examined in a short time. As described above, since the gate voltage-drain current characteristics of a large number of transistors mounted on the mask ROM can be obtained in a short time, the manufacturing process conditions for manufacturing an LSI such as a mask ROM with a stable yield can be changed. Etc. can be performed quickly.

  In this embodiment, instead of supplying the voltage supplied to the circuit (level shifter 210) for outputting the row selection voltage from the outside of the mask ROM, a step-down circuit or power supply voltage for stepping down the power supply voltage in the chip of the mask ROM A booster circuit for boosting the voltage may be provided, and the power supply voltage stepped down or boosted by these may be supplied to a circuit for outputting the row selection voltage.

  In this embodiment, both the means for switching the reference currents Id1, Id2, and Id3 and the means for switching the row selection voltage are provided in the mask ROM. However, only one of them may be provided.

DESCRIPTION OF SYMBOLS 100 ... SRAM cell array, 200 ... Row decoder, 200-i (i = 0-m) ... Row selection circuit, 300 ... Column decoder, 300-j (j = 0-n) ... Column selection circuit, 400, 400'-0 to 400'-15 ... sense amplifier, 500 ... input / output buffer, 600 ... write circuit, 700 ... column gate, 800 ... address input circuit, 900, 900a ... control circuit , 100-0 to 100-n... Data storage area, Mij (i = 0 to m, j = 0 to n), M′ij (i = 0 to m, j = 0 to n). CGj (j = 0 to n), CGjB (j = 0 to n)... Switch, BITj (j = 0 to n), BITjB (j = 0 to n), BL, BLB... Bit line, DL, DLB , DL0 to DL15 ... Global bit line, 410 ... First stage amplifier, 430 ... Second stage amplifier, 420, 440 ... Equalizing switch, 413, 414, 471, 481, 450 ... Load circuit, 499 ... Differential amplifier, 484 ... REF circuit, 210 ... ... level shifter.

Claims (2)

When data is read from the memory cell, the row decoder that applies a row selection voltage that activates the transistor that constitutes the memory cell to be read, and the read data from the memory cell by comparing the current flowing through the memory cell with a reference current A process evaluation semiconductor integrated circuit having a mask read-only memory including a sense amplifier for determining whether the row selection voltage is switched when reading data from the memory cell. Semiconductor integrated circuit for evaluation. When data is read from the memory cell, the row decoder that applies a row selection voltage that activates the transistor that constitutes the memory cell to be read, and the read data from the memory cell by comparing the current flowing through the memory cell with a reference current In a semiconductor integrated circuit for process evaluation having a mask read-only memory having a sense amplifier that performs the above determination, means for switching the row selection voltage when reading data from the memory cell, and data from the memory cell A semiconductor integrated circuit for process evaluation, comprising means for switching the reference current at the time of reading .

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