JP2006332610A - Light emitting element and method of manufacturing same - Google Patents

Light emitting element and method of manufacturing same Download PDF

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JP2006332610A
JP2006332610A JP2006114877A JP2006114877A JP2006332610A JP 2006332610 A JP2006332610 A JP 2006332610A JP 2006114877 A JP2006114877 A JP 2006114877A JP 2006114877 A JP2006114877 A JP 2006114877A JP 2006332610 A JP2006332610 A JP 2006332610A
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Kazunori Hagimoto
和徳 萩本
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Shin Etsu Handotai Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emitting element which has a structure wherein a light emitting layer part and a Si substrate are laminated with a metal layer between them, and is hard to decrease lamination strength and reflection factor. <P>SOLUTION: A main metal layer 10c forming a reflecting surface is formed on a second principal surface of a compound semiconductor layer 50, and further a first brazing material layer 10s1 comprising an AuSn brazing material whose melting point is 364°C or below is so arranged as to coat the main metal layer 10c. A second brazing material layer 10s2 comprising AuSn brazing material whose melting point is 364°C or below is arranged on a first principal surface of a Si substrate 7. Then, the first brazing material layer 10s1 and the second brazing material layer 10s2 are piled and pressurized, and at the same time, heat treatment for lamination is performed for them at the temperature which is equal to or higher than the melting point of the AuSn brazing material and lower than 364°C, to bind and laminate the first brazing material layer 10s1 and the second brazing material layer 10s2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は発光素子の製造方法及び発光素子に関する。
The present invention relates to a method for manufacturing a light emitting element and a light emitting element.

特開平7−66455号公報JP-A-7-66455 特開2001−339100号公報JP 2001-339100 A

発光ダイオードや半導体レーザー等の発光素子に使用される材料及び素子構造は、長年にわたる進歩の結果、素子内部における光電変換効率が理論上の限界に次第に近づきつつある。従って、一層高輝度の素子を得ようとした場合、素子からの光取出し効率が極めて重要となる。例えば、AlGaInP混晶により発光層部が形成された発光素子は、薄いAlGaInP(あるいはGaInP)活性層を、それよりもバンドギャップの大きいn型AlGaInPクラッド層とp型AlGaInPクラッド層とによりサンドイッチ状に挟んだダブルへテロ構造を採用することにより、高輝度の素子を実現できる。このようなAlGaInPダブルへテロ構造は、AlGaInP混晶がGaAsと格子整合することを利用して、GaAs単結晶基板上にAlGaInP混晶からなる各層をエピタキシャル成長させることにより形成できる。そして、これを発光素子として利用する際には、通常、GaAs単結晶基板をそのまま基板として利用することも多い。しかしながら、発光層部を構成するAlGaInP混晶はGaAsよりもバンドギャップが大きいため、発光した光がGaAs基板に吸収されて十分な光取出し効率が得られにくい難点がある。この問題を解決するために、半導体多層膜からなる反射層を基板と発光素子との間に挿入する方法(例えば特許文献1)も提案されているが、積層された半導体層の屈折率の違いを利用するため、限られた角度で入射した光しか反射されず、光取出し効率の大幅な向上は原理的に期待できない。   As a result of many years of progress in materials and element structures used in light-emitting elements such as light-emitting diodes and semiconductor lasers, the photoelectric conversion efficiency inside the elements is gradually approaching the theoretical limit. Therefore, when an element with higher luminance is to be obtained, the light extraction efficiency from the element is extremely important. For example, in a light emitting device having a light emitting layer portion formed of AlGaInP mixed crystal, a thin AlGaInP (or GaInP) active layer is sandwiched between an n-type AlGaInP cladding layer and a p-type AlGaInP cladding layer having a larger band gap. By adopting a sandwiched double hetero structure, a high-luminance element can be realized. Such an AlGaInP double heterostructure can be formed by epitaxially growing each layer of an AlGaInP mixed crystal on a GaAs single crystal substrate by utilizing the lattice matching of the AlGaInP mixed crystal with GaAs. And when using this as a light emitting element, usually a GaAs single crystal substrate is often used as it is as a substrate. However, since the AlGaInP mixed crystal constituting the light emitting layer has a larger band gap than GaAs, the emitted light is absorbed by the GaAs substrate, and it is difficult to obtain sufficient light extraction efficiency. In order to solve this problem, a method (for example, Patent Document 1) in which a reflective layer made of a semiconductor multilayer film is inserted between a substrate and a light emitting element has also been proposed. Therefore, only light incident at a limited angle is reflected, and a significant improvement in light extraction efficiency cannot be expected in principle.

そこで、特許文献2をはじめとする種々の公報には、成長用のGaAs基板を剥離する一方、補強用の素子基板(導電性を有するもの:例えばSi基板)を、反射用のAu層を介して剥離面に貼り合わせる技術が開示されている。このAu層は反射率が高く、また、反射率の入射角依存性が小さい利点がある。   Therefore, in various publications including Patent Document 2, a GaAs substrate for growth is peeled off, while a reinforcing element substrate (having conductivity: for example, a Si substrate) is passed through a reflective Au layer. A technique for bonding to a release surface is disclosed. This Au layer has an advantage that the reflectivity is high and the dependency of the reflectivity on the incident angle is small.

しかしながら、上記の方法では、反射層をなすAu層を発光層部に貼り合せる際に、剥離や反射率の低下といった不具合が生じやすい問題があった。本発明の課題は、金属層を介して発光層部と素子基板とを貼り合せた構造を有し、かつ、貼り合せ強度や反射率の低下などが生じにくい構造の発光素子の製造方法と、それにより得られる発光素子とを提供することにある。   However, the above method has a problem in that when the Au layer constituting the reflective layer is bonded to the light emitting layer portion, problems such as peeling and a decrease in reflectance are likely to occur. An object of the present invention is to provide a method for manufacturing a light-emitting element having a structure in which a light-emitting layer part and an element substrate are bonded via a metal layer, and a structure in which a reduction in bonding strength and reflectance is unlikely to occur. It is to provide a light emitting element obtained thereby.

課題を解決するための手段及び発明の効果Means for Solving the Problems and Effects of the Invention

上記課題を解決するために、本発明の発光素子の製造方法は、
発光層部を有した化合物半導体層の第一主表面を光取出面とし、該化合物半導体層の第二主表面側に金属層を介して素子基板が結合され、該金属層の化合物半導体層との接合面が反射面を形成する発光素子の製造方法であって、
化合物半導体層の第二主表面に反射面を形成する主金属層を形成し、さらに該主金属層を覆う形でAuSn系ろう材からなる第一ろう材層を配置し、
他方、素子基板の第一主表面にAuSn系ろう材からなる第二ろう材層を配置し、
第一ろう材層と第二ろう材層とを重ね合わせ、その状態で加圧しつつAuSn系ろう材の融点よりも高く主金属層の融点よりも低い温度にて貼り合わせ熱処理することにより、それら第一ろう材層と第二ろう材層とを結合して貼り合せることを特徴とする。
In order to solve the above problems, a method for manufacturing a light-emitting device of the present invention includes:
The first main surface of the compound semiconductor layer having the light emitting layer portion is a light extraction surface, and an element substrate is bonded to the second main surface side of the compound semiconductor layer via a metal layer, and the compound semiconductor layer of the metal layer and Is a manufacturing method of a light emitting element in which the bonding surface forms a reflecting surface,
Forming a main metal layer forming a reflective surface on the second main surface of the compound semiconductor layer, and further disposing a first brazing material layer made of AuSn-based brazing so as to cover the main metal layer;
On the other hand, a second brazing filler metal layer made of AuSn brazing material is disposed on the first main surface of the element substrate,
By superposing the first brazing filler metal layer and the second brazing filler metal layer and applying pressure in that state, they are bonded and heat-treated at a temperature higher than the melting point of the AuSn brazing filler metal and lower than the melting point of the main metal layer. The first brazing filler metal layer and the second brazing filler metal layer are bonded and bonded together.

また、本発明の発光素子は、発光層部を有した化合物半導体層の第一主表面を光取出面とし、該化合物半導体層の第二主表面側に金属層を介して素子基板が結合され、該金属層の化合物半導体層との接合面が反射面を形成する発光素子であって、
化合物半導体層の第二主表面に反射面を形成する主金属層が形成され、さらに該主金属層を覆う形でAuSn系ろう材からなる第一ろう材層が配置され、
他方、素子基板の第一主表面にAuSn系ろう材からなる第二ろう材層が配置され、
第一ろう材層と第二ろう材層とが溶融形態で貼り合せ結合されてなることを特徴とする。
In the light emitting device of the present invention, the first main surface of the compound semiconductor layer having the light emitting layer portion is used as a light extraction surface, and the element substrate is bonded to the second main surface side of the compound semiconductor layer through the metal layer. A light-emitting element in which a bonding surface of the metal layer and the compound semiconductor layer forms a reflection surface,
A main metal layer that forms a reflective surface is formed on the second main surface of the compound semiconductor layer, and a first brazing material layer made of AuSn brazing material is disposed so as to cover the main metal layer,
On the other hand, a second brazing filler metal layer made of AuSn brazing material is disposed on the first main surface of the element substrate,
The first brazing filler metal layer and the second brazing filler metal layer are bonded and bonded in a molten form.

なお、本発明においてAuSn系ろう材は、Au又はSnの一方を主成分(50質量%以上)とし、他方を最も質量含有率の高い副成分としてなるろう材のことをいう。   In the present invention, the AuSn brazing material refers to a brazing material in which one of Au and Sn is a main component (50% by mass or more) and the other is a subcomponent having the highest mass content.

金属層を介してSi基板と化合物半導体層とを貼り合わせる際には、均一な貼り合わせ状態を得るために、金属層を介して素子基板と化合物半導体層とを重ね合わせた積層体を加圧しながら貼り合わせ熱処理することが有効である。しかし、加圧力が過度に高くなると、薄い化合物半導体層に割れやクラックなどを生じやすくなり、製品歩留まりが低下する問題を生じやすくなる。しかし、上記のように、AuSn系ろう材からなる第一ろう材層と第二ろう材層とを重ね合わせ、その状態でAuSn系ろう材の融点よりも高い温度に貼り合わせ熱処理温度を設定して貼り合わせを行なえば、それほど高い圧力を付与せずとも比較的低温で均一な貼り合わせ状態を得ることができ、製品歩留まりの向上に寄与する。   When bonding the Si substrate and the compound semiconductor layer through the metal layer, in order to obtain a uniform bonded state, the stacked body in which the element substrate and the compound semiconductor layer are stacked is pressed through the metal layer. It is effective to perform the heat treatment while bonding. However, when the applied pressure is excessively high, a thin compound semiconductor layer is likely to be cracked or cracked, and the product yield is liable to decrease. However, as described above, the first brazing filler metal layer and the second brazing filler metal layer made of AuSn brazing filler metal are overlapped, and in that state, the bonding heat treatment temperature is set to a temperature higher than the melting point of the AuSn brazing filler metal. If the bonding is performed, a uniform bonding state can be obtained at a relatively low temperature without applying a very high pressure, which contributes to an improvement in product yield.

本発明にて採用可能な素子基板は特に種別は限定されないが、特に貼り合わせ面の平坦性等を確保しやすく、かつ比較的安価な導電性基板として、Si基板を本発明に好適に採用できる。なお、Si基板に代えて、GaAs基板、GaP基板あるいはSiC基板など、他の半導体基板を採用することも可能である。さらに、素子基板を発光素子通電経路として使用する必要がない場合は、ガラス基板や石英基板等の絶縁性基板を使用することも可能である。   The type of element substrate that can be employed in the present invention is not particularly limited, but a Si substrate can be suitably employed in the present invention as a conductive substrate that is easy to ensure the flatness of the bonded surface and is relatively inexpensive. . Instead of the Si substrate, other semiconductor substrates such as a GaAs substrate, a GaP substrate, or a SiC substrate can be employed. Furthermore, when it is not necessary to use the element substrate as a light-emitting element energization path, an insulating substrate such as a glass substrate or a quartz substrate can be used.

素子基板としてSi基板を採用する場合、第一ろう材層と第二ろう材層とを構成するAuSnろう材の融点を364℃未満とすることが望ましい。この場合、貼り合わせ熱処理温度を364℃よりも低温に設定することで、AuSn系ろう材のAu成分とSi基板のSi成分との共晶反応が抑制され、貼り合わせ熱処理時にSi基板側から主金属層にSiが湧き上がって反射率を低下させる不具合も防止できる。   When an Si substrate is employed as the element substrate, it is desirable that the melting point of the AuSn brazing material constituting the first brazing material layer and the second brazing material layer be less than 364 ° C. In this case, by setting the bonding heat treatment temperature lower than 364 ° C., the eutectic reaction between the Au component of the AuSn brazing material and the Si component of the Si substrate is suppressed, and the main treatment from the Si substrate side is performed during the bonding heat treatment. It is also possible to prevent a problem that Si rises in the metal layer and lowers the reflectance.

なお、第一ろう材層と第二ろう材層との一方を融点364℃未満の低温AuSn系ろう材とし、他方を融点364℃以上の高温AuSn系ろう材として、貼り合わせ熱処理温度を、低温AuSn系ろう材の融点を超え高温AuSn系ろう材の融点未満に設定して貼り合せを行なうことも可能である。このようにすると、高温AuSn系ろう材側の溶融は抑制されるが、低温AuSn系ろう材の溶融により問題なく貼り合わを行なうことができる。特に、主金属層がAu系層とされる場合は、第一ろう材層を融点364℃以上の高温AuSn系ろう材とすることで、貼り合せ時に主金属層に接する側の第一ろう材層の溶融が抑制され、主金属層のろう材食われを抑制することができる。   One of the first brazing filler metal layer and the second brazing filler metal layer is a low-temperature AuSn-based brazing material having a melting point of less than 364 ° C., and the other is a high-temperature AuSn-based brazing material having a melting point of 364 ° C. or more. It is also possible to perform bonding by setting the melting point of the AuSn brazing material to be higher than the melting point of the high temperature AuSn brazing material. In this way, melting on the high temperature AuSn brazing material side is suppressed, but bonding can be performed without any problem due to melting of the low temperature AuSn brazing material. In particular, when the main metal layer is an Au-based layer, the first brazing filler metal layer is a high-temperature AuSn-based brazing material having a melting point of 364 ° C. or higher so that the first brazing material on the side in contact with the main metal layer at the time of bonding is used. Melting of the layer is suppressed, and the brazing material erosion of the main metal layer can be suppressed.

融点を364℃未満に設定したい場合、AuSn系ろう材は、例えば、Auを主成分(50質量%以上)としてSnを16質量%超27質量%未満にて含有するものを使用することができる。Snの含有量が16質量%以下になるか27質量%以上になると、いずれもAuSn系ろう材の融点がAu−Si共晶温度である364℃以上となり、AuSn系ろう材の溶融を前提とする貼り合わせ熱処理温度を該364℃未満に設定できなくなる場合がある。なお、AuSn系ろう材は、Snを主成分(50質量%以上)とするものであってもよく、Au、Sn以外に、AuSn系ろう材の更なる低融点化のために、Pb、Ga、Biなどの副成分を含有することも可能である。なお、前述のごとく、第一ろう材層と第二ろう材層との一方を融点364℃以上の高温AuSn系ろう材とする場合は、例えばSnを10質量%以上16質量%以下、あるいは27質量%以上35質量%以下の組成範囲に調整するとよい(残部Au)。   When it is desired to set the melting point to less than 364 ° C., for example, an AuSn brazing material containing Au as a main component (50% by mass or more) and containing Sn in an amount of more than 16% by mass and less than 27% by mass can be used. . When the Sn content is 16% by mass or less or 27% by mass or more, the melting point of the AuSn brazing material becomes 364 ° C. or more, which is the Au—Si eutectic temperature, and it is premised on the melting of the AuSn brazing material. In some cases, it is impossible to set the bonding heat treatment temperature below 364 ° C. The AuSn brazing material may contain Sn as a main component (50 mass% or more). In addition to Au and Sn, the AuSn brazing material may be made of Pb, Ga for further lowering the melting point of the AuSn brazing material. It is also possible to contain subcomponents such as Bi. As described above, when one of the first brazing filler metal layer and the second brazing filler metal layer is a high-temperature AuSn brazing filler having a melting point of 364 ° C. or higher, for example, Sn is 10% by mass to 16% by mass, or 27 It is good to adjust to the composition range of mass% or more and 35 mass% or less (remainder Au).

AuSn系ろう材をAu−Sn二元系合金として上記組成を採用する場合、貼り合わせ熱処理は、望ましくは(AuSn系ろう材の融点以上であって)280℃以上360℃以下にて行なうのがよい。貼り合わせ熱処理温度が280℃未満では、上記組成のAuSn系ろう材を溶融させることが不能となる。また、貼り合わせ熱処理温度を360℃以下とすることで、AuSn系ろう材へのSi基板からのSi拡散をより効果的に抑制できる。   When adopting the above composition as an Au-Sn binary alloy for an AuSn brazing material, the bonding heat treatment is desirably performed at a temperature of 280 ° C. or higher and 360 ° C. or lower (above the melting point of the AuSn brazing material). Good. If the bonding heat treatment temperature is less than 280 ° C., it becomes impossible to melt the AuSn brazing material having the above composition. Moreover, Si diffusion from the Si substrate to the AuSn brazing material can be more effectively suppressed by setting the bonding heat treatment temperature to 360 ° C. or less.

主金属層は、Au、Ag及びAlのいずれかを95質量%以上含有するものとすることで、AuSn系ろう材によるSi拡散ブロック効果とも相俟って、反射率の非常に良好な反射面が得られ、得られる発光素子の光取出効率向上に寄与する。   The main metal layer contains at least 95% by mass of any of Au, Ag and Al, and in combination with the Si diffusion blocking effect by the AuSn-based brazing material, the reflecting surface has a very good reflectivity. And contributes to the improvement of the light extraction efficiency of the resulting light-emitting element.

以下、本発明の実施の形態を添付の図面を参照して説明する。
図1は、本発明の一実施形態である発光素子100を示す概念図である。発光素子100は、素子基板としてn型Si単結晶よりなるSi基板7の第一主表面上に金属層10を介して発光層部24が貼り合わされた構造を有してなる。発光層部24は、ノンドープ(AlGa1−xIn1−yP(ただし、0≦x≦0.55,0.45≦y≦0.55)混晶からなる活性層5を、第一導電型クラッド層、本実施形態ではp型(AlGa1−zIn1−yP(ただしx<z≦1)からなるp型クラッド層6と、前記第一導電型クラッド層とは異なる第二導電型クラッド層、本実施形態ではn型(AlGa1−zIn1−yP(ただしx<z≦1)からなるn型クラッド層4とにより挟んだ構造を有し、活性層5の組成に応じて、発光波長を、緑色から赤色領域(発光波長(ピーク発光波長)が550nm以上670nm以下)にて調整できる。発光素子100においては、金属電極9側にp型AlGaInPクラッド層6が配置されており、金属層10側にn型AlGaInPクラッド層4が配置されている。なお、ここでいう「ノンドープ」とは、「ドーパントの積極添加を行なわない」との意味であり、通常の製造工程上、不可避的に混入するドーパント成分の含有(例えば1013〜1016/cm程度を上限とする)をも排除するものではない。
Embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 1 is a conceptual diagram showing a light emitting device 100 according to an embodiment of the present invention. The light emitting element 100 has a structure in which a light emitting layer portion 24 is bonded to a first main surface of a Si substrate 7 made of n-type Si single crystal as an element substrate via a metal layer 10. The light emitting layer portion 24 includes the active layer 5 made of a non-doped (Al x Ga 1-x ) y In 1-y P (where 0 ≦ x ≦ 0.55, 0.45 ≦ y ≦ 0.55) mixed crystal. , the first-conductivity-type cladding layer, in this embodiment the p-type cladding layer 6 made of p-type (Al z Ga 1-z) y in 1-y P ( except x <z ≦ 1), wherein the first conductivity type the second-conductivity-type cladding layer different from the clad layer, in this embodiment interposed by an n-type (Al z Ga 1-z) y in 1-y P ( except x <z ≦ 1) n-type cladding layer 4 made of According to the composition of the active layer 5, the emission wavelength can be adjusted in the green to red region (the emission wavelength (peak emission wavelength) is 550 nm or more and 670 nm or less). In the light emitting device 100, the p-type AlGaInP cladding layer 6 is disposed on the metal electrode 9 side, and the n-type AlGaInP cladding layer 4 is disposed on the metal layer 10 side. The term “non-doped” as used herein means “does not actively add dopant”, and contains a dopant component inevitably mixed in a normal manufacturing process (for example, 10 13 to 10 16 / cm 3). It is not excluded that the upper limit is about 3 ).

また、発光層部24のSi基板7に面しているのと反対側の主表面上には、AlGaAsよりなる電流拡散層20が形成され、その主表面の略中央に、発光層部24に発光駆動電圧を印加するための金属電極(例えばAu電極)9が、該主表面の一部を覆うように形成されている。電流拡散層20の主表面における、金属電極9の周囲の領域は、発光層部24からの光取出領域をなす。発光層部24と電流拡散層20とが化合物半導体層50を形成する。   In addition, a current diffusion layer 20 made of AlGaAs is formed on the main surface of the light emitting layer portion 24 opposite to the side facing the Si substrate 7, and the light emitting layer portion 24 is formed at the approximate center of the main surface. A metal electrode (for example, Au electrode) 9 for applying a light emission driving voltage is formed so as to cover a part of the main surface. A region around the metal electrode 9 on the main surface of the current diffusion layer 20 forms a light extraction region from the light emitting layer portion 24. The light emitting layer portion 24 and the current diffusion layer 20 form the compound semiconductor layer 50.

また、Si単結晶基板7の裏面にはその全体を覆うように金属電極(裏面電極:例えばAu電極である)15が形成されている。金属電極15がAu電極である場合、金属電極15とSi単結晶基板7との間には基板側接合合金化層として、AuSb合金とSiとを合金化したAuSb接合合金化層16が介挿される。なお、接合合金化層はSi基板との合金化により接触抵抗低減が可能なものであれば、特に材質は限定されない。例えば、Si基板としてp型Si基板を用いることも可能であるし、この場合は、Al又はAl合金からなる接合合金化層等を用いるのがよい。また、n型Si基板を用いる場合も、接合合金化層の材質はAuSb合金に限られるものではない。   Further, a metal electrode (back electrode: for example, an Au electrode) 15 is formed on the back surface of the Si single crystal substrate 7 so as to cover the entire surface. When the metal electrode 15 is an Au electrode, an AuSb bonding alloyed layer 16 obtained by alloying AuSb alloy and Si is interposed between the metal electrode 15 and the Si single crystal substrate 7 as a substrate-side bonding alloyed layer. It is. The bonding alloying layer is not particularly limited as long as the contact resistance can be reduced by alloying with the Si substrate. For example, a p-type Si substrate can be used as the Si substrate, and in this case, a bonded alloyed layer made of Al or an Al alloy is preferably used. Even when an n-type Si substrate is used, the material of the bonding alloying layer is not limited to the AuSb alloy.

Si単結晶基板7は、Si単結晶インゴットをスライス・研磨して製造されたものであり、その厚みは例えば100μm以上500μm以下である。そして、発光層部24に対し、金属層10を挟んで貼り合わされている。金属層10は、本実施形態では後述のAuSn系ろう材層10sと主金属層10cとからなる。   The Si single crystal substrate 7 is manufactured by slicing and polishing a Si single crystal ingot, and the thickness thereof is, for example, 100 μm or more and 500 μm or less. Then, the light emitting layer portion 24 is bonded with the metal layer 10 interposed therebetween. In this embodiment, the metal layer 10 includes an AuSn brazing filler metal layer 10s and a main metal layer 10c, which will be described later.

発光層部24と金属層10との間には、発光層部側接合合金化層としてAuGeNi接合合金化層32(例えばGe:15質量%、Ni:10質量%、残部AuよりなるAuGeNi接合金属層を発光層部24側の化合物半導体と合金化したものである)が形成されており、素子の直列抵抗低減に貢献している。AuGeNi接合合金化層32は、金属層10の主表面上に分散形成され、その形成面積率は1%以上25%以下である。また、Si単結晶基板7と金属層10との間には、Si単結晶基板7の第一主表面と接する形で、基板側接合合金化層としてのAuSb接合合金化層31(例えばSb:5質量%、残部AuよりなるAuSb合金を、基板7をなすSiと合金化したものである)が形成されている。ここでも、接合合金化層の材質はAuSb合金に限られるものではない。   Between the light emitting layer portion 24 and the metal layer 10, an AuGeNi bonding alloyed layer 32 (for example, Ge: 15% by mass, Ni: 10% by mass, and the remainder Au is used as the light emitting layer side bonding alloyed layer). The layer is alloyed with the compound semiconductor on the light emitting layer portion 24 side), which contributes to reducing the series resistance of the device. The AuGeNi bonding alloyed layer 32 is formed in a dispersed manner on the main surface of the metal layer 10 and has a formation area ratio of 1% to 25%. Further, between the Si single crystal substrate 7 and the metal layer 10, an AuSb bonding alloyed layer 31 (for example, Sb: as a substrate side bonding alloyed layer) is in contact with the first main surface of the Si single crystal substrate 7. An AuSb alloy made of 5% by mass and the balance Au is alloyed with Si forming the substrate 7). Again, the material of the bonding alloying layer is not limited to the AuSb alloy.

そして、該AuSb接合合金化層31の全面が、金属層10の一部をなすAuSn系ろう材層10sにより覆われている。該AuSn系ろう材層10sは、Auを主成分としてSnを16質量%超27質量%未満の範囲にて含有するものであり、厚さは50nm以上5μm以下である(本実施形態ではAu−Sn二元合金(Sn含有量:例えば20質量%)、厚さは600nm)である。そして、該AuSn系ろう材層10sの全面を覆う形で、これと接するように主金属層10c(金属層10の一部をなすものである)が配置されている。AuSn系ろう材層10sは、主金属層10c及びSi基板7側の接合合金化層31とそれぞれ接して配置されている。このAuSn系ろう材層10sは、後述のごとく、第一ろう材層10s1と第二ろう材層10s2とが溶融形態で一体化したものである。   The entire surface of the AuSb bonding alloyed layer 31 is covered with an AuSn brazing material layer 10 s that forms a part of the metal layer 10. The AuSn brazing filler metal layer 10s contains Au as a main component and Sn in a range of more than 16% by mass and less than 27% by mass, and has a thickness of 50 nm or more and 5 μm or less (in this embodiment, Au— Sn binary alloy (Sn content: for example, 20 mass%, thickness is 600 nm). A main metal layer 10c (which forms a part of the metal layer 10) is disposed so as to cover the entire surface of the AuSn brazing filler metal layer 10s. The AuSn brazing filler metal layer 10s is disposed in contact with the main metal layer 10c and the bonding alloying layer 31 on the Si substrate 7 side. As will be described later, the AuSn brazing filler metal layer 10s is obtained by integrating the first brazing filler metal layer 10s1 and the second brazing filler metal layer 10s2 in a molten form.

主金属層10cはAu、Ag又はAlを主成分とする金属、具体的には、Au、Ag又はAlの含有率が95質量%以上の金属からなる。該主金属層10cは反射面を形成し、発光層部24からの光は、光取出面側に直接放射される光に、主金属層10cによる反射光が重畳される形で取り出される。本実施形態において主金属層10cは、純AuもしくはAu含有率が95質量%以上のAu合金よりなるAu系主金属層とされている。主金属層10cの厚さは、反射効果を十分に確保するため、80nm以上とすることが望ましい。また、主金属層10cの厚さの上限には制限は特にないが、反射効果が飽和するため、コストとの兼ね合いにより適当に定める(例えば10μm程度)。   The main metal layer 10c is made of a metal containing Au, Ag, or Al as a main component, specifically, a metal having a content of Au, Ag, or Al of 95% by mass or more. The main metal layer 10c forms a reflection surface, and light from the light emitting layer portion 24 is extracted in a form in which light reflected directly from the light extraction surface is superimposed on light reflected by the main metal layer 10c. In the present embodiment, the main metal layer 10c is an Au-based main metal layer made of pure Au or an Au alloy having an Au content of 95% by mass or more. The thickness of the main metal layer 10c is preferably 80 nm or more in order to ensure a sufficient reflection effect. Moreover, although there is no restriction | limiting in particular in the upper limit of the thickness of the main metal layer 10c, since a reflective effect is saturated, it determines suitably by balance with cost (for example, about 10 micrometers).

なお、Si単結晶基板7と金属層10との間、及びSi単結晶基板7と裏面側の電極15との間に設けられる接合合金化層31,16は、前述のごとくAuSb合金に限られず、例えばAuSn合金で構成することもできる。特に、金属層10との間の接合合金化層31をAuSn合金で構成した場合、接合合金化層31自体がSi単結晶基板7側から金属層10側へのSi拡散を抑制する機能を発揮する場合がある。この場合、AuSn合金からなる接合合金化層31とは別に、上記のようにAuSnろう材層10sを設けることで、金属層10側へのSi拡散抑制効果がさらに改善されることとなる。   The bonded alloying layers 31 and 16 provided between the Si single crystal substrate 7 and the metal layer 10 and between the Si single crystal substrate 7 and the back-side electrode 15 are not limited to the AuSb alloy as described above. For example, an AuSn alloy can be used. In particular, when the bonding alloyed layer 31 between the metal layer 10 is made of an AuSn alloy, the bonding alloyed layer 31 itself exhibits a function of suppressing Si diffusion from the Si single crystal substrate 7 side to the metal layer 10 side. There is a case. In this case, by providing the AuSn brazing material layer 10s as described above separately from the bonding alloying layer 31 made of the AuSn alloy, the effect of suppressing the Si diffusion toward the metal layer 10 side is further improved.

以下、図1の発光素子100の製造方法について説明する。
まず、図2の工程1に示すように、発光層成長用基板をなす半導体単結晶基板であるGaAs単結晶基板1の主表面に、p型GaAsバッファ層2を例えば0.5μm、AlAsからなる剥離層3を例えば0.5μm、さらにp型AlGaAsよりなる電流拡散層20を例えば5μm、この順序にてエピタキシャル成長させる。また、その後、発光層部24として、1μmのp型AlGaInPクラッド層6、0.6μmのAlGaInP活性層(ノンドープ)5、及び1μmのn型AlGaInPクラッド層4を、この順序にエピタキシャル成長させる。
Hereinafter, a method for manufacturing the light emitting device 100 of FIG. 1 will be described.
First, as shown in Step 1 of FIG. 2, a p-type GaAs buffer layer 2 is made of, for example, 0.5 μm and AlAs on the main surface of a GaAs single crystal substrate 1 which is a semiconductor single crystal substrate forming a light emitting layer growth substrate. The peeling layer 3 is epitaxially grown in this order, for example, in the order of 0.5 μm, and the current diffusion layer 20 made of p-type AlGaAs is, for example, 5 μm. Thereafter, a 1 μm p-type AlGaInP cladding layer 6, a 0.6 μm AlGaInP active layer (non-doped) 5, and a 1 μm n-type AlGaInP cladding layer 4 are epitaxially grown in this order as the light emitting layer portion 24.

次に、工程2に示すように、接合合金化層32を形成済みの発光層部24を覆うように主金属層10cを形成し、さらに該主金属層10cを覆う形でAuSn系ろう材からなる第一ろう材層10s1を蒸着ないしスパッタ等により形成する。他方、工程3に示すように、別途用意したSi単結晶基板7(n型)の両方の主表面に、例えばAuSb接合金属層を形成し、100℃以上500℃以下の温度域で合金化熱処理を行なうことにより、AuSb接合合金化層31,16とする。そして、AuSb接合合金化層31上には、AuSn系ろう材からなる第二ろう材層10s2を蒸着ないしスパッタ等により形成する(第一ろう材層10s1と第二ろう材層10s2とは、いずれも融点364℃以下の同一組成のAuSn二元系合金(Sn含有量:例えば20質量%)からなる。また、各厚さは600nmである)。また、AuSb接合合金化層16上には裏面電極層15(例えばAu系金属よりなるもの)を形成する。以上の工程で各金属層は、スパッタリングあるいは真空蒸着等を用いて行なうことができる。   Next, as shown in step 2, the main metal layer 10c is formed so as to cover the light emitting layer portion 24 on which the bonding alloying layer 32 has been formed, and further from the AuSn brazing material so as to cover the main metal layer 10c. A first brazing filler metal layer 10s1 is formed by vapor deposition or sputtering. On the other hand, as shown in step 3, for example, an AuSb bonding metal layer is formed on both main surfaces of a separately prepared Si single crystal substrate 7 (n-type), and alloying heat treatment is performed in a temperature range of 100 ° C. to 500 ° C. To obtain AuSb bonding alloyed layers 31 and 16. Then, a second brazing filler metal layer 10s2 made of an AuSn-based brazing material is formed on the AuSb bonding alloyed layer 31 by vapor deposition or sputtering (the first brazing filler metal layer 10s1 and the second brazing filler metal layer 10s2 are either Is also made of an AuSn binary alloy (Sn content: for example, 20% by mass) having the same composition with a melting point of 364 ° C. or less. Each thickness is 600 nm. Further, the back electrode layer 15 (for example, made of Au-based metal) is formed on the AuSb bonding alloying layer 16. In the above steps, each metal layer can be formed by sputtering or vacuum deposition.

そして、工程4に示すように、第一ろう材層10s1と第二ろう材層10s2とを重ね合わせて圧迫して、ろう材の融点以上であって温度364℃未満、望ましくは280℃以上360℃以下、例えば300℃にて貼り合せ熱処理する。Si単結晶基板7は、第一ろう材層10s1と第二ろう材層10s2とを介して発光層部24に貼り合わせられる。また、第一ろう材層10s1と第二ろう材層10s2とは上記貼り合せ熱処理により一体化してAuSn系ろう材層10sとなる。   Then, as shown in Step 4, the first brazing filler metal layer 10s1 and the second brazing filler metal layer 10s2 are overlapped and pressed to have a temperature equal to or higher than the melting point of the brazing filler metal and lower than 364 ° C., preferably 280 ° C. to 360 °. Bonding heat treatment is performed at a temperature not higher than ° C., for example, 300 ° C. The Si single crystal substrate 7 is bonded to the light emitting layer portion 24 via the first brazing material layer 10s1 and the second brazing material layer 10s2. The first brazing filler metal layer 10s1 and the second brazing filler metal layer 10s2 are integrated by the bonding heat treatment to form an AuSn brazing filler metal layer 10s.

Au−Sn二元系ろう材の場合、Sn含有率が16質量%超27質量%未満の範囲で、融点がAu−Si二元共晶温度である364℃未満となり、Si基板からのろう材中へのSiの拡散を抑制しつつ第一ろう材層10s1と第二ろう材層10s2とを溶融させて貼り合わせを行なうことが可能となり、低温・低圧で均一な貼り合わせ状態を容易に実現することができる。また、Si単結晶基板7から主金属層10cに向けたSi成分の拡散が上記AuSn系ろう材層10sによりブロックされ、主金属層10c側へのSi成分の染み出しが効果的に阻止される。その結果、最終的に得られる主金属層10cの反射面が、Si成分拡散により汚染される不具合が防止される。   In the case of the Au—Sn binary brazing material, the Sn content is in the range of more than 16% by mass and less than 27% by mass, and the melting point is less than 364 ° C., which is the Au—Si binary eutectic temperature. The first brazing filler metal layer 10s1 and the second brazing filler metal layer 10s2 can be melted and bonded while suppressing the diffusion of Si into the inside, and a uniform bonding state can be easily realized at low temperature and low pressure. can do. Further, the diffusion of the Si component from the Si single crystal substrate 7 toward the main metal layer 10c is blocked by the AuSn brazing filler metal layer 10s, and the seepage of the Si component toward the main metal layer 10c is effectively prevented. . As a result, a problem that the reflection surface of the main metal layer 10c finally obtained is contaminated by Si component diffusion is prevented.

他方、ろう材が上記AuSn系ろう材でない場合は、第二ろう材層10s2を蒸着等により形成したりする際の熱履歴により、Si単結晶基板7からAuSb接合合金化金属層31を突き抜けてSiが拡散し、第二ろう材層10s2の最表面にそのSiが湧き上がることがある。この沸き上がったSiが酸化されると、第一ろう材層10s1と第二ろう材層10s2との貼り合わせが著しく阻害される場合がある。しかし、上記のようにろう材層をAuSn系ろう材層とすることで、第二ろう材層10s2の形成時においても、その熱履歴による該Siの湧き上がりひいては酸化が効果的に阻止され、第一ろう材層10s1と第二ろう材層10s2とによるSi単結晶基板7と発光層部(化合物半導体層)24との貼り合せ強度をより高めることができる。   On the other hand, when the brazing material is not the AuSn-based brazing material, the AuSb bonding alloyed metal layer 31 penetrates from the Si single crystal substrate 7 due to the thermal history when the second brazing material layer 10s2 is formed by vapor deposition or the like. Si may diffuse and the Si may spring up on the outermost surface of the second brazing material layer 10s2. When the heated Si is oxidized, the bonding of the first brazing filler metal layer 10s1 and the second brazing filler metal layer 10s2 may be significantly inhibited. However, by forming the brazing filler metal layer as described above as an AuSn brazing filler metal layer, even when the second brazing filler metal layer 10s2 is formed, the Si upwelling due to its thermal history and the oxidation is effectively prevented, The bonding strength between the Si single crystal substrate 7 and the light emitting layer part (compound semiconductor layer) 24 by the first brazing material layer 10s1 and the second brazing material layer 10s2 can be further increased.

また、上記工程では、第一ろう材層10s1と第二ろう材層10s2とを溶融させて貼り合せを行なうので、貼り合わせの加圧力は、5kPa以上1000kPa以下で十分である。貼り合わせの加圧力をこのように低減できることで、貼り合せ処理時の発光層部24への割れやクラックの発生、特に、主金属層10cと発光層部24との間に配置される散点状の接合金属層32の周囲にクラックが発生する不具合を効果的に抑制でき、良好な発光特性を長期間にわたって維持することができる。   Moreover, in the said process, since 1st brazing filler metal layer 10s1 and 2nd brazing filler metal layer 10s2 are fuse | melted and bonded together, the applied pressure of bonding is 5 kPa or more and 1000 kPa or less is enough. By being able to reduce the pressure of the bonding in this way, cracks and occurrence of cracks in the light emitting layer portion 24 during the bonding process, in particular, scattered points arranged between the main metal layer 10c and the light emitting layer portion 24. It is possible to effectively suppress the occurrence of cracks around the metal bonding metal layer 32 and to maintain good light emission characteristics over a long period of time.

次に、工程5に進み、上記基板貼り合わせ体を、例えば10%フッ酸水溶液からなるエッチング液に浸漬し、バッファ層2と発光層部24との間に形成したAlAs剥離層3を選択エッチングすることにより、GaAs単結晶基板1(発光層部24からの光に対して不透明である)を、発光層部24とこれに接合されたSi単結晶基板7との積層体から剥離・除去する。なお、AlAs剥離層3に代えてAlInPよりなるエッチストップ層を形成しておき、GaAsに対して選択エッチング性を有する第一エッチング液(例えばアンモニア/過酸化水素混合液)を用いてGaAs単結晶基板1をGaAsバッファ層2とともにエッチング除去し、次いでAlInPに対して選択エッチング性を有する第二エッチング液(例えば塩酸:Al酸化層除去用にフッ酸を添加してもよい)を用いてエッチストップ層をエッチング除去する工程を採用することもできる。   Next, the process proceeds to step 5, and the substrate bonded body is immersed in an etching solution made of, for example, a 10% hydrofluoric acid aqueous solution, and the AlAs release layer 3 formed between the buffer layer 2 and the light emitting layer portion 24 is selectively etched. As a result, the GaAs single crystal substrate 1 (which is opaque to the light from the light emitting layer portion 24) is peeled and removed from the laminate of the light emitting layer portion 24 and the Si single crystal substrate 7 bonded thereto. . It should be noted that an etch stop layer made of AlInP is formed in place of the AlAs release layer 3, and a GaAs single crystal is used by using a first etching solution (for example, ammonia / hydrogen peroxide mixed solution) having selective etching properties with respect to GaAs. Etch and remove the substrate 1 together with the GaAs buffer layer 2 and then etch stop using a second etchant that has selective etching properties with respect to AlInP (for example, hydrochloric acid: hydrofluoric acid may be added to remove the Al oxide layer) A step of etching away the layer can also be employed.

そして、工程6に示すように、GaAs単結晶基板1の剥離により露出した電流拡散層20の第一主表面の一部を覆うように、ワイヤボンディング用の電極9(ボンディングパッド:図1)を形成する。以下、通常の方法によりダイシングして半導体チップとし、これを支持体に固着してリード線のワイヤボンディング等を行なった後、樹脂封止をすることにより最終的な発光素子が得られる。   Then, as shown in step 6, an electrode 9 for wire bonding (bonding pad: FIG. 1) is provided so as to cover a part of the first main surface of the current diffusion layer 20 exposed by peeling of the GaAs single crystal substrate 1. Form. Thereafter, the semiconductor chip is diced by a usual method, and this is fixed to a support and wire bonding of a lead wire is performed, followed by resin sealing to obtain a final light emitting element.

なお、第一ろう材層10s1と第二ろう材層10s2との一方を融点364℃未満の低温AuSn系ろう材とし、他方を融点364℃以上の高温AuSn系ろう材として、貼り合わせ熱処理温度を、低温AuSn系ろう材の融点を超え高温AuSn系ろう材の融点未満に設定して貼り合せを行なうことも可能である。得られる発光素子のAuSn系ろう材層10sは、第一ろう材層10s1と第二ろう材層10s2とが組成の異なるろう材層として識別されるが、その一方が溶融して貼り合された形態となることに変わりはない。   Note that one of the first brazing filler metal layer 10s1 and the second brazing filler metal layer 10s2 is a low-temperature AuSn brazing material having a melting point of less than 364 ° C., and the other is a high-temperature AuSn brazing material having a melting point of 364 ° C. or more. It is also possible to perform the bonding by setting the melting point of the low temperature AuSn brazing material to be higher than the melting point of the high temperature AuSn brazing material. The AuSn-based brazing filler metal layer 10s of the obtained light emitting element is identified as a brazing filler metal layer having a different composition between the first brazing filler metal layer 10s1 and the second brazing filler metal layer 10s2, but one of them is melted and bonded. There is no change in form.

特に、第一ろう材層10s1を融点364℃以上の高温AuSn系ろう材とすることで、貼り合せ時に主金属層10cに接する側の高温AuSn系ろう材からなる第一ろう材層10s1の溶融が抑制され、主金属層10cのろう材食われを抑制することができる。高温AuSn系ろう材は、Snを10質量%以上16質量%以下、あるいは27質量%以上35質量%以下のいずれかの範囲で含有するAu−Sn二元系ろう材で構成できる。特に、Snを27質量%以上35質量%以下(例えば30質量%)を含有するものを用いれば、ろう材中のAu含有量を低減でき、低コスト化を図ることができる。   In particular, the first brazing filler metal layer 10s1 is made of a high-temperature AuSn brazing material having a melting point of 364 ° C. or higher, so that the first brazing filler metal layer 10s1 made of the high-temperature AuSn brazing material on the side in contact with the main metal layer 10c at the time of bonding is melted. Is suppressed, and the brazing material erosion of the main metal layer 10c can be suppressed. The high-temperature AuSn brazing material can be composed of an Au—Sn binary brazing material containing Sn in a range of 10 mass% to 16 mass%, or 27 mass% to 35 mass%. In particular, if a material containing Sn in an amount of 27% by mass to 35% by mass (for example, 30% by mass) is used, the Au content in the brazing material can be reduced, and the cost can be reduced.

また、素子基板は、Si基板7に代えて、GaAs基板、GaP基板あるいはSiC基板など、他の半導体基板を採用することも可能である。さらに、素子基板を発光素子通電経路として使用する必要がない場合は、ガラス基板や石英基板等の絶縁性基板を使用することも可能である。   Further, the element substrate may be replaced with another semiconductor substrate such as a GaAs substrate, a GaP substrate, or a SiC substrate instead of the Si substrate 7. Furthermore, when it is not necessary to use the element substrate as a light-emitting element energization path, an insulating substrate such as a glass substrate or a quartz substrate can be used.

本発明の発光素子の第一実施形態を積層構造にて示す模式図。The schematic diagram which shows 1st embodiment of the light emitting element of this invention by laminated structure. 図1の発光素子の製造工程の一例を示す説明図。Explanatory drawing which shows an example of the manufacturing process of the light emitting element of FIG.

符号の説明Explanation of symbols

1 GaAs単結晶基板(発光層成長用基板)
4 n型クラッド層
5 活性層
6 p型クラッド層
7 Si単結晶基板(素子基板)
9 金属電極
10 金属層
10c 主金属層
10s AuSn系ろう材層
10s1 第一ろう材層
10s2 第二ろう材層
24 発光層部
100 発光素子
1 GaAs single crystal substrate (light emitting layer growth substrate)
4 n-type cladding layer 5 active layer 6 p-type cladding layer 7 Si single crystal substrate (element substrate)
DESCRIPTION OF SYMBOLS 9 Metal electrode 10 Metal layer 10c Main metal layer 10s AuSn type | system | group brazing filler metal layer 10s1 1st brazing filler metal layer 10s2 2nd brazing filler metal layer 24 Light emitting layer part 100 Light emitting element

Claims (8)

発光層部を有した化合物半導体層の第一主表面を光取出面とし、該化合物半導体層の第二主表面側に金属層を介して素子基板が結合され、該金属層の前記化合物半導体層との接合面が反射面を形成する発光素子の製造方法であって、
前記化合物半導体層の第二主表面に前記反射面を形成する主金属層を形成し、さらに該主金属層を覆う形でAuSn系ろう材からなる第一ろう材層を配置し、
他方、前記素子基板の第一主表面にAuSn系ろう材からなる第二ろう材層を配置し、
前記第一ろう材層と前記第二ろう材層とを重ね合わせ、その状態で加圧しつつ前記AuSn系ろう材の融点よりも高く前記主金属層の融点よりも低い温度にて貼り合わせ熱処理することにより、それら第一ろう材層と前記第二ろう材層とを結合して貼り合せることを特徴とする発光素子の製造方法。
The first main surface of the compound semiconductor layer having the light emitting layer portion is a light extraction surface, and an element substrate is bonded to the second main surface side of the compound semiconductor layer via a metal layer, and the compound semiconductor layer of the metal layer And a manufacturing method of a light emitting element in which a joint surface forms a reflective surface,
Forming a main metal layer that forms the reflective surface on the second main surface of the compound semiconductor layer, and further disposing a first brazing material layer made of AuSn-based brazing so as to cover the main metal layer;
On the other hand, a second brazing material layer made of AuSn-based brazing material is disposed on the first main surface of the element substrate,
The first brazing filler metal layer and the second brazing filler metal layer are overlaid and bonded and heat-treated at a temperature higher than the melting point of the AuSn brazing filler metal and lower than the melting point of the main metal layer while pressing in that state. Thus, the first brazing filler metal layer and the second brazing filler metal layer are bonded and bonded together.
前記素子基板がSi基板であり、前記第一ろう材層と前記第二ろう材層とを構成するAuSn系ろう材の融点がいずれも364℃未満である請求項1記載の発光素子の製造方法。   2. The method of manufacturing a light emitting element according to claim 1, wherein the element substrate is a Si substrate, and the melting point of the AuSn brazing material constituting the first brazing filler metal layer and the second brazing filler metal layer is less than 364 ° C. 3. . 前記AuSn系ろう材は、Auを主成分としてSnを16質量%超27質量%未満にて含有するものを使用する請求項1又は請求項2に記載の発光素子の製造方法。   The method for manufacturing a light-emitting element according to claim 1, wherein the AuSn brazing material contains Au as a main component and contains Sn in an amount of more than 16 mass% and less than 27 mass%. 前記AuSn系ろう材はAu−Sn二元合金からなり、前記貼り合わせ熱処理を280℃以上360℃以下にて行なう請求項3に記載の発光素子の製造方法。   The method for manufacturing a light-emitting element according to claim 3, wherein the AuSn brazing material is made of an Au—Sn binary alloy, and the bonding heat treatment is performed at 280 ° C. or higher and 360 ° C. or lower. 前記主金属層は、Au、Ag及びAlのいずれかを95質量%以上含有するものを使用する請求項1ないし請求項4のいずれか1項に記載の発光素子の製造方法。   5. The method for manufacturing a light-emitting element according to claim 1, wherein the main metal layer contains 95 mass% or more of any one of Au, Ag, and Al. 発光層部を有した化合物半導体層の第一主表面を光取出面とし、該化合物半導体層の第二主表面側に金属層を介して素子基板が結合され、該金属層の前記化合物半導体層との接合面が反射面を形成する発光素子であって、
前記化合物半導体層の第二主表面に前記反射面を形成する主金属層が形成され、さらに該主金属層を覆う形でAuSn系ろう材からなる第一ろう材層が配置され、
他方、前記素子基板の第一主表面にAuSn系ろう材からなる第二ろう材層が配置され、
前記第一ろう材層と前記第二ろう材層とが溶融形態で貼り合せ結合されてなることを特徴とする発光素子。
The first main surface of the compound semiconductor layer having the light emitting layer portion is a light extraction surface, and an element substrate is bonded to the second main surface side of the compound semiconductor layer via a metal layer, and the compound semiconductor layer of the metal layer A light-emitting element in which the joint surface forms a reflective surface,
A main metal layer that forms the reflective surface is formed on the second main surface of the compound semiconductor layer, and a first brazing material layer made of AuSn-based brazing material is disposed so as to cover the main metal layer,
On the other hand, a second brazing filler metal layer made of AuSn brazing material is disposed on the first main surface of the element substrate,
The light emitting device, wherein the first brazing filler metal layer and the second brazing filler metal layer are bonded and bonded in a molten form.
前記素子基板がSi基板である請求項6記載の発光素子。   The light emitting device according to claim 6, wherein the device substrate is a Si substrate. 前記AuSn系ろう材は、Auを主成分としてSnを16質量%超27質量%未満にて含有するものである請求項6又は請求項7に記載の発光素子。
The light emitting device according to claim 6 or 7, wherein the AuSn brazing material contains Au as a main component and Sn in an amount of more than 16% by mass and less than 27% by mass.
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