JP2006319089A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of high dimension accuracy in pattern. <P>SOLUTION: The semiconductor device comprises a semiconductor substrate 50, a trench formed in a p-well 70 on the main surface of the semiconductor substrate 50, a separation region 40 which is formed in the trench and comprises a defective embedding point 41, and an assist gate electrode 12 whose one part is formed on the separation region 40 and comprises an end on the defective embedding point 41. The assist gate electrode 12 comprises a thick wall T which is formed ticker than other part as embedded in the defective embedding point 41. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a buried pattern embedded in a groove and a manufacturing method thereof.

  In the field of semiconductor devices, a buried pattern provided in a trench is conventionally known. For example, an isolation region formed by embedding an insulating film in a trench, a buried wiring formed by embedding a conductive film, and the like are known.

  Japanese Patent Application Laid-Open No. 2005-85903 discloses a semiconductor device having a gate electrode as “another pattern” formed so as to reach an insulating film as an “embedded pattern” embedded in a trench.

By the way, it has been conventionally performed to increase the width of the remaining pattern (light-shielding pattern) of the photomask at the end portion thereof. Such techniques are described in, for example, JP-A-9-127676, JP-A-9-292701, and JP-A-11-258770.
JP 2005-85903 A Japanese Patent Laid-Open No. 9-127676 Japanese Patent Laid-Open No. 9-292701 JP 11-258770 A

  As shown in JP-A-2005-85903, when another pattern (upper layer pattern) is formed on the embedded pattern embedded in the groove and the upper layer pattern is formed by etching, the upper layer pattern is formed by etching. The length may shrink. At this time, the shrinkage amount (pattern retraction amount) varies on one semiconductor device. Therefore, the characteristics of the semiconductor device vary. Further, it is necessary to set a margin for pattern receding, and as a result, downsizing of the semiconductor device is hindered.

  JP-A-9-127676, JP-A-9-292701, and JP-A-11-258770 adjust the width of a light-shielding pattern in a photomask, and an upper layer pattern is formed in a defective portion of the embedded pattern. Embedding does not suppress shrinkage in the length direction of the upper layer pattern during etching.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having high pattern dimensional accuracy.

  A semiconductor device according to the present invention includes a semiconductor substrate having a main surface, a groove formed on the main surface, an embedded pattern formed in the groove and having a void, and at least a part of the embedded pattern formed on the embedded pattern. , And another pattern having an end portion on the void, and the other pattern has a thick portion formed thicker than the other portion by being embedded in the void.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a groove on a main surface of a semiconductor substrate, a step of forming an embedded pattern having a void in the groove, and an upper layer film on the embedded pattern from the void. Depositing, and patterning the upper layer film to form another pattern having a terminal portion on the void.

  According to the present invention, the recession of the pattern due to etching can be suppressed. As a result, variation in characteristics of the semiconductor device can be suppressed. Further, the dimensional accuracy of the pattern of the semiconductor device can be improved and the semiconductor device can be miniaturized.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below. Note that the same or corresponding portions are denoted by the same reference numerals, and the description thereof may not be repeated.

(Embodiment 1)
FIG. 1 is a top view showing a semiconductor device according to Embodiment 1 of the present invention.

  The semiconductor device 1 according to the present embodiment is an AG (Assist Gate) -AND type flash memory (nonvolatile semiconductor memory device), and includes a memory cell region having a memory cell array unit 10 and a peripheral circuit unit. In the memory cell array portion 10, a control gate electrode 11 as a word line and an assist gate electrode 12 are formed so as to be substantially orthogonal to each other. Here, among the control gate electrodes 11 arranged in the extending direction of the assist gate electrode 12, the outermost one is a dummy gate electrode (dummy word line) 1100.

  When a voltage is applied to the assist gate electrode 12, an inversion layer (not shown) is formed immediately below the assist gate electrode 12 on the semiconductor substrate. A common drain 20 and a selection MOS unit 30 are provided around the memory cell array unit 10. When the selection MOS unit 30 is turned on, the common drain 20 and the inversion layer below the assist gate electrode 12 are electrically connected. Connected. The assist gate electrode 12, the common drain 20, and the gate electrode 31 in the selection MOS portion 30 are connected to the upper layer wiring via the contact portions 12A, 20A, 31A, respectively. In the selection MOS section 30, impurity regions serving as the source / drain of the transistor and isolation regions 40 are formed alternately in the direction in which the gate electrode 31 extends. The isolation region 40 is a groove-type isolation region called STI (Shallow Trench Isolation) or SGI (Shallow Groove Isolation).

  FIG. 2 shows a II-II cross section in FIG. Referring to FIG. 2, n type buried region 60 and p well 70 are formed on semiconductor substrate 50. Assist gate electrode 12 and gate electrode 31 are formed on p well 70 via a gate insulating film 80 made of, for example, silicon oxide. On both sides of the gate electrode 31 in the p-well 70, an n− impurity region 71 and an n + impurity region 72 and an n− impurity region 73 as the common drain 20 are provided. A silicon nitride film 90 and an insulating film 100 are deposited on the assist gate electrode 12 and the gate electrode 31. In the memory cell array portion, an insulating film 110 having an ONO (Oxide-Nitride-Oxide) film structure is formed on the silicon nitride film 90. A control gate electrode 11 including a conductive film 11A and a silicide film 11B is formed on the insulating film 110, and an insulating film 120 is formed on the control gate electrode 11. An insulating film 130 is formed on the sidewalls of the gate electrode 31, the silicon nitride film 90 and the insulating film 100 and on the sidewalls of the control gate electrode 11 and the insulating film 120. An interlayer insulating film 140 is formed so as to cover the insulating films 100, 120, and 130, and upper layer wirings 12 </ b> D, 20 </ b> D, and 31 </ b> D are formed on the interlayer insulating film 140. Upper layer wirings 12D, 20D, 31D are electrically connected to assist gate electrode 12, n + impurity region 72 in common drain 20, and gate electrode 31 through contact portions 12A, 20A, 31A, respectively. The contact portions 12A, 20A, and 31A include contact holes 12B, 20B, and 31B and plugs 12C, 20C, and 31C provided in the contact holes, respectively.

  FIG. 3 shows a III-III cross section in FIG. Referring to FIG. 3, an insulating film 150 is formed on the sidewall of assist gate electrode 12. In addition, between each assist gate electrode 12, a floating gate electrode 13 that is an isolated pattern is provided on the p-well 70 via a gate insulating film 80. The floating gate electrode 13 and the conductive film 11A in the control gate electrode 11 are electrically insulated by the insulating film 110.

  FIG. 4 shows an IV-IV cross section in FIG. Note that FIG. 4 shows only the vicinity of portion A in FIG. Referring to FIG. 4, the end portion of isolation region 40 that is an embedding pattern has embedding failure portion 41 (concave portion). The conductive film constituting the assist gate electrode 12 is formed so as to reach the recess. In other words, the assist gate electrode 12 has a thick portion T that is formed thicker than other portions by being embedded in the poorly embedded portion 41 at the terminal portion thereof. A conductive film 1300 is formed on the isolation region 40. The conductive film 1300 is typically formed simultaneously with the conductive film constituting the floating gate electrode 13. An interlayer insulating film 140 is formed over the conductive film 1300.

Next, a process for forming the structure shown in FIG. 3 will be described with reference to FIGS.
Referring to FIG. 5, for example, phosphorus (P) is selectively implanted onto semiconductor substrate 50 using a commonly used ion implantation method or the like, so that n-type buried region 60 is formed. Then, for example, boron (B) is selectively implanted by a commonly used ion implantation method or the like, whereby the p-well 70 is formed. Further, for example, arsenic is implanted using a predetermined resist pattern as a mask, thereby forming n − impurity region 71 (see FIG. 2) connecting memory cell array portion and selection MOS portion 30. Gate insulating film 80 is formed on p well 70 and n-impurity region 71 (see FIG. 2) so as to have a silicon dioxide equivalent film thickness of, for example, about 8.5 nm. The gate insulating film 80 is formed by a thermal oxidation method such as an ISSG (In-Situ Steam Generation) oxidation method. Then, a conductive film 1200 made of polycrystalline silicon or the like is formed on the gate insulating film 80 using a CVD (Chemical Vapor Deposition) method or the like so as to have a thickness of about 50 nm. The conductive film 1200 becomes the gate electrode 31 and the assist gate electrode 12 in the selection MOS unit 30. Then, a silicon nitride film 90 having a thickness of about 70 nm is formed on the conductive film 1200. The silicon nitride film 90 is formed by a CVD method or the like.

  Referring to FIG. 6, an insulating film 100 made of a TEOS oxide film or the like is deposited on the silicon nitride film 90. A resist film 160 is formed on the insulating film 100 via a hard mask film (not shown) and an antireflection film (not shown). Then, using the hard mask film as a mask, the silicon nitride film 90 and the insulating film 100 are patterned as shown in FIG. Next, as shown in FIG. 8, the assist gate electrode 12 and the gate insulating film 80 are patterned. Further, as shown in FIG. 9, the insulating film 150 is formed on the sidewall of the insulating film 100 from the assist gate electrode 12, and the floating gate electrode 13 is formed in a region surrounded by the insulating film 150. Then, as shown in FIG. 10, the insulating film 100 and a part of the silicon nitride film 90 are removed. Further, an insulating film 110 (see FIG. 2) is formed so as to cover the floating gate electrode 13 from the silicon nitride film 90. The insulating film 110 has an oxide film-nitride film-oxide film laminated structure (ONO film structure) having thicknesses of about 5 nm, 8 nm, and 5 nm, respectively.

  Referring again to FIG. 2, conductive film 11A, silicide film 11B, and insulating film 120 are formed on insulating film 110, and these are patterned to form control gate electrode 11. The floating gate electrode 13 is also patterned, and the gate electrode 13 becomes an isolated pattern. Thereafter, an insulating film 130 and an interlayer insulating film 140 are formed, and contact portions 12A, 20A, and 31A reaching the assist gate electrode 12, the n + impurity region 72, and the gate electrode 31 from the interlayer insulating film 140 are provided. Thus, the upper wirings 12D, 20D, 31D are electrically connected to the assist gate electrode 12, the n + impurity region 72, and the gate electrode 31. Through the above steps, the structure shown in FIG. 3 is obtained.

  Next, a process for forming the structure shown in FIG. 4 will be described with reference to FIGS.

  Referring to FIG. 11, gate insulating film 80 is formed on p well 70. Then, a conductive film 1200A as a buffer layer made of polycrystalline silicon or the like is formed on the gate insulating film 80. Then, a silicon nitride film 90A as a hard mask layer is formed over the conductive film 1200A. Note that the conductive film 1200A (buffer layer) is not necessarily formed.

  Next, photoengraving is performed using the photomask shown in FIG. Referring to FIG. 12, the photomask 400 includes a light shielding pattern 410 and a light transmissive pattern 420. Here, the translucent pattern 420 has a shape corresponding to the separation region 40. In the photomask 400, pattern correction (OPC: Optical Proximity Correction) is not performed in which an auxiliary pattern is provided or the width of the translucent pattern 420 is increased at the end of the translucent pattern 420. That is, the translucent pattern 420 has the same shape as the other portions at the end portion.

  The formation region of the separation region 40 is patterned by photolithography using the photomask 400. Thereafter, by etching the hard mask (silicon nitride film 90A), removing the resist, and etching the p well 70, a trench (groove) 700 is formed on the p well 70 as shown in FIG. Trench 700 is formed to extend in the direction of arrow DR1.

Referring to FIG. 14, from the state shown in FIG. 13, SiO ₂ film 4000 is formed on silicon nitride film 90A from within trench 700. Here, the formation of the SiO ₂ film 4000 is performed using Ar process HDP-CVD. Then, a planarization process is performed on the SiO ₂ film 4000 by CMP (Chemical Mechanical Polishing) or the like. As a result, as shown in FIG. 15, the SiO ₂ film 4000 is buried in the groove 700, and the isolation region 40 is formed. Further, the silicon nitride film 90A and the conductive film 1200A are removed by wet etching.

By the way, as a result of forming the groove portion 700 using the photomask 400 shown in FIG. 12, the separation region 40 embedded in the groove portion 700 has a tapered shape with a thin tip portion (terminal portion) as shown in FIG. Have In the tapered portion, since the embedding property of the SiO ₂ film 4000 is inferior to other portions, an oxide film having a relatively high etching rate is formed.

Wet etching is performed on silicon nitride film 90A and conductive film 1200A. Referring to FIGS. 16 and 17, during this wet etching, a buried defective portion 41 is formed at the terminal portion of isolation region 40 (SiO ₂ film 4000).

  In other words, the isolation region 40 has a narrow portion 42 in which the pattern width is narrower than the design pattern width (B), and the embedding failure portion 41 is formed in the narrow portion 42.

  Referring to FIG. 18, conductive film 1200 made of polycrystalline silicon or the like is formed on isolation region 40 and gate insulating film 80 from the state shown in FIG. The conductive film 1200 is also formed in the buried defect portion 41 in the isolation region 40. Thereby, the thick part T is formed in the electrically conductive film 1200 in the said part. Then, a silicon nitride film 90 is formed over the conductive film 1200. Further, an insulating film 100 made of a TEOS oxide film or the like is deposited on the silicon nitride film 90. A resist film 160 is formed on the insulating film 100 via a hard mask film (not shown) and an antireflection film (not shown).

  Note that the conductive film 1200, the silicon nitride film 90, the insulating film 100, and the resist film 160 shown in FIG. 18 are typically respectively the conductive film 1200, the silicon nitride film 90, the insulating film 100, and the resist film 160 shown in FIG. It is formed simultaneously with the resist film 160.

  Referring to FIG. 19, etching is performed on insulating film 100, silicon nitride film 90 and conductive film 1200 from the state shown in FIG. As a result, the assist gate electrode 12 having a termination portion is formed on the isolation region 40. Here, the terminal portion of the assist gate electrode 12 is formed on a buried defect portion 41 in the isolation region 40. In other words, the assist gate electrode 12 is patterned so as to have a thick portion T at the end portion thereof. Further, an insulating film 150 is formed on the sidewall of the insulating film 100 from the assist gate electrode 12.

  By the way, when a pattern is formed by etching, an actually formed pattern length may be reduced (in the direction of the arrow DR1) with respect to an intended pattern length due to an action such as undercut. In the present specification, the pattern shrinkage is sometimes referred to as “pattern receding”.

  In the semiconductor device manufacturing process, layout design is performed with a margin for the above-described pattern recession amount. However, increasing the margin amount leads to an increase in chip area. On the other hand, if the variation in the pattern retraction amount is large, the margin amount must be set large.

  In contrast, in the semiconductor device according to the present embodiment, the terminal portion of assist gate electrode 12 has a thick portion T. By providing the thick portion T, pattern recession during etching is suppressed. Further, variations in pattern receding amount (variations in dimensions) are also suppressed. Therefore, it is possible to suppress the pattern receding and the variation in the receding amount when the assist gate electrode 12 is patterned.

  Note that the etching process for patterning the conductive film 1200 is typically hard mask etching using a hard mask film (not shown) formed over the insulating film 100 as a mask. Etching can also be performed using the resist film 160 as a mask. In this case, it is not necessary to form a hard mask film.

  Referring to FIG. 20, conductive film 1300 is formed on insulating film 150 from isolation region 40 from the state shown in FIG. 19. Then, an insulating film 110 is formed so as to cover the conductive film 1300 from the silicon nitride film 90. The insulating film 110 has an oxide film-nitride film-oxide film laminated structure (ONO film structure) having thicknesses of about 5 nm, 8 nm, and 5 nm, respectively. Further, a conductive film 11A and a silicide film 11B are formed on the insulating film 110.

  Note that the insulating film 110, the conductive film 11A, and the silicide film 11B shown in FIG. 20 are typically formed simultaneously with the insulating film 110, the conductive film 11A, and the silicide film 11B shown in FIG. 2, respectively. In addition, the insulating film 150 and the conductive film 1300 shown in FIG. 20 are typically formed simultaneously with the conductive films constituting the insulating film 150 and the floating gate electrode 13 shown in FIG.

  Referring to FIG. 4 again, insulating film 120 is formed on conductive film 11A and silicide film 11B. Then, the control gate electrode 11 is formed by patterning the conductive film 11A, the silicide film 11B, and the insulating film 120. Thereafter, an insulating film 130 and an interlayer insulating film 140 are formed. Through the above steps, the structure shown in FIG. 4 is obtained.

  Insulating films 120 and 130 and interlayer insulating film 140 shown in FIG. 4 are typically formed simultaneously with insulating films 120 and 130 and interlayer insulating film 140 shown in FIG.

  Next, the writing, reading and erasing operations of the flash memory will be described with reference to FIGS.

  At the time of data writing, a voltage is applied to a predetermined assist gate electrode 12. As a result, a predetermined memory cell (selected memory cell) is selected. The data writing is performed by a source side hot electron injection method. Thereby, efficient data writing is realized at high speed with low current. Each memory cell can store multi-value data. This multi-value storage is realized by changing the write time for each individual memory cell while keeping the write voltage applied to the control gate electrode constant, thereby forming memory cells having different threshold levels. For example, four or more values such as “00” / “01” / “10” / “11” can be stored. Therefore, the function of two or more memory cells can be realized with one memory cell. As a result, the flash memory can be downsized.

  In the data write operation, a voltage of about 15 V, for example, is applied to the control gate electrode 11 to which the selected memory cell is connected, and a voltage of, for example, about −2 V is applied to the other control gate electrode 11. Further, a voltage of about 5 V, for example, is applied to the assist gate electrode 12 for source formation in the selected memory cell, and the assist gate electrode 12 for drain formation (typically, for example, to the assist gate electrode 12 for source formation). A voltage of about 8 V, for example, is applied to the adjacent assist gate electrode 12). As a result, an inversion layer (not shown) serving as a source / drain is formed on the main surface (on the p well 70) of the semiconductor substrate 50 facing these assist gate electrodes 12. On the other hand, a voltage of about −2 V, for example, is applied to the assist gate electrode 12 other than the above, and no inversion layer is formed on the main surface of the semiconductor substrate 50 facing the assist gate electrode 12. . Thereby, isolation between the selected memory cell and the non-selected memory cell is performed. Further, a voltage of, for example, about 4.5 V is applied to the bit line connected to the inversion layer serving as the drain in the selected memory cell. Here, for example, a voltage of about 0 V is applied to the bit line connected to the inversion layer serving as the source in the selected memory cell, while the bit line connected to the inversion layer serving as the source in the non-selected memory cell is applied to For example, a voltage of about 2V is applied. As a result, in the selected memory cell, a write current flows from the drain to the source, and charges accumulated in the inversion layer on the source side are injected into the floating gate electrode 13 via the gate insulating film 80. On the other hand, in the non-selected memory cell, no current flows from the drain to the source, and no charge is injected into the floating gate electrode 13. Through the above operation, data is selectively written into a predetermined memory cell.

  In the data read operation, an operation opposite to the write operation is performed. Here, a voltage of about 2 to 5 V, for example, is applied to the control gate electrode 11 to which the selected memory cell is connected, and a voltage of about −2 V, for example, is applied to the other control gate electrode 11. Further, a voltage of about 4 V, for example, is applied to the assist gate electrode 12 for source / drain formation in the selected memory cell. Thereby, the source / drain in the selected memory cell is formed. On the other hand, a voltage of about −2 V, for example, is applied to the assist gate electrode 12 for forming the source / drain in the non-selected memory cell. As a result, in the non-selected memory cell, the inversion layer serving as the source / drain is not formed. As a result, isolation between the selected memory cell and the non-selected memory cell is realized. Here, a voltage of about 1 V, for example, is applied to the bit line to which the inversion layer serving as the drain in the selected memory cell is connected. On the other hand, a voltage of about 0 V, for example, is applied to the other bit lines. Further, a voltage of about 0 V, for example, is applied to the bit line connected to the inversion layer serving as the source in the selected memory cell. Here, the threshold voltage of the selected memory cell changes depending on the state of the accumulated charge in the floating gate electrode 13. Therefore, the data of the memory cell can be determined from the state of current flowing between the source and drain of the selected memory cell. With the above operation, a read operation can be performed on a multi-value storage memory cell.

  In the data erasing operation, a negative voltage (for example, about −16V) is applied to the word line to be selected, while a positive voltage is applied to the semiconductor substrate 50 (p well 70). Note that a voltage of about 0 V is applied to the assist gate electrode 12, and the inversion layer is not formed. As a result, charges are released from the floating gate electrode 13 to the semiconductor substrate 50. The emission is performed by FN (Fowler Nordheim) tunnel emission. With the above operation, data in a plurality of memory cells are erased collectively.

  The above contents are summarized as follows. That is, the semiconductor device 1 according to the present embodiment includes a semiconductor substrate 50 having a main surface, a trench 700 as a “groove portion” formed in a p-well 70 on the main surface of the semiconductor substrate 50, and a trench 700. An isolation region 40 (insulating film) as an “embedding pattern” having an embedded defective portion 41 as a “void” and a part thereof is formed on the isolated region 40, and a termination portion is formed on the embedded defective portion 41. And an assist gate electrode 12 (conductive film) as an “other pattern”. The assist gate electrode 12 has a thick portion T formed so as to be thicker than the other portions by being embedded in the embedding defect portion 41.

  According to the above configuration, since the end portion of the assist gate electrode 12 is formed to be relatively thick, pattern receding during etching and variations in the receding amount are reduced. As a result, variation in characteristics of the semiconductor device is suppressed. Further, the margin for pattern receding is set to be relatively small (for example, the length of the assist gate electrode 12 protruding on the separation region 40 is set to be relatively short, or “L” in FIG. 1 is set to be small). And the chip area is reduced.

  On the main surface of the semiconductor substrate 50, a portion where the trench 700 is formed constitutes a “first portion”, and a portion adjacent to the “first portion” constitutes a “second portion”. In the present embodiment, the assist gate electrode 12 is provided so as to reach the “second portion” from the “first portion”. As a modification, the entire “other pattern” may be formed on the “embedded pattern”.

  In the method of manufacturing the semiconductor device according to the present embodiment, the step of forming trench 700 on the main surface of semiconductor substrate 50 (FIG. 13) and formation of isolation region 40 having defective filling portion 41 in trench 700 are performed. 14 (FIGS. 14 to 17), a step (FIG. 18) of depositing a conductive film 1200 as an “upper layer film” on the isolation region 40 from within the poorly embedded portion 41, and a poorly embedded region by patterning the conductive film 1200. Forming an assist gate electrode 12 having a terminal portion on the portion 41 (FIG. 19).

  Then, the process of forming the trench 700 includes the process of forming a mask film (silicon nitride film 90A) having an opening corresponding to the trench 700 using the photomask 400 shown in FIG. 12, and the mask film as a mask. And the step of forming the isolation region 40 includes the step of depositing an insulating film 4000 as an “embedded film” on the silicon nitride film 90A from within the trench 700. 14), the step of filling the insulating film 400 in the trench 700 by reducing the thickness of the insulating film 4000 by CMP or the like (FIG. 15), and removing the silicon nitride film 90A and the like while forming the defective filling portion 41. Process (FIGS. 16 and 17).

  In the present embodiment, the embedding failure portion 41 is formed by providing the narrow portion 42 at the terminal portion of the separation region 40, but other than the terminal portion in the separation region 40 (for example, the central portion in the longitudinal direction). The embedding defect portion 41 may be formed by providing the narrow portion 42.

  According to the present embodiment, the above-described configuration can suppress the back-up of the assist gate electrode 12 during etching. As a result, the dimensional accuracy of the pattern of the semiconductor device can be improved, and variations in the characteristics of the semiconductor device can be suppressed. Further, the semiconductor device can be reduced in size.

(Embodiment 2)
21 and 22 are diagrams showing first and second steps in the manufacturing process of the semiconductor device according to the second embodiment, respectively. FIG. 23 is a top view showing the semiconductor device according to the present embodiment.

  Referring to FIG. 21, active region 74 is formed in advance on a part of “groove” where isolation region 40 as “embedded pattern” is formed on the main surface of the semiconductor substrate. As a result, when the oxide film constituting the isolation region 40 is formed using HDP-CVD, the region surrounded by the plurality (two) of active regions 74 and the edge of the isolation region 40 has three directions ( An oxide film grows from the direction of the arrow in FIG. As a result, an embedding defect portion 41 as a “void” occurs in the region.

  Referring to FIG. 22, gate electrode 14 as “another pattern” is formed so as to reach buried defect portion 41 in isolation region 40 from a position adjacent to isolation region 40. The gate electrode 14 is formed by forming a conductive film on the main surface of the semiconductor substrate on which the isolation region 40 is formed, and patterning the conductive film by etching. The gate electrode 14 has a terminal portion on the poorly embedded portion 41, and the terminal portion is formed thicker than the other portions by embedding the conductive film in the poorly embedded portion 41. Has been.

  Referring to FIG. 23, gate electrode 14 reaches on active region 74 adjacent to isolation region 40. The active region 74 is provided with a contact portion 74A.

  In the semiconductor device according to the present embodiment as well, since the thickness of the terminal portion of the gate electrode 14 is relatively large, the pattern receding during etching and the variation in the receding amount are similar to those in the first embodiment. Reduced. As a result, variation in characteristics of the semiconductor device is suppressed. In addition, the margin for pattern receding can be set relatively small, and the chip area is reduced.

  Further, in the present embodiment, the active region 74 (dummy active region) is intentionally formed in the isolation region 40, and the embedding defect portion 41 is positively generated in the vicinity thereof. That is, in the present embodiment, the step of forming the isolation region 40 as the “embedded pattern” includes the active region as the “dummy pattern” in a part of the groove (recess) formed on the main surface of the semiconductor substrate. And a step of depositing an insulating film as a “buried film” in the groove so as to form a buried defect portion 41 as a “void” between the active region 74 and the edge of the isolation region 40. And a step of embedding the insulating film in the groove by reducing the thickness of the insulating film. By doing in this way, the position where the embedding defect portion 41 is provided can be set relatively freely. As a result, layout flexibility in the semiconductor device is improved.

(Reference example)
FIG. 24 is a top view showing an element isolation structure according to a reference example. FIG. 25 is a sectional view taken along line XXV-XXV in FIG. Referring to FIGS. 24 and 25, in the element isolation structure according to the present reference example, the isolation region 40 which is an insulating film is formed on the active region 74 so as to be arranged substantially in parallel.

  FIG. 26 is a diagram in which gate electrodes are laid out on the element isolation structure shown in FIG. FIG. 26 shows a layout of design values. On the other hand, FIG. 27 is a diagram showing the gate electrode 14 actually formed.

  Referring to FIGS. 26 and 27, gate electrode 14 has a terminal portion on isolation region 40. Then, a narrow portion where the pattern width is narrower than the design pattern width is formed at the terminal portion of the gate electrode 14 (B portion in FIG. 27).

  FIG. 28 is an enlarged view showing the periphery of the terminal portion of the gate electrode shown in FIG. 29 and 30 are a cross-sectional view taken along XXIX-XXIX and a cross-sectional view taken along XXX-XXX in FIG. 28, respectively. Referring to FIGS. 28 to 30, the gate electrode 14 includes a conductive film 14A and a silicide film 14B. The gate length Lg at the terminal portion of the gate electrode 14 is relatively smaller than the gate length Lg ′ at other portions.

  FIG. 31 is a graph showing the relationship between the gate voltage Vg and the drain current Id. As shown in FIG. 31, when the gate length is small (Lg), the threshold voltage is lowered and the off-leakage current (Ioff) is increased due to the short channel effect as compared with the case where the gate length is large (Lg ′). . As a result, the originally designed transistor characteristics may not be obtained.

  Further, when the terminal portion of the gate electrode 14 is retracted to a portion indicated by a two-dot chain line in FIG. 28, a source-drain short circuit occurs.

  On the other hand, according to each embodiment mentioned above, it is possible to solve the problem in this reference example.

  Although the embodiments of the present invention have been described above, it is planned from the beginning to appropriately combine the characteristic portions of the respective embodiments described above. The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a top view showing a semiconductor device according to a first embodiment of the present invention. It is II-II sectional drawing in FIG. It is the III-III sectional view in FIG. It is IV-IV sectional drawing in FIG. It is a figure which shows the 1st step in the formation process of the structure shown by FIG. It is a figure which shows the 2nd step in the formation process of the structure shown by FIG. It is a figure which shows the 3rd step in the formation process of the structure shown by FIG. It is a figure which shows the 4th step in the formation process of the structure shown by FIG. It is a figure which shows the 5th step in the formation process of the structure shown by FIG. It is a figure which shows the 6th step in the formation process of the structure shown by FIG. It is a figure which shows the 1st step in the formation process of the structure shown by FIG. It is the figure which showed the photomask used in the formation process of the structure shown by FIG. It is a figure which shows the 2nd step in the formation process of the structure shown by FIG. It is a figure which shows the 3rd step in the formation process of the structure shown by FIG. It is a figure which shows the 4th step in the formation process of the structure shown by FIG. It is a figure which shows the 5th step in the formation process of the structure shown by FIG. It is XVII-XVII sectional drawing in FIG. It is a figure which shows the 6th step in the formation process of the structure shown by FIG. It is a figure which shows the 7th step in the formation process of the structure shown by FIG. It is a figure which shows the 8th step in the formation process of the structure shown by FIG. It is a figure which shows the 1st step in the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a figure which shows the 2nd step in the manufacturing process of the semiconductor device which concerns on Embodiment 2 of this invention. It is the top view which showed the semiconductor device which concerns on Embodiment 2 of this invention. It is the top view which showed the element isolation structure concerning a reference example. It is XXV-XXV sectional drawing in FIG. FIG. 25 is a diagram in which gate electrodes (design values) are laid out on the element isolation structure shown in FIG. 24. FIG. 27 is a diagram showing a gate electrode actually formed with respect to FIG. 26. It is the figure which expanded and showed the termination part periphery of the gate electrode shown by FIG. It is XXIX-XXIX sectional drawing in FIG. It is XXX-XXX sectional drawing in FIG. 4 is a graph showing the relationship between gate voltage Vg and drain current Id.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device, 10 Memory cell array part, 11 Control gate electrode, 11A, 14A, 1100A Conductive film, 11B, 14B, 1100B Silicide film, 12 Assist gate electrode, 12A, 20A, 31A Contact part, 12B, 20B, 31B Contact hole , 12C, 20C, 31C plug, 12D, 20D, 31D upper layer wiring, 13 floating gate electrode, 14 gate electrode, 20 common drain, 30 selection MOS part, 31 gate electrode (selection MOS part), 40 isolation region, 41 embedded defect Location, 42 narrow portion, 50 semiconductor substrate, 60 n-type buried region, 70 p well, 71, 73 n− impurity region, 72 n + impurity region, 74 active region, 80 gate insulating film, 90, 90A silicon nitride film, 100, 110, 120, 13 , 150 insulating film, 140 an interlayer insulating film, 160 a resist film, 400 a photomask, 410 light-shielding pattern, 420 light-transmitting pattern, 700 trenches, 1100 dummy gate electrode (dummy gate line), 1200,1200A, 1300 conductive, 4000 SiO ₂ membranes.

Claims (7)

A semiconductor substrate having a main surface;
A groove formed on the main surface;
An embedded pattern formed in the groove and having a void;
And at least a part of the pattern formed on the embedded pattern and having a termination on the void,
The said other pattern is a semiconductor device which has a thick part formed thicker than another part by being embedded in the said void. The embedded pattern has a narrow portion where the pattern width is narrower than the design pattern width,
The semiconductor device according to claim 1, wherein the void is formed in the narrow portion. The embedded pattern is an insulating film;
The semiconductor device according to claim 1, wherein the other pattern is a conductive film. The main surface of the semiconductor substrate has a first part in which the groove is formed, and a second part adjacent to the first part,
The semiconductor device according to claim 3, wherein the conductive film is a gate electrode provided from the first portion to the second portion. Forming a groove on the main surface of the semiconductor substrate;
Forming an embedded pattern having voids in the groove;
Depositing an upper layer film on the embedded pattern from within the void;
And patterning the upper layer film to form another pattern having a terminal portion on the void. The step of forming the groove includes
Forming a mask film having an opening corresponding to the groove on the main surface of the semiconductor substrate;
Forming the groove by etching using the mask film as a mask,
The step of forming the embedded pattern includes:
Depositing a buried film on the mask film from within the groove;
Burying the buried film in the groove by reducing the thickness of the buried film;
The method for manufacturing a semiconductor device according to claim 5, further comprising a step of removing the mask film. The step of forming the embedded pattern includes:
Forming a dummy pattern in a part of the groove,
Depositing a buried film in the groove so as to form a void between the dummy pattern and an edge of the buried pattern;
The method of manufacturing a semiconductor device according to claim 5, further comprising a step of burying the buried film in the groove portion by reducing a thickness of the buried film.

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