JP2006316308A - Method of forming group iii nitride semiconductor layer, method of manufacturing group iii nitride semiconductor substrate, and group iii nitride semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a group III nitride semiconductor layer forming method for forming a group III nitride semiconductor layer having excellent crystallinity, a group III nitride semiconductor substrate manufacturing method, and a group III nitride semiconductor substrate. <P>SOLUTION: A mask 12 having a covering part 122 having a square shape in a plane view is formed on a sapphire substrate 10. The three-dimensional core 140 of a GaN semiconductor layer is formed on the corner part 122A of the covering part 122 of the mask 12. The three-dimensional core 140 is further grown to form a structure 141 having a facet face 141A inclined with respect to the substrate surface of the sapphire substrate 10. In addition, the structure 141 is grown, and the structures 141 are integrated with each other to form the GaN semiconductor layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for forming a group III nitride semiconductor layer.

  In recent years, it has been proposed to use a gallium nitride (GaN) crystal as a substrate for producing a nitride-based optical device or electronic device, and many research institutions have attempted to produce a bulk crystal to obtain this substrate. ing. However, since the dissociation pressure of nitrogen in the GaN crystal is high, it is difficult to obtain a large bulk crystal from a solution such as GaAs, and it is very difficult to manufacture a GaN bulk crystal that can be used as a GaN semiconductor substrate.

For this reason, a method as described in Patent Document 1 has been proposed as a method for manufacturing a GaN semiconductor substrate.
In this manufacturing method, a mask having an island-shaped cover is formed on a sapphire (Al ₂ O ₃ ) substrate, and a GaN semiconductor layer is grown from an opening around the cover. At this time, the GaN semiconductor layer grown from the opening has a substantially T-shaped cross section as described in claim 1 of Patent Document 1.
Then, the GaN semiconductor layers are united at the center of the upper surface of the mask covering portion. By combining the GaN semiconductor layers at the center of the upper surface of the mask covering portion, the area of the merging point between the GaN semiconductor layers where dislocation is likely to occur can be minimized.
Thereafter, the GaN semiconductor layer and the sapphire substrate are separated to obtain a GaN semiconductor substrate.
JP 2003-55097 A

However, the prior art described in the above literature has room for improvement in the following points.
In the GaN semiconductor layer growth method described in Patent Document 1, threading dislocations inherited from the base substrate grow upward in the stacking direction when the GaN semiconductor layer is grown from the growth region of the base substrate. Therefore, there are problems that many threading dislocations remain in the GaN semiconductor layer and the crystallinity of the GaN semiconductor layer is poor.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for forming a group III nitride semiconductor layer capable of forming a group III nitride semiconductor layer having good crystallinity. It is in.

According to the present invention, a step of forming a mask having a polygonal covering portion on a base substrate, and at least growing a nucleus of a group III nitride semiconductor layer at a corner portion of the covering portion of the mask Growing a structure having a facet surface inclined with respect to the substrate surface of the base substrate from the nucleus, and combining the structures to obtain a group III nitride semiconductor layer;
A method for forming a group III nitride semiconductor layer is provided.

Here, in the step of growing the nucleus of the group III nitride semiconductor layer at the corner portion of the covering portion, the group III nitride semiconductor on the covering portion gathers at the corner portion to form the nucleus. Therefore, the corner of the covering portion needs to be smaller than 180 °. This is because if the angle formed by the corner becomes 180 ° or more, it becomes impossible to form a nucleus in the corner.
The angle of the corner of the covering is preferably 120 ° or less. By setting the angle of the corner portion of the covering portion to 120 ° or less, the nucleus of the group III nitride semiconductor layer can be stably formed.
Further, the corners only need to form the nucleus of the group III nitride semiconductor layer, and the corners may be somewhat rounded.
Furthermore, the shape of the mask covering portion is arbitrary as long as the planar shape is a polygonal shape, but is preferably a planar rectangular shape or a planar hexagonal shape.

According to the present invention, the nucleus of the group III nitride semiconductor layer is grown at the corner of the covering portion, and the structure having the facet plane inclined from the nucleus with respect to the base substrate is grown. The threading dislocation inherited from the base substrate is bent at the facet surface inclined with respect to the base substrate of the structure.
Each structure grown from the core of the corner portion of the covering portion grows while developing toward the central portion of the covering portion of the mask. In the method according to the present invention, since the structure having the facet surface grows from the corner portion of the covering portion, the periphery of each structure is developed surrounded by the facet surface, and the threading dislocation inherited from the base substrate is It becomes easier to bend.
Since each structure is gathered and united on the upper surface of the mask covering portion, the threading dislocations also gather on the upper surface of the mask covering portion, and the group III nitride semiconductor layer having a T-shaped cross section as in the prior art. Compared to the case of combining them, threading dislocations can be more concentrated in a specific part. Therefore, the reaction between dislocations having different Burgers vectors can be promoted. Thereby, a threading dislocation can be reduced more effectively by forming a dislocation loop.
In addition, the structures are not only gathered and united on the covering portion of the mask, but also the similar uniting of the structures occurs at the opening of the mask, so that the effect is further increased.
Therefore, in the method according to the present invention, the density of dislocations generated in the group III nitride semiconductor layer can be reduced, and a group III nitride semiconductor layer having good crystallinity can be obtained.

  According to the present invention, a Group III nitride semiconductor layer forming method, a Group III nitride semiconductor substrate manufacturing method, and a Group III nitride semiconductor substrate capable of forming a Group III nitride semiconductor layer having good crystallinity are provided. Is done.

In the present invention, a HVPE (hydride vapor phase epitaxy) method may be used in the step of growing the nucleus of the group III nitride semiconductor layer and the step of obtaining the group III nitride semiconductor layer.
By using the HVPE method, the nucleus of the group III nitride semiconductor layer is reliably grown at the corner of the mask covering portion, and the structure has a facet surface that is inclined from the nucleus to the substrate surface of the base substrate Can grow.

Further, in the present invention, in the step of growing the nucleus of the group III nitride semiconductor layer and the step of obtaining the group III nitride semiconductor layer, the supply amount of the nitrogen source gas constituting the group III nitride semiconductor layer is The V / III ratio, which is a ratio to the supply amount of the group III source gas constituting the group III nitride semiconductor layer, is preferably 30 or more.
By using the HVPE method and setting the V / III ratio to 30 or more, the nucleus of the group III nitride semiconductor layer is more reliably grown at the corner of the mask covering portion, and from the nucleus to the substrate surface of the base substrate It is possible to grow structures having faceted surfaces that are inclined with respect to.

Further, in the present invention, in the step of forming the mask, a first covering portion arranged in parallel at a predetermined interval in a stripe shape and a second covering portion arranged between the first covering portions. And the second covering part may form a mask whose planar shape is the polygonal covering part.
Furthermore, the first covering portion may extend in the <11-20> direction of the group III nitride semiconductor layer to be formed.
In the present invention, since the first covering portions extending in the <11-20> direction of the group III nitride semiconductor layer are arranged in parallel at predetermined intervals in a stripe shape, A structure having a facet surface is formed between the portions.
Accordingly, a structure having a facet surface grows from the corner of the polygon-shaped second covering portion, and the structures grown from this corner merge together to newly form the first covering portion. A structure having a facet surface will be formed.
Thereby, a group III nitride semiconductor layer with higher crystallinity can be obtained.

In the present invention, in the step of forming the mask, the mask having the covering portion having a polygonal shape along at least one side along the <11-20> direction of the group III nitride semiconductor layer to be formed. It may be formed.
Here, the <11-20> direction of the group III nitride semiconductor layer does not have to be a completely equivalent direction to the <11-20> direction of the group III nitride semiconductor layer, and the group III nitride semiconductor layer The deviation of the <11-20> direction from the completely equivalent direction is 10 ° or less.
According to the present invention as described above, since one side of the polygonal covering portion is along the <11-20> direction of the group III nitride semiconductor layer, the facet plane is formed from the nucleus of the group III nitride semiconductor layer. The structure which has can be formed reliably.
Furthermore, in the present invention, in the step of forming the mask, the planar shape has a covering portion having a regular hexagonal shape, and each side of the covering portion is along the <11-20> direction of the group III nitride semiconductor layer. A mask may be formed.
According to the present invention, since each side of the planar regular hexagonal covering portion is along the <11-20> direction of the group III nitride semiconductor layer, each of the two sides constituting the corner portion of the covering portion. The cross section of the structure perpendicular to the shape is triangular. Therefore, a group III nitride semiconductor layer with better crystallinity can be formed.

In the present invention, the group III nitride semiconductor layer is grown on the base substrate by any of the methods described above to obtain a group III nitride semiconductor layer, and the group III nitride semiconductor layer and base substrate A group III nitride semiconductor substrate including the group III nitride semiconductor layer is obtained, and a method for manufacturing a group III nitride semiconductor substrate can be provided.
Furthermore, the present invention can also provide a group III nitride semiconductor substrate manufactured by the method for manufacturing a group III nitride semiconductor substrate.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

Embodiments of the present invention will be described with reference to the schematic diagrams of FIGS.
The method for manufacturing a GaN substrate according to the present embodiment includes a step of forming a mask 12 having a cover 122 having a polygonal planar shape on a sapphire (Al ₂ O ₃ ) substrate 10 as a base substrate, and at least the mask 12. A step of growing the three-dimensional nucleus 140 of the GaN semiconductor layer 14 on the corner 122A of the covering portion 122, and a structure 141 having a facet surface 141A inclined from the three-dimensional nucleus 140 with respect to the substrate surface of the sapphire substrate 10. And growing the structures 141 together to obtain the GaN semiconductor layer 14.

Below, the manufacturing method of the GaN substrate of this embodiment is demonstrated in detail.
First, a silicon oxide (SiO ₂ ) film 12 having a thickness of 0.5 μm is formed on a (1000) sapphire substrate 10 on which a GaN film 11 having a thickness of 2 μm is formed (FIG. 1A).
Next, the silicon oxide (SiO ₂ ) film 12 is etched using the lithography technique to form a mask 12. The width of the opening 121 of the mask 12 (the width between adjacent covering portions 122) is 3 μm, and the opening 121 is formed in a lattice shape (FIGS. 1B and 1C).
The mask 12 has a plurality of covering portions 122 whose planar shape is a square shape. The periphery of the covering part 122 is surrounded by the opening part 121.
The directions of the sides of the cover 122 are the <1-100> direction of the sapphire substrate 10 (<11-20> direction of the GaN semiconductor layer 14) and the <11-20> direction of the sapphire substrate 10 (of the GaN semiconductor layer 14). <1-100> direction).

Next, the sapphire substrate 10 on which the mask 12 is formed is set on the substrate holder 31 in the reaction tube 30 of the HVPE (Hydride Vapor Phase Epitaxy) apparatus 3 shown in FIG.
Then, nitrogen (N ₂ ) gas is supplied from the gas introduction pipes 33 and 34 to purge the inside of the reaction pipe 30. The gas supplied into the reaction tube 30 is discharged from the discharge port 38. After sufficiently purging the inside of the reaction tube 30, the reaction tube 30 is heated by the heater 35 by switching to hydrogen (H ₂ ) gas. When the temperature of the growth region 36 reaches around 500 ° C., the temperature is increased by adding ammonia (NH ₃ ) gas from the gas introduction pipe 34. Further, the temperature rise is continued until the temperature of the Ga source 37 region reaches 850 ° C. and the temperature of the growth region 36 reaches 1040 ° C.
After the temperature of the Ga source 37 region and the temperature of the growth region 36 is stabilized, HCl gas is added and supplied from the gas introduction pipe 33 and reacted with gallium (Ga) in the source boat 39 to generate gallium chloride (GaCl). And transported to the growth region 36. In the growth region 36, NH ₃ gas and GaCl react. At this time, the surface of the covering portion 122 of the mask 12 is chemically low in activity, and it is difficult to adsorb these source gases or GaN molecular gas generated by the reaction. For this reason, these gases that have reached the surface of the covering portion 122 of the mask 12 are gathered at a site preferable for nucleation by diffusing the surface or by re-evaporation. A preferable portion for the nucleation is a corner portion 122A (four corners) in the covering portion 122 of the mask 12.

At this time, the V / III ratio, which is the ratio between the supply amount of NH ₃ gas and the supply amount of HCl gas, is preferably 30 or more. In this embodiment, the supply amount of HCl gas is 30 cc / min, and the supply amount of NH ₃ gas is 2000 cc / min.
When the GaN semiconductor at the corner 122A of the covering portion 122 is grown for about 2 minutes, the three-dimensional nucleus 140 of the GaN semiconductor layer 14 is formed at the corner 122A of the mask 12 (FIGS. 2D and 2E). .
After the growth of the three-dimensional nucleus 140 of the GaN semiconductor layer 14, the growth spreads from the nucleus to the opening 121 of the mask 12 and the covering portion 122 of the mask 12, and the facet surface is inclined with respect to the substrate surface of the sapphire substrate 10. A structure 141 having 141A is formed (FIGS. 2F and 2G).

Further, when the growth of the GaN semiconductor layer 14 is continued, the structures 141 grown from the four corners 122A of the covering portion 122 of the mask 12 are merged at substantially the center of the upper surface of the covering portion 122 of the mask 12. Further, the structures 141 are combined at substantially the center of the portion of the opening 121 surrounded by the four covering portions 122.
If the growth is continued for about 30 minutes after the structure 141 is formed, the GaN semiconductor layer 14 fills the opening 121 and the covering 122 of the mask 12.
Thereafter, the HCl gas supply rate is further increased to 200 cc / min to continue the growth.
If the growth is continued for 4 hours, the GaN semiconductor layer 14 embeds the mask 12, and a surface with less unevenness can be formed (FIGS. 3 (H) and (I)). The film thickness of the GaN semiconductor layer 14 formed by this growth was about 350 μm.
When the etch pit density by the mixed solution of phosphoric acid and sulfuric acid on the surface of the obtained GaN semiconductor layer 14 was measured, it was 7 × 10 ⁶ per cm ² .
Further, by separating the sapphire substrate 10 and the GaN semiconductor layer 14, a GaN substrate (self-supporting substrate) could be obtained.

Such effects of the present embodiment will be described below.
This will be described with reference to the schematic diagrams of FIGS.
FIG. 5 is a cross-sectional view showing a dislocation state in a conventional GaN semiconductor layer as described in Patent Document 1. In FIG.
FIG. 6 is a cross-sectional view showing a dislocation state in the GaN semiconductor layer 14 of the present embodiment.

As shown in FIG. 5, in the conventional method of forming a GaN semiconductor layer as described in Patent Document 1, the GaN semiconductor layers 102 are combined on the upper surface of the covering portion 101 of the mask 100 to form a continuous GaN semiconductor layer 102. Get. In this method, the threading dislocation Y2 generated from the interface between the sapphire substrate 10 and the GaN semiconductor layer 102 remains upward in the stacking direction.
On the other hand, in the present embodiment, the structure 141 having the facet surface 141A inclined with respect to the substrate surface of the sapphire substrate 10 is grown from the three-dimensional nucleus 140 of the corner portion 122A of the covering portion 122 of the mask 12. . As shown in FIG. 6, in this structure 141, threading dislocations Y <b> 2 generated from the interface between the sapphire substrate 10 and the GaN semiconductor layer 14 are bent by the facet surface 141 </ b> A inclined with respect to the substrate surface of the sapphire substrate 10. In this embodiment, since the structure 141 grows from the corner portion 122A of the covering portion 122, the periphery of each structure 141 is surrounded by the facet surface 141A, and the threading dislocation inherited from the sapphire substrate 10 is obtained. Y2 becomes easier to bend.
Since each structure 141 gathers and merges on the upper surface of the covering portion 122 of the mask 12, the threading dislocation Y2 also collects on the upper surface of the covering portion 122 of the mask 12, and as in the conventional case, the GaN having a T-shaped cross section. Compared with the case where the semiconductor layers 102 are combined, the threading dislocations Y2 can be more concentrated on a specific portion.
Therefore, the reaction between dislocations having different Burgers vectors can be promoted. Thereby, a threading dislocation Y2 can be reduced more effectively by forming a dislocation loop.
In addition to this, not only the upper surface of the covering portion 122 of the mask 12 is united but also the similar combination of the structures 141 occurs in the opening 121 of the mask 12, so that the effect is further increased.
As described above, dislocations generated in the GaN semiconductor layer 14 can be greatly reduced, and the GaN semiconductor layer 14 with good crystallinity can be obtained.
Compared with the case where a structure having a facet surface is grown from an opening instead of from a corner of the mask using a mask in which a covering is arranged in a stripe shape, the corner of the covering is as in this embodiment. The threading dislocation inherited from the base substrate is more easily bent when the structure having the facet surface is formed from the portion.

In the present embodiment, since the HVPE method is used, the three-dimensional nucleus 140 of the GaN semiconductor layer 14 can be reliably grown on the corner portion 122A of the covering portion 122 of the mask 12, and further, the three-dimensional nucleus 140 can be grown. Thus, the structure 141 can be grown.
Furthermore, when the GaN semiconductor layer 14 is grown, the V / III ratio, which is the ratio of the supply amount of NH ₃ gas and the supply amount of HCl gas, is set to 30 or more. Then, the three-dimensional nucleus 140 of the GaN semiconductor layer 14 can be grown, and the structure 141 can be further reliably grown from the three-dimensional nucleus 140.

As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.
For example, in the embodiment, the planar shape of the covering portion 122 of the mask 12 is a square shape, and the direction of the side of the covering portion 122 is the <1-100> direction of the sapphire substrate 10 (<11-20> of the GaN semiconductor layer 14). Direction) and <11-20> direction of the sapphire substrate 10 (<1-100> direction of the GaN semiconductor layer 14), but the direction of the sides of the covering portion is not limited to this.

Furthermore, the planar shape of the covering portion 122 is not limited to a square shape, and is arbitrary as long as it is a polygonal shape.
For example, as in the mask 21 shown in FIG. 7A, the shape of the covering portion 212 may be a planar triangle shape. The mask 21 has a plurality of covering portions 212, and the covering portions 212 are scattered in an island shape. The periphery of the covering portion 212 is surrounded by the opening 211.
One side of the covering portion 212 is along the <1-100> direction of the sapphire substrate 10 (the <11-20> direction of the GaN semiconductor layer 14).

Further, like the mask 41 shown in FIG. 7B, the shape of the covering portion 412 may be a plane regular hexagonal shape. The mask 41 has a plurality of covering portions 412, and the covering portions 412 are scattered in an island shape. The periphery of the covering portion 412 is surrounded by the opening 411.
Each side of the covering portion 412 is along the <1-100> direction of the sapphire substrate 10 (the <11-20> direction of the GaN semiconductor layer 14).
Therefore, the cross section orthogonal to each of the two sides constituting the corner portion of the covering portion 412 of the structure growing from the corner portion of the covering portion 412 has a triangular shape. Therefore, a GaN semiconductor layer with better crystallinity can be formed

Furthermore, you may form the mask 51 of a shape as shown in FIG.
The mask 51 includes a plurality of elongated first covering portions 513 and a plurality of second covering portions 512 disposed between the first covering portions 513.
The first covering portion 513 extends in the <1-100> direction of the sapphire substrate 10 (the <11-20> direction of the GaN semiconductor layer).
The 2nd coating | coated part 512 is a shape similar to the coating | coated part 122 of the said embodiment, and is a planar square shape. The periphery of the second covering portion 512 is surrounded by the opening 511, and the plurality of second covering portions 512 are spaced apart. The directions of the sides of the second covering portion 512 are the <1-100> direction of the sapphire substrate 10 (<11-20> direction of the GaN semiconductor layer 14) and the <11-20> direction of the sapphire substrate 10 (GaN semiconductor). <1-100> direction of layer 14).
When a GaN semiconductor layer is grown using such a mask 51, first, a three-dimensional nucleus of the GaN semiconductor layer is grown at the corner of the second covering portion 512. Then, a structure having a facet surface is formed from the three-dimensional nucleus. As the structure grows, the structures merge at approximately the center of the upper surface of the second covering portion 512.
When this combined structure is grown, a structure having a large facet surface between the first covering portions 513 is obtained. Further, when a large structure between the first covering portions 513 is grown, adjacent structures sandwiching the first covering portion 513 are combined to form a GaN semiconductor layer.
Therefore, when forming a GaN semiconductor layer using such a mask 51, after a structure having a facet surface is grown from a three-dimensional nucleus, a facet surface is further formed between the first covering portions 513. Since the structure having the structure is grown, a GaN semiconductor layer with higher crystallinity can be formed.

Moreover, in the said embodiment, although the film thickness of the GaN semiconductor layer 14 was about 350 micrometers, not only this but a dislocation density can be reduced by growing a GaN semiconductor layer to a thick film thickness, and 1 cm < ² >. 1 × 10 ⁶ crystals or less can be formed.

Moreover, in the said embodiment, although the sapphire substrate 10 was isolate | separated immediately after growing the GaN semiconductor layer 14, it is not restricted to this, Light emitting elements, such as a light emitting diode, Furthermore, a transistor etc. on the GaN semiconductor layer 14 After creating the electronic device, the sapphire substrate 10 may be removed to obtain a light emitting element and an electronic device. When manufacturing these devices, the sapphire substrate may be removed to form electrodes on the back surface.
Furthermore, although the single-layered GaN semiconductor layer 14 is obtained in the embodiment, the present invention is not limited to this. The group III nitride semiconductor layer produced in the present invention may have a multilayer structure. For example, a GaN semiconductor layer is formed as a first layer on a base substrate, and a second layer (for example, an n-AlGaN layer) made of a group III nitride semiconductor and a third layer are further formed on the first layer. A group III nitride semiconductor layer obtained by the present invention by forming (for example, an InGaN layer) or the like may be used as a semiconductor laser.
When manufacturing such a semiconductor laser, a first-layer GaN semiconductor layer is formed on a base substrate, and a second-layer, third-layer, etc. group III nitride semiconductor is formed on the first layer. After the layer is grown, the base substrate is finally separated.

Furthermore, in the above embodiment, was used to produce the GaN semiconductor layer 14 is not limited to the GaN semiconductor layer _{14, In X Ga 1-X} N layer (0 ≦ X ≦ 1) or _{Al X Ga 1-X} N layer (0 ≦ X ≦ 1) may be formed.
In the embodiment, the GaN film 11 is formed on the sapphire substrate 10 and the mask 12 is formed on the GaN film 11. However, the mask 12 may be directly formed on the sapphire substrate 10.

Furthermore, in the embodiment, when the GaN semiconductor layer 14 is formed by the HVPE method, the V / III ratio is set to 30 or more. However, the present invention is not limited to this, and the V / III ratio may be less than 30.
Moreover, in the said embodiment, although the GaN semiconductor layer 14 was formed by HVPE method, the method for forming a GaN semiconductor layer is not restricted to HVPE method. The GaN semiconductor layer can be formed by any method as long as the growth conditions of the GaN semiconductor layer are appropriately set and the nucleus of the group III nitride semiconductor layer can be grown at the corner of the mask covering portion.
Furthermore, in the above-described embodiment, the three-dimensional nucleus 140 is grown only on the corner 122A of the covering portion 122 of the mask 12. However, the present invention is not limited to this. Nuclei may be grown.

Example 1
A GaN semiconductor substrate was manufactured under the growth conditions shown in the above embodiment.

(Comparative Example 1)
A mask covering portion was formed in a stripe shape, and a GaN semiconductor substrate was formed without growing a nucleus of the GaN semiconductor layer at a corner portion of the covering portion. The mask covering portion extends in the <1-100> direction of the sapphire substrate (<11-20> direction of the GaN semiconductor layer). The GaN semiconductor layer is obtained by growing a structure having facet surfaces that are inclined with respect to the substrate surface of the sapphire substrate on both sides of the long side of the covering portion. The so-called FIELO method (facet-initiated epitaxial lateral overgrowth) It has grown by.

(Comparative Example 2)
A GaN semiconductor layer was grown by MOCVD (metal organic chemical vapor deposition) using the mask used in the above embodiment. In Comparative Example 2, the growth of the GaN semiconductor layer was stopped halfway, and the growth state of the GaN semiconductor layer was observed.
The GaN semiconductor layer grew from the opening, and no nuclei of the GaN semiconductor layer were formed at the corners of the covering.

(Results of Example 1 and Comparative Examples 1 and 2)
FIG. 9 shows the result of the relationship between the film thickness of the GaN semiconductor substrate and the dislocation density.
9 indicates the GaN semiconductor substrate manufactured in Example 1, and the black triangle in FIG. 9 indicates the GaN semiconductor substrate manufactured in Comparative Example 1.
The dislocation density is lower in the GaN semiconductor substrate manufactured in Example 1 than in the GaN semiconductor substrate manufactured in Comparative Example 1.
From the above, in Example 1, it was confirmed that a highly crystalline GaN semiconductor substrate could be obtained.

FIG. 10 shows the result of the relationship between the film thickness of the GaN semiconductor substrate and the half width of the X-ray rocking curve obtained by the (0002) reflection of the GaN semiconductor substrate.
10 indicates the GaN semiconductor substrate manufactured in Example 1, and the black triangle in FIG. 10 indicates the GaN semiconductor substrate manufactured in Comparative Example 1.
The FWHM of the GaN semiconductor substrate manufactured in Example 1 is smaller than that of the GaN semiconductor substrate manufactured in Comparative Example 1.
From the above, in Example 1, it was confirmed that a highly crystalline GaN semiconductor substrate could be obtained.
In addition, the GaN semiconductor layer manufactured in Comparative Example 2 grew from the opening, and the core of the GaN semiconductor layer was not formed at the corner of the covering. It was confirmed that nuclei could not be formed at the corners of the covering portion only by using the mask having the same.

1A and 1B are cross-sectional views schematically showing a manufacturing process of a GaN substrate according to an embodiment of the present invention, and FIG. 1C is a plan view of FIG. is there. FIG. 2D is a cross-sectional view schematically showing a manufacturing process of the GaN substrate, and FIG. 2E is a plan view of FIG. FIG. 2F is a cross-sectional view schematically showing the manufacturing process of the GaN substrate, and FIG. 2G is a plan view of FIG. FIG. 3 (H) is a cross-sectional view schematically showing the manufacturing process of the GaN substrate, and FIG. 3 (I) is a plan view of FIG. 3 (H). It is a figure which shows a HVPE apparatus typically. It is sectional drawing which shows the state of the dislocation in the conventional GaN semiconductor layer. It is sectional drawing which shows the state of the dislocation in the GaN semiconductor layer of this embodiment. FIG. 7A and FIG. 7B are plan views showing modifications of the mask. It is a top view which shows the other modification of a mask. It is a figure which shows the relationship between the film thickness of a GaN semiconductor substrate and dislocation density in an Example and a comparative example. It is a figure which shows the relationship between the film thickness of the GaN semiconductor substrate in an Example and a comparative example, and the half value width of a X-ray rocking curve.

Explanation of symbols

3 HVPE apparatus 10 sapphire substrate 11 GaN film 12 mask 14 GaN semiconductor layer 21 mask 30 reaction tube 31 substrate holder 33 gas introduction tube 34 gas introduction tube 35 heater 36 growth region 37 source 38 discharge port 39 source boat 41 mask 51 mask 100 mask DESCRIPTION OF SYMBOLS 101 Covering part 102 GaN semiconductor layer 121 Opening part 122 Covering part 122A Corner part 140 Three-dimensional nucleus 141A Facet surface 141 Structure 211 Opening part 212 Covering part 411 Opening part 412 Covering part 511 Opening part 512 Second covering part 513 First Coating Y2 threading dislocation

Claims (9)

Forming a mask having a polygonal covering portion on a base substrate;
Growing a nucleus of a group III nitride semiconductor layer at least at a corner of the covering portion of the mask; and
From the nucleus, growing a structure having a facet surface inclined with respect to the substrate surface of the base substrate, and combining the structures to obtain a group III nitride semiconductor layer;
A method for forming a group III nitride semiconductor layer, comprising: The method for forming a group III nitride semiconductor layer according to claim 1,
In the step of growing the nucleus of the group III nitride semiconductor layer and the step of obtaining the group III nitride semiconductor layer, a HVPE (hydride vapor phase epitaxy) method is used. Method. The method for forming a group III nitride semiconductor layer according to claim 2,
In the step of growing the nucleus of the group III nitride semiconductor layer and the step of obtaining the group III nitride semiconductor layer, the supply amount of the nitrogen source gas constituting the group III nitride semiconductor layer, and the group III nitride A method for forming a group III nitride semiconductor layer, wherein a V / III ratio, which is a ratio to a supply amount of a group III source gas constituting the semiconductor layer, is 30 or more. In the method for forming a group III nitride semiconductor layer according to any one of claims 1 to 3,
The step of forming the mask includes a first covering portion arranged in parallel with a predetermined interval in a stripe shape, and a second covering portion disposed between the first covering portions,
The method of forming a group III nitride semiconductor layer, wherein the second covering portion forms a mask whose planar shape is the polygonal covering portion. The method for forming a group III nitride semiconductor layer according to claim 4,
The method of forming a group III nitride semiconductor layer, wherein the first covering portion extends in a <11-20> direction of the group III nitride semiconductor layer to be formed. In the method for forming a group III nitride semiconductor layer according to any one of claims 1 to 5,
In the step of forming the mask, at least one side forms a mask having the polygonal covering portion along the <11-20> direction of the group III nitride semiconductor layer to be formed. A method for forming a group III nitride semiconductor layer. The method for forming a group III nitride semiconductor layer according to claim 6,
In the step of forming the mask, the planar shape has a regular hexagonal covering portion, and each side of the covering portion forms a mask along the <11-20> direction of the group III nitride semiconductor layer. A method for forming a group III nitride semiconductor layer. A method for manufacturing a group III nitride semiconductor substrate, comprising:
A step of growing the group III nitride semiconductor layer on the base substrate by the method according to claim 1 to obtain the group III nitride semiconductor layer;
Separating the group III nitride semiconductor layer and the base substrate,
A method for producing a group III nitride semiconductor substrate comprising obtaining a group III nitride semiconductor substrate including the group III nitride semiconductor layer. A group III nitride semiconductor substrate manufactured by the method for manufacturing a group III nitride semiconductor substrate according to claim 8.

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