JP2006295079A - Light emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emitting device which can efficiently radiate the heat generated in a semiconductor light emitting element. <P>SOLUTION: A light emitting device LE1 includes the semiconductor light emitting element 1 and a multi-layered chip varistor 11. The multi-layered chip varistor 11 includes a varistor element 21 and a plurality of external electrodes 27, 28 which are formed on the outer surface of the varistor element 21. The varistor element 21 has a vaistor layer with a ZnO as a main component and a plurality of internal electrodes 31, 41 located to sandwich the varistor layer. The external electrode 27 is connected with the internal electrode 31, and the external electrode 28 is connected with the internal electrode 41. The semiconductor light emitting element 1 is located on the multi-layered chip varistor 11, and is connected with the plurality of external electrodes 27, 28 so as to be connected with the multi-layered chip varistor 11 in parallel. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a light emitting device.

As this type of light emitting device, a device including a semiconductor light emitting element and a varistor connected in parallel to the semiconductor light emitting element is known (for example, see Patent Document 1). In the light emitting device described in Patent Document 1, the semiconductor light emitting element is protected from an ESD (Electrostatic Discharge) surge by a varistor connected in parallel.
Japanese Patent Laid-Open No. 2001-15815

  By the way, the semiconductor light emitting device emits heat during the light emitting operation. When the semiconductor light emitting element becomes high temperature, the light emitting operation is affected. For this reason, it is necessary to dissipate the generated heat efficiently. In particular, when the semiconductor light emitting element is sealed with an optically transparent resin, it is difficult to dissipate heat generated in the semiconductor light emitting element.

  An object of the present invention is to provide a light emitting device capable of efficiently dissipating heat generated in a semiconductor light emitting element.

  A light-emitting device according to the present invention includes a semiconductor light-emitting element and a multilayer chip varistor, and the multilayer chip varistor is disposed so as to sandwich the varistor layer mainly composed of ZnO and the varistor layer. A semiconductor light emitting element comprising: a multilayer body having a plurality of internal electrodes; and a plurality of external electrodes formed on the outer surface of the multilayer body and respectively connected to corresponding internal electrodes among the plurality of internal electrodes Is arranged on a multilayer chip varistor and is connected to a corresponding external electrode among a plurality of external electrodes so as to be connected in parallel to the multilayer chip varistor.

  In the light emitting device according to the present invention, since the multilayer chip varistor is connected in parallel to the semiconductor light emitting element, the semiconductor light emitting element can be protected from an ESD surge.

  In the present invention, since the multilayer chip varistor has an external electrode connected to the semiconductor light emitting element and an internal electrode connected to the external electrode, heat generated in the semiconductor light emitting element is mainly applied to the external electrode and the internal electrode. It will be transmitted and dissipated. The heat dissipation path of the heat generated in the semiconductor light emitting element is expanded, and the heat generated in the semiconductor light emitting element can be efficiently dissipated. By the way, the varistor layer is mainly composed of ZnO. ZnO has a thermal conductivity comparable to that of alumina or the like normally used as a heat dissipation substrate, and has a relatively good thermal conductivity. Therefore, it is possible to suppress the heat dissipation from the internal electrode from being inhibited by the varistor layer.

  Preferably, the semiconductor light emitting element is disposed so as to face a surface extending in a direction parallel to the stacking direction of the stacked body in the stacked chip varistor. In this case, the plurality of internal electrodes are juxtaposed along the direction in which the surface extends with respect to the surface of the multilayer chip varistor facing the surface on which the semiconductor light emitting element is disposed. Thereby, with respect to each internal electrode, a heat radiation path from the internal electrode to the outer surface of the multilayer chip varistor is shortened, and heat can be more efficiently dissipated from the internal electrode.

  Preferably, the plurality of external electrodes include a pair of terminal electrodes, and the pair of terminal electrodes are formed on a pair of outer surfaces facing each other and extending in a direction parallel to the stacking direction of the stacked body. And a second electrode portion formed on one outer surface adjacent to the pair of outer surfaces on which the first electrode portions are formed and extending in a direction parallel to the stacking direction of the laminate. Yes. In this case, the semiconductor light emitting element is mounted on the multilayer chip varistor by being connected to the second electrode portion. Therefore, mounting for electrically connecting the semiconductor light emitting element and the external electrode can be performed easily and simply.

Preferably, the varistor layer includes Pr, and the plurality of external electrodes are formed on the outer surface of the multilayer body by co-firing with the multilayer body and have an electrode layer including Pd. In this case, by simultaneous firing of the varistor element body and the electrode layer, an oxide of Pr and Pd, such as Pr ₂ Pd ₂ O ₅ or Pr ₄ PdO _7, is formed in the vicinity of the interface between the laminate and the external electrode. , Will exist. As a result, the adhesive strength between the laminate and the external electrode can be improved.

  The present inventors have conducted intensive research on a varistor capable of improving the adhesive strength between a varistor element body mainly composed of ZnO and an external electrode. As a result, depending on the material contained in the laminate (green body that becomes a laminate when fired) and the external electrode (conductive paste that becomes an external electrode when fired), the laminate and the external electrode It came to discover the new fact that adhesive strength changes.

  After the conductive paste is applied to the outer surface of the green body mainly composed of ZnO, these are fired to obtain a laminate and an external electrode. At this time, when the green body contains Pr (praseodymium) and the conductive paste contains Pd (palladium), the adhesive strength between the obtained varistor element body and the external electrode is improved.

  The effect of improving the adhesive strength between the laminate and the external electrode is considered to be caused by the following event during firing. When the green body and the conductive paste are fired, Pr contained in the green body moves near the surface of the green body, that is, near the interface between the green body and the conductive paste. And Pr which moved to the interface vicinity of a green body and an electrically conductive paste and Pd contained in an electrically conductive paste mutually diffuse. At this time, an oxide of Pr and Pd may be formed near the interface between the laminate and the external electrode. An anchor effect is produced by the oxide of Pr and Pd, and the adhesive strength between the laminate obtained by firing and the external electrode is improved.

  Preferably, the varistor layer includes Pr, and the plurality of external electrodes includes an electrode layer that is formed on the outer surface of the multilayer body and includes Pd, and the varistor layer is disposed near the interface between the multilayer body and the electrode layer. There is an oxide of Pr contained in the layer and Pd contained in the electrode layer. In this case, since an oxide of Pr contained in the laminate and Pd contained in the electrode layer exists in the vicinity of the interface between the laminate and the external electrode, the adhesive strength between the laminate and the external electrode is improved. be able to.

  Preferably, the electrode layer is formed on the outer surface of the multilayer body by simultaneous firing with the multilayer body. In this case, an oxide of Pr contained in the varistor element body and Pd contained in the electrode layer can surely exist in the vicinity of the interface between the varistor element body and the external electrode.

  Preferably, a plurality of external electrodes are formed on one outer surface of the outer surface of the laminate, and a pair of terminal electrodes electrically connected to corresponding internal electrodes among the plurality of internal electrodes, and a pair A pair of pad electrodes formed on the outer surface opposite to the outer surface on which the terminal electrode is formed and electrically connected to the corresponding inner electrode among the plurality of inner electrodes, and the plurality of inner electrodes However, a first electrode portion that overlaps between adjacent internal electrodes among the plurality of internal electrodes, an outer surface on which a pair of terminal electrodes are formed from the first electrode portion, and a pair of pad electrodes are formed. And a pair of terminal electrodes and a pair of pad electrodes that are electrically connected to corresponding internal electrodes through the second electrode portion. There. In this case, the semiconductor light emitting element is mounted on the multilayer chip varistor by being connected to the pad electrode. Therefore, mounting for electrically connecting the semiconductor light emitting element and the pad electrode can be performed easily and simply. The multilayer chip varistor is mounted on an external substrate, an external device, or the like with the outer surface on which the terminal electrode is formed facing the external substrate, the external device, or the like. Therefore, the mounting of the multilayer chip varistor can be performed easily and simply.

  Preferably, the outer surface on which the pair of terminal electrodes are formed and the outer surface on which the pair of pad electrodes are formed extend in a direction parallel to the stacking direction of the stacked body. In this case, the plurality of internal electrodes are juxtaposed along the direction in which the outer surface extends with respect to the outer surface on which the pair of terminal electrodes are formed and the outer surface on which the pair of pad electrodes are formed. Thereby, with respect to each internal electrode, a heat radiation path from the internal electrode to the outer surface of the multilayer chip varistor is shortened, and heat can be more efficiently dissipated from the internal electrode.

  Preferably, the semiconductor light emitting element is disposed on the multilayer chip varistor by being bump-connected to the pair of pad electrodes. In this case, the semiconductor light emitting element can be mounted on the multilayer chip varistor very easily and simply.

  Preferably, the semiconductor light emitting element has a first conductivity type semiconductor region and a second conductivity type semiconductor region, and is applied between the first conductivity type semiconductor region and the second conductivity type semiconductor region. Emits light according to the applied voltage.

  ADVANTAGE OF THE INVENTION According to this invention, the light-emitting device which can dissipate the heat generate | occur | produced in the semiconductor light-emitting element efficiently can be provided.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

(First embodiment)
With reference to FIGS. 1-4, the structure of light-emitting device LE1 which concerns on 1st Embodiment is demonstrated. FIG. 1 is a schematic top view showing the multilayer chip varistor according to the first embodiment. FIG. 2 is a schematic bottom view showing the multilayer chip varistor according to the first embodiment. FIG. 3 is a diagram for explaining a cross-sectional configuration along the line III-III in FIG. 1. FIG. 4 is a diagram for explaining a cross-sectional configuration along the line IV-IV in FIG. 1.

  As shown in FIGS. 1 to 4, the light emitting device LE <b> 1 includes a semiconductor light emitting element 1 and a multilayer chip varistor 11. The semiconductor light emitting device 1 is disposed on a multilayer chip varistor 11.

  First, the configuration of the multilayer chip varistor 11 will be described. The multilayer chip varistor 11 includes a varistor element body 21 having a substantially rectangular parallelepiped shape, a plurality (a pair in this embodiment) of external electrodes 25 and 26, and a plurality (a pair in this embodiment) of external electrodes. 27, 28. The pair of external electrodes 25 and 26 are formed on one main surface (outer surface) 22 of the varistor element body 21, respectively. The pair of external electrodes 27 and 28 are respectively formed on the other main surface (outer surface) 23 of the varistor element body 21. For example, the varistor element body 21 is set to have a length of about 1.0 mm, a width of about 0.5 mm, and a thickness of about 0.3 mm. The external electrode 25 functions as an input terminal electrode of the multilayer chip varistor 11, and the external electrode 26 functions as an output terminal electrode of the multilayer chip varistor 11. The external electrodes 27 and 28 function as pad electrodes that are electrically connected to the semiconductor light emitting element 1 described later.

  The varistor element body 21 is formed by laminating a plurality of varistor layers that exhibit voltage nonlinear characteristics (hereinafter referred to as “varistor characteristics”), and a plurality of first internal electrodes 31 and second internal electrodes 41, respectively. It is comprised as a laminated body. The first internal electrode 31 and the second internal electrode 41 are arranged one by one in the varistor element body 21 along the stacking direction of the varistor layers (hereinafter simply referred to as “stacking direction”). The first internal electrode 31 and the second internal electrode 41 are arranged so that at least one varistor layer is sandwiched between them. The pair of main surfaces 22 and 23 of the varistor element body 21 extend in a direction parallel to the stacking direction of the varistor layers and a direction parallel to the varistor layers. The first internal electrode 31 and the second internal electrode 41 are juxtaposed along the stacking direction of the varistor layers. In the actual multilayer chip varistor 11, the plurality of varistor layers are integrated so that the boundary between them cannot be visually recognized.

  The varistor layer contains ZnO (zinc oxide) as a main component and also includes rare earth metal elements, Co, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, K) as subcomponents. Rb, Cs) and simple earth metals such as alkaline earth metal elements (Mg, Ca, Sr, Ba) and element bodies containing these oxides. In the present embodiment, the varistor layer contains Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents. As a result, a region of the varistor layer that overlaps the first internal electrode 31 and the second internal electrode 41 contains ZnO as a main component and Pr.

  In the present embodiment, Pr is used as the rare earth metal. Pr is a material for expressing varistor characteristics. The reason for using Pr is that voltage non-linearity is excellent and characteristic variation during mass production is small. Although content of ZnO in a varistor layer is not specifically limited, When the whole material which comprises a varistor layer is 100 mass%, it is 99.8-69.0 mass% normally. The thickness of the varistor layer is, for example, about 5 to 60 μm.

  As shown also in FIG. 3, the first internal electrode 31 includes a first electrode portion 33 and second electrode portions 35a and 35b. The first electrode portion 33 overlaps with a first electrode portion 43 of a third internal electrode 41 described later when viewed from the stacking direction. The first electrode portion 33 has a substantially rectangular shape. The second electrode portion 35a is led out from the first electrode portion 33 so as to be exposed on the one main surface 22, and functions as a lead conductor. The second electrode portion 35 a is physically and electrically connected to the external electrode 25. The second electrode portion 35b is drawn out from the first electrode portion 33 so as to be exposed on the other main surface 23, and functions as a lead conductor. The second electrode portion 35 b is physically and electrically connected to the external electrode 27. The first electrode portion 33 is electrically connected to the external electrode 25 through the second electrode portion 35a, and is electrically connected to the external electrode 27 through the second electrode portion 35b. The second electrode portions 35 a and 35 b are formed integrally with the first electrode portion 33.

  The second internal electrode 41 includes a first electrode portion 43 and second electrode portions 45a and 45b as shown in FIG. The first electrode portion 43 overlaps the first electrode portion 33 of the first internal electrode 31 when viewed from the stacking direction. The first electrode portion 43 has a substantially rectangular shape. The second electrode portion 45a is led out from the first electrode portion 43 so as to be exposed on the one main surface 22, and functions as a lead conductor. The second electrode portion 45 a is physically and electrically connected to the external electrode 26. The second electrode portion 45b is drawn out from the first electrode portion 43 so as to be exposed on the other main surface 23, and functions as a lead conductor. The second electrode portion 45 b is physically and electrically connected to the external electrode 28. Each first electrode portion 43 is electrically connected to the external electrode 26 through the second electrode portion 45a, and is electrically connected to the external electrode 28 through the second electrode portion 45b. The second electrode portions 45 a and 45 b are formed integrally with the first electrode portion 43.

  The first and second internal electrodes 31 and 41 include a conductive material. Although it does not specifically limit as a electrically conductive material contained in the 1st and 2nd internal electrodes 31 and 41, It is preferable to consist of Pd or an Ag-Pd alloy. The thickness of the first and second internal electrodes 31 and 41 is, for example, about 0.5 to 5 μm.

  The external electrode 25 and the external electrode 26 are arranged on one main surface 22 with a predetermined interval in a direction perpendicular to the stacking direction of the varistor layers and parallel to the other main surface 22. The external electrodes 25 and 26 have a rectangular shape (in this embodiment, a square shape). For example, the length of each side of the external electrodes 25 and 26 is set to about 300 μm, and the thickness is set to about 5 μm.

  The external electrode 27 and the external electrode 28 are arranged on the other main surface 23 with a predetermined interval in a direction perpendicular to the stacking direction of the varistor layers and parallel to the other main surface 23. The external electrodes 27 and 28 have a rectangular shape (in this embodiment, a square shape). For example, the length of each side of the external electrodes 27 and 28 is set to about 300 μm, and the thickness is set to about 5 μm.

  The external electrodes 25 to 28 have first electrode layers 25a to 28a and second electrode layers 25b to 28b, respectively. The first electrode layers 25a to 28a are formed on the outer surface of the varistor element body 21, and contain Pd. The first electrode layers 25a to 28a are formed by firing a conductive paste as will be described later. As the conductive paste, a mixture of a metal powder containing Pd particles as a main component with an organic binder and an organic solvent is used. The metal powder may be mainly composed of Ag—Pd alloy particles.

  The second electrode layers 25b to 28b are formed on the first electrode layers 25a to 28a by a printing method or a plating method. The second electrode layers 25b to 28b are made of Au or Pt. In the case of using the printing method, a conductive paste in which an organic binder and an organic solvent are mixed in a metal powder mainly composed of Au particles or Pt particles is prepared, and the conductive paste is applied to the first electrode layers 25a to 28a. The second electrode layers 25b to 28b are formed by printing and baking or baking. When the plating method is used, the second electrode layers 25b to 28b are formed by vapor-depositing Au or Pt by a vacuum plating method (vacuum evaporation method, sputtering method, ion plating method, or the like). The second electrode layers 25b to 28b may be configured as a Pt / Au laminate.

  As described above, the first electrode portion 33 of the first internal electrode 31 and the first electrode portion 43 of the third internal electrode 41 are the first electrode portions 33 of the adjacent first internal electrodes 31. And overlap each other. Therefore, a region overlapping the first electrode portion 33 and the first electrode portion 43 in the varistor layer functions as a region that develops varistor characteristics. In the multilayer chip varistor 11 having the above-described configuration, the first electrode portion 33, the first electrode portion 43, and a region overlapping the first electrode portion 33 and the first electrode portion 43 in the varistor layer. One varistor portion is formed.

  Subsequently, a manufacturing process of the multilayer chip varistor 11 having the above-described configuration will be described with reference to FIGS. FIG. 5 is a flowchart for explaining the manufacturing process of the multilayer chip varistor according to the first embodiment. FIG. 6 is a view for explaining the manufacturing process of the multilayer chip varistor according to the first embodiment.

  First, after weighing ZnO, which is a main component constituting the varistor layer, and trace additives such as Pr, Co, Cr, Ca, Si, K, and Al metals or oxides so as to have a predetermined ratio. The varistor material is adjusted by mixing the components (step S101). Then, an organic binder, an organic solvent, an organic plasticizer, etc. are added to this varistor material, and it mixes and grinds for about 20 hours using a ball mill etc., and obtains a slurry.

  The slurry is applied onto a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a thickness of about 30 μm. The film thus obtained is peeled from the film to obtain a green sheet (step S103).

  Next, a plurality of electrode portions corresponding to the first and second internal electrodes 31, 41 are formed on the green sheet (a number corresponding to the number of divided chips described later) (step S105). The electrode portions corresponding to the first and second internal electrodes 31 and 41 are printed by a printing method such as screen printing with a conductive paste in which a metal powder mainly composed of Pd particles, an organic binder, and an organic solvent is mixed. It is formed by drying.

  Next, a sheet laminate is formed by stacking each green sheet on which electrode portions are formed and a green sheet on which electrode portions are not formed in a predetermined order (step S107). The thus obtained sheet laminate is cut into chips, and a plurality of divided green bodies GL1 (see FIG. 6) are obtained (step S109). In the obtained green body GL1, a green sheet GS1 in which an electrode portion EL1 corresponding to the first internal electrode 31 is formed, a green sheet GS2 in which an electrode portion EL2 corresponding to the second internal electrode 41 is formed, A green sheet GS3 on which the electrode portions EL1 and EL2 are not formed is sequentially laminated. A plurality of green sheets GS3 positioned between the green sheets GS1 and GS2 may be stacked or may not be stacked.

  Next, the conductive paste for the first electrode layers 25a to 28a of the external electrodes 25 to 28 and the conductive paste for the second electrode layers 25b to 28b of the external electrodes 25 to 28 are formed on the outer surface of the green body GL1. (Step S111). Here, a conductive paste is printed on one main surface of the green body GL1 so as to be in contact with the corresponding electrode portions EL1 and EL2, and then dried, thereby drying the first electrode layer 25a, An electrode portion corresponding to 26a is formed. Then, the conductive paste is printed on the electrode portions corresponding to the first electrode layers 25a and 26a by a screen printing method, and then dried, so that the electrode portions corresponding to the second electrode layers 25b and 26b are formed. Form. In addition, a conductive paste is printed on the other main surface of the green body GL1 so as to be in contact with the corresponding electrode portions EL1 and EL2 by a screen printing method, and then dried to thereby form the first electrode layers 27a and 28a. The electrode part corresponding to is formed. Then, after the conductive paste is printed on the electrode portions corresponding to the first electrode layers 27a and 28a by the screen printing method, the electrode portions corresponding to the second electrode layers 27b and 28b are dried by drying. Form.

  As described above, the conductive paste for the first electrode layers 25a to 28a is a mixture of an organic binder and an organic solvent in a metal powder mainly composed of Ag-Pd alloy particles or Pd particles. Can do. As described above, the conductive paste for the second electrode layers 25b to 28b may be a mixture of a metal powder containing Pt particles as a main component and an organic binder and an organic solvent. These conductive pastes do not contain glass frit.

  Next, the green body GL1 provided with the conductive paste was subjected to a heat treatment at 180 to 400 ° C. for about 0.5 to 24 hours to remove the binder, and then further to 1000 to 1400 ° C. and 0. Baking is performed for about 5 to 8 hours (step S113), and the varistor element body 21, the first electrode layers 25a to 28a, and the second electrode layers 25b to 28b are obtained. By this firing, the green sheets GS1 to GS3 in the green body GL1 become varistor layers. The electrode portion EL <b> 1 becomes the first internal electrode 31. The electrode portion EL <b> 2 becomes the second internal electrode 41.

  Through the above process, the multilayer chip varistor 11 is obtained. Note that alkali metal (for example, Li, Na, etc.) may be diffused from the surface of the varistor element body 21 after firing.

  Next, the configuration of the semiconductor light emitting element 1 will be described with reference to FIGS. 3 and 4.

  The semiconductor light-emitting element 1 is a light-emitting diode (LED) of a GaN (gallium nitride) semiconductor, and includes a substrate 2 and a layer structure LS formed on the substrate 2. GaN-based semiconductor LEDs are well known and will be described briefly. The substrate 2 is an optically transparent and electrically insulating substrate made of sapphire. The layer structure LS includes an n-type (first conductivity type) semiconductor region 3, a light emitting layer 4, and a p-type (second conductivity type) semiconductor region 5 which are stacked. The semiconductor light emitting element 1 emits light according to a voltage applied between the n-type semiconductor region 3 and the p-type semiconductor region 5.

  The n-type semiconductor region 3 includes an n-type nitride semiconductor. In this embodiment, the n-type semiconductor region 3 is formed by epitaxially growing GaN on the substrate 2 and has an n-type conductivity by adding an n-type dopant such as Si. Further, the n-type semiconductor region 3 may have a composition such that the refractive index is smaller than that of the light emitting layer 4 and the band gap is increased. In this case, the n-type semiconductor region 3 serves as a lower cladding for the light emitting layer 4.

  The light emitting layer 4 is formed on the n-type semiconductor region 3, and carriers (electrons and holes) supplied from the n-type semiconductor region 3 and the p-type semiconductor region 5 are recombined to emit light in the light-emitting region. Is generated. The light emitting layer 4 can have, for example, a multiple quantum well (MQW) structure in which barrier layers and well layers are alternately stacked over a plurality of periods. In this case, the barrier layer and the well layer are made of InGaN, and the band gap of the barrier layer is configured to be larger than the band gap of the well layer by appropriately selecting the composition of In (indium). The light emitting region is generated in a region where carriers are injected in the light emitting layer 4.

  The p-type semiconductor region 5 includes a p-type nitride semiconductor. In the present embodiment, the p-type semiconductor region 5 is formed by epitaxially growing AlGaN on the light emitting layer 4 and has p-type conductivity by adding a p-type dopant such as Mg. The p-type semiconductor region 5 may have a composition that has a refractive index smaller than that of the light emitting layer 4 and a larger band gap. In this case, the p-type semiconductor region 5 serves as an upper cladding for the light emitting layer 4.

  A cathode electrode 6 is formed on the n-type semiconductor region 3. The cathode electrode 6 is made of a conductive material and realizes ohmic contact with the n-type semiconductor region 3. An anode electrode 7 is formed on the p-type semiconductor region 5. The anode electrode 7 is made of a conductive material, and has an ohmic contact with the p-type semiconductor region 5. Bump electrodes 8 are formed on the cathode electrode 6 and the anode electrode 7.

  In the semiconductor light emitting device 1 having the above-described configuration, when a predetermined voltage is applied between the anode electrode 7 (bump electrode 8) and the cathode electrode 6 (bump electrode 8) and a current flows, the light emitting region 4 emits light. Luminescence will occur.

  The semiconductor light emitting element 1 is bump-connected to a pair of external electrodes 27 and 28. That is, the cathode electrode 6 is electrically and physically connected to the external electrode 28 via the bump electrode 8. The anode electrode 7 is electrically and physically connected to the external electrode 27 through the bump electrode 8. Thereby, the varistor part comprised by the 1st electrode part 33, the 1st electrode part 43, and the area | region which overlaps with the 1st electrode parts 33 and 43 in a varistor layer is connected to the semiconductor light emitting element 1 in parallel. It will be.

  As described above, according to the first embodiment, since the multilayer chip varistor 11 is connected in parallel to the semiconductor light emitting element 1, the semiconductor light emitting element 1 can be protected from the ESD surge.

  In the first embodiment, since the multilayer chip varistor 11 includes the external electrodes 27 and 28 connected to the semiconductor light emitting element 1 and the internal electrodes 31 and 41 connected to the external electrodes 27 and 28, the semiconductor light emitting element The heat generated in 1 is mainly transmitted to and dissipated in the external electrodes 27 and 28 and the internal electrodes 31 and 41. The heat radiation path of the heat generated in the semiconductor light emitting element 1 is expanded, and the heat generated in the semiconductor light emitting element 1 can be efficiently dissipated.

  In the first embodiment, the varistor layer is mainly composed of ZnO. ZnO has a thermal conductivity comparable to that of alumina or the like normally used as a heat dissipation substrate, and has a relatively good thermal conductivity. Therefore, it is possible to suppress the heat dissipation from the internal electrodes 31 and 41 from being inhibited by the varistor layer.

  By the way, in the multilayer chip varistor 11 of the first embodiment, both the external electrode 25 functioning as an input terminal electrode and the external electrode 26 functioning as an output terminal electrode are arranged on one main surface 22 of the varistor element body 21. ing. That is, the multilayer chip varistor 11 is a multilayer chip varistor formed as a BGA (Ball Grid Array) package. The multilayer chip varistor 11 is configured such that each external electrode 25, 26 and a land corresponding to each external electrode 25, 26 are electrically and mechanically connected by using solder balls, bump electrodes, etc. And mounted on external devices.

  Further, according to the first embodiment, the green body GL1 includes Pr, the conductive paste for the first electrode layers 25a to 28a of the external electrodes 25 to 28 includes Pd, and the conductive paste is applied. Since the green body GL1 is fired to obtain the varistor element body 21 and the first electrode layers 25a to 28a, the varistor element body 21 and the first electrode layers 25a to 28a are simultaneously fired. Thereby, the adhesive strength between the varistor element body 21 and the external electrodes 25 to 28 (first electrode layers 25a to 28a) can be improved.

The effect of improving the adhesive strength between the varistor element body 21 and the external electrodes 25 to 28 is considered to be caused by the following event during firing. When the green body GL1 and the conductive paste are fired, Pr contained in the green body GL1 moves near the surface of the green body GL1, that is, near the interface between the green body GL1 and the conductive paste. Then, Pr moved to the vicinity of the interface between the green body GL1 and the conductive paste and Pd contained in the conductive paste mutually diffuse. When Pr and Pd are interdiffused, an oxide of Pr and Pd (for example, Pr ₂ Pd ₂ O ₅ or Pr ₄ ) is provided in the vicinity (including the interface) between the varistor element body 21 and the external electrodes 25 to 28. PdO ₇ etc.) may be formed. An anchor effect is generated by the oxide of Pr and Pd, and the adhesive strength between the varistor element body 21 obtained by firing and the external electrodes 25 to 28 is improved.

  A multilayer chip varistor formed as a BGA package has a particularly small area of an external electrode functioning as an input / output terminal electrode or a ground terminal electrode. For this reason, the adhesive strength between the varistor element body and the external electrode is lowered, and the external electrode may be peeled off from the varistor element body. However, in the multilayer chip varistor 11 according to the first embodiment, as described above, the adhesive strength between the varistor element body 21 and the external electrodes 25 to 28 (first electrode layers 25a to 28a) is improved. The electrodes 25 to 28 are not peeled off from the varistor element body 21.

  When the conductive paste for forming the first electrode layers 25a to 28a contains glass frit, a glass component may be deposited on the surfaces of the first electrode layers 25a to 28a during firing. Plating properties and solderability may be deteriorated. However, in the first embodiment, since the conductive paste for forming the first electrode layers 25a to 28a does not include glass frit, the plating property and the solderability are not deteriorated.

  In the first embodiment, a pair of external electrodes 25, 26 are formed on one main surface 22 of the varistor element body 21, and a pair of external electrodes 27, 28 are opposed to the one main surface 22. 23 is formed. The first and second internal electrodes 31, 41 are exposed to the first electrode portions 33, 43 that overlap each other and the one main surface 22 and the other main surface 23 from the first electrode portions 33, 43. 2nd electrode part 35a, 35b, 45a, 45b pulled out by (3). The plurality of external electrodes 25 to 28 are electrically connected to the corresponding internal electrodes 31 and 41 through the second electrode portions 35a, 35b, 45a, and 45b. In this case, the semiconductor light emitting element 1 is mounted on the multilayer chip varistor 11 by connecting to the external electrodes 27 and 28. Therefore, mounting for electrically and physically connecting the semiconductor light emitting element 1 and the external electrodes 27 and 28 can be performed easily and simply. In addition, the multilayer chip varistor 11 is mounted on an external substrate, an external device, or the like with one main surface 22 on which the external electrodes 25, 26 are formed facing the external substrate, the external device, or the like. . Therefore, the multilayer chip varistor 11 can be mounted easily and simply.

  In the first embodiment, the semiconductor light emitting device 1 is disposed on the multilayer chip varistor 11 by being bump-connected to the pair of external electrodes 27 and 28. Thereby, the mounting of the semiconductor light emitting element 1 on the multilayer chip varistor 11 can be performed very easily and simply.

  In the first embodiment, one main surface 22 and the other main surface 23 extend in a direction parallel to the stacking direction of the varistor element body 21, that is, the stacking direction of the varistor layers. Accordingly, the internal electrodes 31 and 41 are juxtaposed along the direction in which the one main surface 22 and the other main surface 23 extend with respect to the one main surface 22 and the other main surface 23. As a result, for each internal electrode 31, 41, a heat radiation path from the internal electrode 31, 41 to one main surface 22 and the other main surface 23 of the varistor element body 21, that is, to the outer surface of the multilayer chip varistor 11. The heat dissipation path is shortened, and heat can be dissipated from the internal electrodes 31 and 41 more efficiently.

(Second Embodiment)
With reference to FIG. 7, the structure of light-emitting device LE2 which concerns on 2nd Embodiment is demonstrated. FIG. 7 is a view for explaining a cross-sectional configuration of the multilayer chip varistor according to the second embodiment. The light emitting device LE2 according to the second embodiment is different from the light emitting device LE1 according to the first embodiment with respect to the configuration of the multilayer chip varistor.

  The light emitting device LE2 includes a semiconductor light emitting element 1 and a multilayer chip varistor 51, as shown in FIG. The semiconductor light emitting element 1 is disposed on a multilayer chip varistor 51. The multilayer chip varistor 51 includes a multilayer body 53 and a pair of external electrodes 55 and 56 respectively formed on the multilayer body 53. The external electrode 55 functions as an input terminal electrode of the multilayer chip varistor 51, and the external electrode 56 functions as an output terminal electrode of the multilayer chip varistor 51.

  The laminated body 53 includes a varistor part 57 and a pair of outer layer parts 59 arranged so as to sandwich the varistor part 57, and is configured by laminating the varistor part 57 and the pair of outer layer parts 59. Yes. The laminated body 53 has a rectangular parallelepiped shape. The stacked body 53 is opposed to each other and extends in a direction parallel to the stacking direction of the stacked body 53, and a pair of side surfaces that are adjacent to the pair of end surfaces 53 a and 53 b and face each other. (Outer surface) 53c, 53d. The pair of side surfaces 53 c and 53 d are orthogonal to the stacking direction of the stacked body 53.

  The varistor portion 57 includes a varistor layer 61 that exhibits varistor characteristics, and a plurality of internal electrodes 63 and 64 that are disposed so as to sandwich the varistor layer 61. In the varistor part 57, the varistor layers 61 and the internal electrodes 63 and 64 are alternately laminated. In the varistor layer 61, regions that overlap with a pair of adjacent internal electrodes 63 and 64 function as regions that exhibit varistor characteristics. The thickness of the internal electrodes 63 and 64 is, for example, about 0.5 to 5 μm. The actual multilayer chip varistor 51 is integrated to such an extent that the boundary between the varistor layer 61 and the boundary between the varistor layer 61 and the outer layer portion 59 are not visible.

  The varistor layer 61 contains ZnO (zinc oxide) as a main component and also includes rare earth metal elements, Co, IIIb group elements (B, Al, Ga, In), Si, Cr, Mo, and alkali metal elements (K) as subcomponents. , Rb, Cs) and alkaline earth metal elements (Mg, Ca, Sr, Ba) and the like, and element bodies containing these oxides. In the present embodiment, the varistor layer contains Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents. Thereby, a region overlapping with a pair of adjacent internal electrodes 63 and 64 contains ZnO as a main component and contains Pr. In the present embodiment, as in the first embodiment, Pr is used as the rare earth metal.

  The plurality of internal electrodes 63 and 64 are provided substantially in parallel so that one end of each of the internal electrodes 63 and 64 is alternately exposed on the end faces 53 a and 53 b facing each other in the stacked body 53. These internal electrodes 63 and 64 contain a conductive material. The conductive material included in the internal electrodes 63 and 64 is not particularly limited, but is preferably made of Pd or an Ag—Pd alloy. The plurality of internal electrodes 63 and 64 are juxtaposed along the stacking direction of the stacked body 53, that is, the opposing direction of the pair of side surfaces 53 c and 53 d.

  Similar to the varistor layer 61, the outer layer portion 59 contains ZnO as a main component, and includes rare earth metal elements, Co, IIIb group elements (B, Al, Ga, In), Si, Cr, Mo, and alkali metals as subcomponents. It consists of elemental bodies including simple metals such as elements (K, Rb, Cs) and alkaline earth metal elements (Mg, Ca, Sr, Ba) and oxides thereof. In the present embodiment, the outer layer portion 59 includes Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents included in the outer layer portion 59. In the present embodiment, Pr is used as the rare earth metal.

  The pair of external electrodes 55 and 56 are provided so as to cover both end portions of the multilayer body 53. The pair of external electrodes 55 and 56 include first electrode portions 55a and 56a, second electrode portions 55b and 56b, and third electrode portions 55c and 56c, respectively. The first electrode portion 55a is formed on one end surface 53a. The first electrode portion 56a is formed on the other end surface 53b. The second electrode portion 55b is formed on one side surface 53c so as to be continuous with the first electrode portion 55a. The second electrode portion 56b is formed on one side surface 53c so as to be continuous with the first electrode portion 56a. The third electrode portion 55c is formed on the other side surface 53d so as to be continuous with the first electrode portion 55a. The third electrode portion 56c is formed on the other side surface 53d so as to be continuous with the first electrode portion 56a.

  The internal electrode 63 is electrically and physically connected to the first electrode portion 55a of the external electrode 55 at one end exposed at the end face 53a. The internal electrode 64 is electrically and physically connected to the first electrode portion 56a of the external electrode 56 at one end exposed at the end face 53b.

  The external electrodes 55 and 56 contain Pd. The external electrodes 55 and 56 are formed by baking a conductive paste. As the conductive paste, a mixture of a metal powder containing Ag—Pd alloy particles as a main component and an organic binder and an organic solvent is used. The metal powder may be mainly composed of Pd particles. The external electrodes 55 and 56 are obtained by simultaneous firing with the stacked body 53 as in the first embodiment. A metal layer may be formed on the surfaces of the external electrodes 55 and 56 so as to cover the external electrodes 55 and 56. As a material for this metal layer, Au, Pt, Sn, Sn alloy, Ag, or the like can be used. The metal layer can be formed by a plating method or the like.

  The semiconductor light emitting element 1 is disposed on a side surface 53c orthogonal to the stacking direction of the stacked body 53 (varistor layer 61), and is bump-connected to a pair of external electrodes 55 and 56. That is, the cathode electrode 6 is electrically and physically connected to the external electrode 55 via the bump electrode 8. The anode electrode 7 is electrically and physically connected to the external electrode 56 through the bump electrode 8.

  As described above, according to the second embodiment, since the multilayer chip varistor 51 is connected in parallel to the semiconductor light emitting element 1, the semiconductor light emitting element 1 can be protected from the ESD surge.

  In the second embodiment, since the multilayer chip varistor 11 includes the external electrodes 55 and 56 connected to the semiconductor light emitting element 1 and the internal electrodes 63 and 64 connected to the external electrodes 55 and 56, the semiconductor light emitting element. 1 is mainly transmitted to the external electrodes 55 and 56 and the internal electrodes 63 and 64 to be dissipated. The heat radiation path of the heat generated in the semiconductor light emitting element 1 is expanded, and the heat generated in the semiconductor light emitting element 1 can be efficiently dissipated.

  In the second embodiment, the varistor layer 61 is mainly composed of ZnO. ZnO has a thermal conductivity comparable to that of alumina or the like normally used as a heat dissipation substrate, and has a relatively good thermal conductivity. Therefore, it is possible to suppress the heat dissipation from the internal electrodes 63 and 64 from being inhibited by the varistor layer 61.

  Further, according to the second embodiment, since the laminate 53 and the external electrodes 55 and 56 are obtained by simultaneous firing as in the first embodiment, the adhesive strength between the laminate 53 and the external electrodes 55 and 56 is increased. Can be improved.

(Third embodiment)
With reference to FIG.8 and FIG.9, the structure of light-emitting device LE3 which concerns on 3rd Embodiment is demonstrated. FIG. 8 is a view for explaining a cross-sectional configuration of the multilayer chip varistor according to the third embodiment. FIG. 9 is a diagram for explaining a cross-sectional configuration along the line IX-IX in FIG. 8. The light emitting device LE3 according to the third embodiment is different from the light emitting device LE1 according to the first embodiment with respect to the configuration of the multilayer chip varistor.

  The light emitting device LE3 includes a semiconductor light emitting element 1 and a multilayer chip varistor 71 as shown in FIGS. The semiconductor light emitting element 1 is disposed on a multilayer chip varistor 71.

  Similar to the multilayer chip varistor 51 of the second embodiment, the multilayer chip varistor 71 includes a multilayer body 53 and a pair of external electrodes 55 and 56. In the multilayer chip varistor 71, the plurality of internal electrodes 63 and 64 are orthogonal to the stacking direction of the stacked body 53 (varistor layer 61) (the facing direction of the pair of side surfaces 53c and 53d) and the facing direction of the pair of end surfaces 53a and 53b. It is juxtaposed along the direction. The stacked body 53 includes a pair of side surfaces (outer surfaces) 53e and 53f that are adjacent to the pair of end surfaces 53a and 53b and face each other. The pair of side surfaces 53 e and 53 f extend in a direction parallel to the stacking direction of the stacked body 53.

  The first electrode portion 55a of the external electrode 55 is formed on one end surface 53a. The first electrode portion 56a of the external electrode 56 is formed on the other end surface 53b. The second electrode portions 55b and 56b are formed on one side surface 53e so as to be continuous with the corresponding first electrode portions 55a and 56a. The third electrode portions 55c and 56c are formed on the other side surface 53f so as to be continuous with the first electrode portions 55a and 56a. The semiconductor light emitting element 1 is disposed on a surface of the multilayer chip varistor 71 that extends in a direction parallel to the stacking direction of the stacked body 53, that is, on the side surface 53 e of the stacked body 53.

  In the third embodiment, since the multilayer chip varistor 71 is connected in parallel to the semiconductor light emitting element 1, the semiconductor light emitting element 1 can be protected from an ESD surge.

  Also in the third embodiment, as in the second embodiment, the multilayer chip varistor 11 has external electrodes 55 and 56 connected to the semiconductor light emitting element 1 and internal electrodes 63 and 64 connected to the external electrodes 55 and 56. Therefore, the heat generated in the semiconductor light emitting element 1 is mainly transmitted to the external electrodes 55 and 56 and the internal electrodes 63 and 64 and is dissipated. The heat radiation path of the heat generated in the semiconductor light emitting element 1 is expanded, and the heat generated in the semiconductor light emitting element 1 can be efficiently dissipated. In addition, since the varistor layer 61 is mainly composed of ZnO, it is possible to suppress the heat dissipation from the internal electrodes 63 and 64 from being inhibited by the varistor layer 61.

  In the third embodiment, the semiconductor light emitting element 1 is disposed so as to face a surface of the multilayer chip varistor 71 that extends in a direction parallel to the stacking direction of the stacked body 53. Thus, the plurality of internal electrodes 63 and 64 are juxtaposed along the direction in which the surface extends with respect to the surface of the multilayer chip varistor 71 facing the surface on which the semiconductor light emitting element 1 is disposed. As a result, with respect to each internal electrode 63, 64, the heat radiation path from the internal electrode 63, 64 to the outer surface of the multilayer chip varistor 71 is shortened, and heat dissipation from the internal electrodes 63, 64 is performed more efficiently. be able to.

  In the third embodiment, the pair of external electrodes 55 and 56 are first electrode portions formed on the pair of end faces 53 a and 53 b that face each other and extend in a direction parallel to the stacking direction of the stacked body 53. 55a, 56a and a second side surface 53e formed adjacent to the pair of end surfaces 53a, 53b on which the first electrode portions 55a, 56a are formed and extending in a direction parallel to the stacking direction of the stacked body 53. Electrode portions 55b and 56b. In this case, the semiconductor light emitting element 1 is mounted on the multilayer chip varistor 71 by being connected to the second electrode portions 55b and 56b. Therefore, mounting for electrically connecting the semiconductor light emitting element 1 and the external electrodes 55 and 56 can be performed easily and simply.

  In the multilayer chip varistors 11 and 51 according to the first to third embodiments, the varistor element bodies 21 and 53 (varistor layers) do not contain Bi. The reason why the varistor element bodies 21 and 53 do not contain Bi is as follows. When the varistor element body contains ZnO as a main component and contains Bi, and the external electrode has an electrode layer formed on the outer surface of the varistor element body by simultaneous firing with the varistor element body and including Pd, By simultaneous firing of the varistor element body and the electrode layer, Bi and Pd are alloyed, and an alloy of Bi and Pd is formed at the interface between the varistor element body and the electrode layer. The alloy of Bi and Pd has particularly poor wettability with the varistor element body, and acts to reduce the adhesive strength between the varistor element body and the electrode layer. For this reason, it becomes difficult to ensure the adhesive strength between the varistor element body and the electrode layer in a desired state.

  The preferred embodiments of the present invention have been described above, but the present invention is not necessarily limited to these embodiments.

  The multilayer chip varistor 11 described above has a pair of internal electrodes 31 and 41, but is not limited thereto. For example, similarly to the multilayer chip varistors 51 and 71 of the second and third embodiments, a plurality of first internal electrodes 31 and second internal electrodes 41 may be provided.

  In the first to third embodiments, a GaN-based semiconductor LED is used as the semiconductor light emitting element 1, but is not limited thereto. As the semiconductor light emitting element 1, for example, a nitride semiconductor LED other than GaN-based (for example, InGaNAs-based semiconductor LED), a compound semiconductor LED other than nitride-based, or a laser diode (LD) may be used. .

1 is a schematic top view showing a multilayer chip varistor according to a first embodiment. 1 is a schematic bottom view showing a multilayer chip varistor according to a first embodiment. It is a figure for demonstrating the cross-sectional structure along the III-III line in FIG. It is a figure for demonstrating the cross-sectional structure along the IV-IV line | wire in FIG. It is a flowchart for demonstrating the manufacturing process of the multilayer chip varistor which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing process of the multilayer chip varistor which concerns on 1st Embodiment. It is a figure for demonstrating the cross-sectional structure of the multilayer chip varistor which concerns on 2nd Embodiment. It is a figure for demonstrating the cross-sectional structure of the multilayer chip varistor which concerns on 3rd Embodiment. It is a figure for demonstrating the cross-sectional structure along the IX-IX line in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor light-emitting device, 11 ... Multilayer chip varistor, 21 ... Varistor element body, 22 ... One main surface, 23 ... Other main surface, 25-28 ... External electrode, 25a-28a ... 1st electrode layer, 25b to 28b ... second electrode layer, 31 ... first internal electrode, 33 ... first electrode portion, 35a, 35b ... second electrode portion, 41 ... second internal electrode, 43 ... first electrode 45a, 45b ... second electrode part, 51 ... stacked chip varistor, 53 ... laminated body, 53a, 53b ... end face, 53c-53f ... side surface, 55 ... external electrode, 55a ... first electrode part, 55b ... second electrode part, 55c ... third electrode part, 56 ... external electrode, 56a ... first electrode part, 56b ... second electrode part, 56c ... third electrode part, 61 ... varistor layer, 63 64 ... Internal electrode 71 ... Multilayer chip varistor LE1~LE3 ... light-emitting device.

Claims (10)

A semiconductor light emitting device and a multilayer chip varistor,
The multilayer chip varistor is
A laminate having a varistor layer mainly composed of ZnO and a plurality of internal electrodes arranged so as to sandwich the varistor layer;
A plurality of external electrodes formed on the outer surface of the laminate and connected to corresponding internal electrodes among the plurality of internal electrodes, and
The semiconductor light emitting device is disposed on the multilayer chip varistor and connected to a corresponding external electrode among the plurality of external electrodes so as to be connected in parallel to the multilayer chip varistor. .   2. The light emitting device according to claim 1, wherein the semiconductor light emitting element is disposed so as to face a surface of the multilayer chip varistor extending in a direction parallel to the stacking direction of the stacked body. The plurality of external electrodes include a pair of terminal electrodes,
The pair of terminal electrodes are
A first electrode portion formed on a pair of outer surfaces facing each other and extending in a direction parallel to the stacking direction of the stacked body;
Each including a second electrode portion formed on one outer surface adjacent to the pair of outer surfaces on which the first electrode portions are formed and extending in a direction parallel to the stacking direction of the stacked body. The light-emitting device according to claim 1. The varistor layer comprises Pr;
2. The light emitting device according to claim 1, wherein the plurality of external electrodes have an electrode layer formed on the outer surface of the multilayer body by being simultaneously fired with the multilayer body and including Pd. The varistor layer comprises Pr;
The plurality of external electrodes have an electrode layer formed on the outer surface of the laminate and including Pd,
2. The light emitting device according to claim 1, wherein an oxide of Pr contained in the varistor layer and Pd contained in the electrode layer exists in the vicinity of an interface between the stacked body and the electrode layer.   The light emitting device according to claim 5, wherein the electrode layer is formed on the outer surface of the multilayer body by being simultaneously fired with the multilayer body. The plurality of external electrodes are
A pair of terminal electrodes formed on one outer surface of the outer surfaces of the laminate and electrically connected to corresponding internal electrodes among the plurality of internal electrodes,
A pair of pad electrodes formed on an outer surface opposite to the outer surface on which the pair of terminal electrodes are formed and electrically connected to corresponding internal electrodes among the plurality of internal electrodes,
The plurality of internal electrodes are
A first electrode portion overlapping between adjacent internal electrodes of the plurality of internal electrodes;
A second electrode portion that is drawn from the first electrode portion so as to be exposed on the outer surface on which the pair of terminal electrodes are formed and on the outer surface on which the pair of pad electrodes are formed. And
2. The light emitting device according to claim 1, wherein the pair of terminal electrodes and the pair of pad electrodes are electrically connected to the corresponding internal electrodes through the second electrode portion.   8. The outer surface on which the pair of terminal electrodes are formed and the outer surface on which the pair of pad electrodes are formed extend in a direction parallel to the stacking direction of the stacked body. Light emitting device.   The light emitting device according to claim 7, wherein the semiconductor light emitting element is disposed on the multilayer chip varistor by being bump-connected to the pair of pad electrodes. The semiconductor light emitting element has a first conductivity type semiconductor region and a second conductivity type semiconductor region, and is applied between the first conductivity type semiconductor region and the second conductivity type semiconductor region. The light-emitting device according to claim 1, wherein the light-emitting device emits light according to a voltage.

Images