JP2006294930A - 半導体集積回路装置およびその実装方法 - Google Patents
半導体集積回路装置およびその実装方法 Download PDFInfo
- Publication number
- JP2006294930A JP2006294930A JP2005114777A JP2005114777A JP2006294930A JP 2006294930 A JP2006294930 A JP 2006294930A JP 2005114777 A JP2005114777 A JP 2005114777A JP 2005114777 A JP2005114777 A JP 2005114777A JP 2006294930 A JP2006294930 A JP 2006294930A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- circuit device
- types
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】回路Aおよび回路Bといった2種類の回路を内部に有する半導体集積回路装置において、これら回路の各端子から引き出されるかたちで設けられた外部接続用のボンディングバッドBP1およびBP2を、これら回路の種類別に電気的に識別可能に関連付けする。具体的には、回路Aおよび回路Bに対する関連付けの別に異なる抵抗値に設定してこの抵抗値の差異により識別可能とする。こうして、これら関連付けされたボンディングバッドのいずれかの組合せの選択をもって回路Aおよび回路Bの選択的な外部接続が可能とされる構成とする。
【選択図】 図2
Description
(1)回路Aおよび回路Bといった2種類の回路を内部に有する半導体集積回路装置において、これら回路の各端子から引き出されるかたちで設けられた外部接続用のボンディングバッドBP1およびBP2を、これら回路の種類別に電気的に識別可能に関連付けする。こうして、これら関連付けされたボンディングバッドのいずれかの組合せの選択をもって上記回路Aや回路Bの選択的な外部接続が可能とされる構成とした。これにより、ウェハ完成後の工程においても、所望とされる回路を選択的に使用することができるようになり、ひいては、限られたチップスペースを有効に利用しながら実際に必要とされる数に対する完成品の過不足を抑制して、実情に即したかたちで製造の効率化を図ることができるようになる。
なお、上記実施の形態は、以下のように変更して実施してもよい。
・上記実施の形態においてはブレッドボードの評価に用いられる集積回路装置を想定したが、これに限られることなく、他の集積回路装置についてもこの発明は同様に適用することができる。
Claims (8)
- 複数種の回路を内部に有し、これら回路の各端子から引き出されるかたちで設けられた外部接続用のボンディングバッドが前記複数種の回路の種類別に電気的に識別可能に関連付けされて、これら回路の種類別に関連付けされたボンディングバッドのいずれか1つもしくは組合せの選択をもって、前記複数種の回路の選択的な外部接続が可能とされてなる
半導体集積回路装置。 - 複数種の回路素子を内部に有し、これら回路素子の各端子から引き出されるかたちで設けられた外部接続用のボンディングバッドが前記複数種の回路素子の種類別に電気的に識別可能に関連付けされて、これら回路素子の種類別に関連付けされたボンディングバッドのいずれか1つもしくは組合せの選択をもって、前記複数種の回路素子の選択的な外部接続が可能とされてなる
半導体集積回路装置。 - 前記ボンディングバッドは、前記関連付けの別に異なる抵抗値をもって、この抵抗値の差異により識別可能にされてなる
請求項1または2に記載の半導体集積回路装置。 - 当該半導体集積回路装置は、回路試作用の基板であるブレッドボードの評価に用いられる集積回路装置である
請求項1〜3のいずれか一項に記載の半導体集積回路装置。 - 複数種の回路を内部にもってこれら回路の各端子から引き出されるかたちで設けられた外部接続用のボンディングバッドが前記複数種の回路の種類別に関連付けされて構成される半導体集積回路装置をリードフレームにマウント、ボンディングするにあたって、所望とされる回路に関連付けされた前記ボンディングバッドを選択し、該選択されるボンディングバッドと前記リードフレーム側の対応するリード電極とをワイヤボンディングにより電気的に接続する
半導体集積回路装置の実装方法。 - 複数種の回路素子を内部にもってこれら回路素子の各端子から引き出されるかたちで設けられた外部接続用のボンディングバッドが前記複数種の回路素子の種類別に関連付けされて構成される半導体集積回路装置をリードフレームにマウント、ボンディングするにあたって、所望とされる回路素子に関連付けされた前記ボンディングバッドを選択し、該選択されるボンディングバッドと前記リードフレーム側の対応するリード電極とをワイヤボンディングにより電気的に接続する
半導体集積回路装置の実装方法。 - 前記ボンディングバッドの選択は、前記半導体集積回路装置に設けられた幾つかのボンディングバッドの中から所望とされるバッドが電気的に識別されることに基づいて行われる
請求項5または6に記載の半導体集積回路装置の実装方法。 - 前記電気的な識別は、前記関連付けの別に各異なる値に設定された前記ボンディングバッドの抵抗値の大小に基づいて行われる
請求項7に記載の半導体集積回路装置の実装方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005114777A JP2006294930A (ja) | 2005-04-12 | 2005-04-12 | 半導体集積回路装置およびその実装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005114777A JP2006294930A (ja) | 2005-04-12 | 2005-04-12 | 半導体集積回路装置およびその実装方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006294930A true JP2006294930A (ja) | 2006-10-26 |
Family
ID=37415166
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005114777A Pending JP2006294930A (ja) | 2005-04-12 | 2005-04-12 | 半導体集積回路装置およびその実装方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2006294930A (ja) |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63122242A (ja) * | 1986-11-12 | 1988-05-26 | Nec Corp | マスタ−スライス集積回路の構成方法 |
JPH01298737A (ja) * | 1988-05-27 | 1989-12-01 | Hitachi Ltd | 半導体装置 |
JPH0230156A (ja) * | 1988-07-19 | 1990-01-31 | Nec Corp | 半導体装置 |
JPH03203365A (ja) * | 1989-12-29 | 1991-09-05 | Nec Corp | 半導体集積回路 |
JPH0417355A (ja) * | 1990-05-10 | 1992-01-22 | Nec Ic Microcomput Syst Ltd | 半導体集積回路 |
JPH05243318A (ja) * | 1992-02-28 | 1993-09-21 | Toshiba Corp | 集積回路素子用ボンディングパッドの識別方法 |
JPH07193131A (ja) * | 1993-12-24 | 1995-07-28 | Nec Corp | 半導体集積回路装置 |
JPH07254628A (ja) * | 1994-03-16 | 1995-10-03 | Fujitsu Ltd | 半導体装置 |
JP2000357640A (ja) * | 1999-06-15 | 2000-12-26 | Nec Yamagata Ltd | 半導体装置の製造方法 |
JP2004527121A (ja) * | 2001-03-26 | 2004-09-02 | ミクロナス ゲーエムベーハー | 集積回路で配線オプションを具体化する方法、および集積回路 |
-
2005
- 2005-04-12 JP JP2005114777A patent/JP2006294930A/ja active Pending
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63122242A (ja) * | 1986-11-12 | 1988-05-26 | Nec Corp | マスタ−スライス集積回路の構成方法 |
JPH01298737A (ja) * | 1988-05-27 | 1989-12-01 | Hitachi Ltd | 半導体装置 |
JPH0230156A (ja) * | 1988-07-19 | 1990-01-31 | Nec Corp | 半導体装置 |
JPH03203365A (ja) * | 1989-12-29 | 1991-09-05 | Nec Corp | 半導体集積回路 |
JPH0417355A (ja) * | 1990-05-10 | 1992-01-22 | Nec Ic Microcomput Syst Ltd | 半導体集積回路 |
JPH05243318A (ja) * | 1992-02-28 | 1993-09-21 | Toshiba Corp | 集積回路素子用ボンディングパッドの識別方法 |
JPH07193131A (ja) * | 1993-12-24 | 1995-07-28 | Nec Corp | 半導体集積回路装置 |
JPH07254628A (ja) * | 1994-03-16 | 1995-10-03 | Fujitsu Ltd | 半導体装置 |
JP2000357640A (ja) * | 1999-06-15 | 2000-12-26 | Nec Yamagata Ltd | 半導体装置の製造方法 |
JP2004527121A (ja) * | 2001-03-26 | 2004-09-02 | ミクロナス ゲーエムベーハー | 集積回路で配線オプションを具体化する方法、および集積回路 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6218202B1 (en) | Semiconductor device testing and burn-in methodology | |
DE60233902D1 (de) | Stapelbare schichten die eingekapselte integrierte schaltungschips mit einer oder mehreren darüberliegenden verbindungsschichten beinhalten und verfahren zu deren herstellung | |
JP2005286345A (ja) | 複数の接地面を備えた半導体素子 | |
JP2001085610A (ja) | マルチチップ半導体モジュール及びその製造方法 | |
JP5131812B2 (ja) | 半導体装置 | |
US9698087B2 (en) | Semiconductor device, corresponding methods of production and use and corresponding apparatus | |
US20160240458A1 (en) | Package | |
JP2006294930A (ja) | 半導体集積回路装置およびその実装方法 | |
JP2006080564A (ja) | 半導体装置のパッケージ構造 | |
JP2007227727A (ja) | モジュールパッケージおよび内蔵する半導体の温度検査方法 | |
US7105923B2 (en) | Device and method for including passive components in a chip scale package | |
US10031179B2 (en) | Testing method | |
JP2007096216A (ja) | 半導体集積回路装置 | |
TWI595617B (zh) | 利用印刷電路板的多裸片堆疊方法及利用其的半導體封裝件 | |
JP2005347470A (ja) | 半導体パッケージ用中継基板、半導体サブパッケージおよび半導体装置 | |
JPH1079466A (ja) | 半導体装置 | |
KR20080051197A (ko) | 반도체 패키지 | |
KR101404014B1 (ko) | 3차원 패키징 모듈 | |
US20170077065A1 (en) | Semiconductor storage device and manufacturing method thereof | |
JPH0778938A (ja) | 複合半導体装置及びその製造方法 | |
US9991196B2 (en) | Printed circuit board and method of fabricating an element | |
US9633959B2 (en) | Integrated circuit die with corner IO pads | |
US20190131197A1 (en) | Quad flat no-lead package | |
TWI571996B (zh) | 承載器陣列以及發光二極體封裝結構 | |
JP4388989B2 (ja) | 半導体チップマウント封止サブ基板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070627 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080110 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100420 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100609 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100810 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101004 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20101102 |