JP2006294899A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2006294899A
JP2006294899A JP2005114338A JP2005114338A JP2006294899A JP 2006294899 A JP2006294899 A JP 2006294899A JP 2005114338 A JP2005114338 A JP 2005114338A JP 2005114338 A JP2005114338 A JP 2005114338A JP 2006294899 A JP2006294899 A JP 2006294899A
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semiconductor device
heat sink
lead
resin
semiconductor element
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Shuichi Ogata
秀一 尾方
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of ensuring the sufficient heat dissipation characteristics and improving the mounting reliability, and its manufacturing method. <P>SOLUTION: The semiconductor device incorporates a heat sink (11) with at least one or more notches (5a and 5b), a lead frame (15) comprising many inner leads (3i), a semiconductor element (4) mounted on the heat sink (11), a bonding pad (7) attached on this semiconductor element (4), and a resin for sealing a wire (2) used for electrical connection of the inner leads (3i). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体装置及びその製造方法、特に、車載用ＤＶＤ、ＤＴＶ等で用いられている高消費電力の半導体装置及びその製造方法に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a high power consumption semiconductor device used in an in-vehicle DVD, a DTV and the like and a manufacturing method thereof.

近年、電子機器の多機能化、小型化、高密度化に対応するために半導体装置などの半導体部品の高密度、高機能化、システム化が要求され、それに伴って半導体部品の消費電力が増大してきているのが現状であり、これらの消費電力増大により発生する熱を発散させるため、一般的な半導体装置にあってはその放熱性を向上させるためのダイパッドを露出するか、放熱板を内蔵あるいは露出させる構造を有している。   In recent years, there has been a demand for higher density, higher functionality, and systematization of semiconductor components such as semiconductor devices in order to cope with multifunctionalization, miniaturization, and higher density of electronic devices, and the power consumption of semiconductor components has increased accordingly. Currently, in order to dissipate the heat generated by the increase in power consumption, a general semiconductor device exposes a die pad to improve its heat dissipation or incorporates a heat sink Or it has the structure to expose.

以下、このような放熱手段を有する従来の半導体装置について説明する。   Hereinafter, a conventional semiconductor device having such a heat dissipation means will be described.

図９は従来の放熱板内蔵の半導体装置を示す構成図であり、図９(ａ)は透過平面図、図９(ｂ)は断面図、図９(ｃ)は一部拡大透過平面図である。図１０は図９に示す半導体装置の発熱による変化の説明図であり図１０(ａ)は一部平面図、図１０(ｂ)は発熱による内部応力の説明図、図１０(ｃ)は変形の説明図である。   9A and 9B are configuration diagrams showing a conventional semiconductor device with a built-in heat sink. FIG. 9A is a transmission plan view, FIG. 9B is a cross-sectional view, and FIG. 9C is a partially enlarged transmission plan view. is there. FIG. 10 is an explanatory diagram of changes due to heat generation of the semiconductor device shown in FIG. 9, FIG. 10 (a) is a partial plan view, FIG. 10 (b) is an explanatory diagram of internal stress due to heat generation, and FIG. It is explanatory drawing of.

各図において、１は半導体装置、２はワイヤー、３はリード、３ｉはインナーリード、３ｏはアウターリード、４は半導体素子、９は収縮応力の強さを表した矢印、１０は封止樹脂体、１１はダイパッド等の放熱板である。   In each figure, 1 is a semiconductor device, 2 is a wire, 3 is a lead, 3i is an inner lead, 3o is an outer lead, 4 is a semiconductor element, 9 is an arrow indicating the strength of shrinkage stress, and 10 is a sealing resin body , 11 is a heat sink such as a die pad.

図９から明らかなように半導体素子４には放熱板１１が接合され、これらを封止樹脂１０で封止した構成になっており、このような構成はダイパッドあるいは放熱板１１を露出させたものに比べ基板設計への制約も少なく安価であるため取り扱いが容易であり、更に、インナーリード３ｉと接着剤を介して直接放熱板１１と接続しているため放熱性も良い。
特開平８−３２１５７７号公報 As is apparent from FIG. 9, the heat sink 11 is joined to the semiconductor element 4, and these are sealed with the sealing resin 10. Such a structure is obtained by exposing the die pad or the heat sink 11. Compared with the circuit board, there are few restrictions on the board design and it is inexpensive, so that it is easy to handle. Further, since it is directly connected to the heat radiating plate 11 via the inner lead 3i and an adhesive, heat dissipation is good.
JP-A-8-321577

しかしながら、上記従来の半導体装置は図１０（ｂ）に示すように発熱による収縮応力は矢印９で示すように上下の樹脂厚が異なるため上層部で強く、下層部で弱く（矢印の太さは収縮応力の強さを表す）なり、図１０（ｃ）に示すように樹脂と放熱板との収縮応力差により半導体装置全体に大きな反りが発生し、カスタマでの実装不良を多発させている。その対策として樹脂厚のバランスをよくするための構造も考えられるが放熱板内蔵ということもあり、加工が非常に困難であるという問題点があった。   However, in the conventional semiconductor device, as shown in FIG. 10B, the shrinkage stress due to heat generation is strong at the upper layer portion and weak at the lower layer portion because the upper and lower resin thicknesses are different as shown by the arrow 9 (the thickness of the arrow is As shown in FIG. 10C, a large warp is generated in the entire semiconductor device due to a difference in contraction stress between the resin and the heat sink, resulting in frequent mounting failures by customers. As a countermeasure, a structure for improving the balance of the resin thickness is conceivable. However, there is a problem that processing is very difficult due to the built-in heat sink.

本発明は、上記従来の問題点を解決するものであり、放熱特性を充分に確保し、実装信頼性を向上させることができる半導体装置及びその製造方法を提供することを目的とする。   The present invention solves the above-described conventional problems, and an object thereof is to provide a semiconductor device and a manufacturing method thereof that can sufficiently secure heat dissipation characteristics and improve mounting reliability.

本発明の半導体装置は、切り欠きを少なくとも１箇所以上設けた放熱板と、複数本のインナーリードからなるリードフレームと、前記放熱板上に搭載された半導体素子及び前記半導体素子上に設けられたボンディングパッドと、前記インナーリードを電気的に接続するワイヤーを封止する樹脂を備えたものである。また、本発明の半導体装置の製造方法は、インナーリードと放熱板を粘着テープで接着する工程と、前記放熱板の中央部の孔と吊りリードを挟むように切り欠きを各コーナーに金型で打ち抜く工程を備えたものである。   The semiconductor device according to the present invention is provided with a heat sink having at least one notch, a lead frame including a plurality of inner leads, a semiconductor element mounted on the heat sink, and the semiconductor element. A bonding pad and a resin that seals a wire that electrically connects the inner leads are provided. In addition, the semiconductor device manufacturing method of the present invention includes a step of bonding the inner lead and the heat sink with an adhesive tape, and a notch at each corner with a mold so as to sandwich the hole in the center of the heat sink and the suspension lead. It is equipped with a punching process.

以上のように、本発明によれば、放熱板に切り欠きを設けることにより樹脂と放熱板との収縮応力差を小さくすることができると共に応力バランスを均等にすることが可能であり、このように応力差を小さくすることで、反りを低減することができ、実装信頼性を充分確保できる品質の優れた半導体装置を提供することができる。   As described above, according to the present invention, it is possible to reduce the difference in shrinkage stress between the resin and the heat sink by providing a notch in the heat sink and to equalize the stress balance. Further, by reducing the stress difference, it is possible to provide a semiconductor device with excellent quality that can reduce warpage and sufficiently ensure mounting reliability.

以下、本発明の各実施の形態について図面を参照しながら説明する。なお、前記従来のものと同一の部分については同一符号を用いるものとする。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol shall be used about the same part as the said conventional thing.

（実施の形態１）
図１は本発明半導体装置の実施の形態１における構成図を示し、図１（ａ）は透過平面図、図１（ｂ）は断面図、図１（ｃ）は切り欠き部の拡大透過平面図、図２は本発明半導体装置の実施の形態１における切り欠きを示す放熱板の平面図、図３は本発明半導体装置の実施の形態１におけるダイボンディング工程の前工程の説明図、図４は本発明半導体装置の実施の形態１におけるダイボンディング工程の説明図、図５は本発明半導体装置の実施の形態１における樹脂封止工程の説明図、図６は図１に示す半導体装置の発熱による変化の説明図であり図６(ａ)は一部平面図、図６(ｂ)は発熱による内部応力の説明図、図６(ｃ)は変形の説明図である。 (Embodiment 1)
FIG. 1 shows a configuration diagram of a semiconductor device according to a first embodiment of the present invention, FIG. 1 (a) is a transmission plan view, FIG. 1 (b) is a sectional view, and FIG. 1 (c) is an enlarged transmission plane of a notch. 2 is a plan view of a heat sink showing a notch in the first embodiment of the semiconductor device of the present invention. FIG. 3 is an explanatory diagram of a pre-process of the die bonding process in the first embodiment of the semiconductor device of the present invention. FIG. 5 is an explanatory diagram of a die bonding process in the first embodiment of the semiconductor device of the present invention, FIG. 5 is an explanatory diagram of a resin sealing process in the first embodiment of the semiconductor device of the present invention, and FIG. 6 is a heat generation of the semiconductor device shown in FIG. 6A is a partial plan view, FIG. 6B is an explanatory view of internal stress due to heat generation, and FIG. 6C is an explanatory view of deformation.

各図において、１は半導体装置、２はワイヤー、３はリード、３ｉはインナーリード、３ｏはアウターリード、４は半導体素子、５ａは切り欠きで細くて長い形状をしている。６は吊りリード、７はボンディングパッド、９は収縮応力の強さを表した矢印、１０は封止樹脂体、１１はダイパッド等の放熱板、１２は接着剤である。   In each figure, 1 is a semiconductor device, 2 is a wire, 3 is a lead, 3i is an inner lead, 3o is an outer lead, 4 is a semiconductor element, and 5a is a notch and has a thin and long shape. 6 is a suspension lead, 7 is a bonding pad, 9 is an arrow indicating the strength of contraction stress, 10 is a sealing resin body, 11 is a heat sink such as a die pad, and 12 is an adhesive.

この構成は、各コーナーに切り欠き５ａを有する放熱板１１に接着剤１２を塗布して、その上に半導体素子４を固着する。その半導体素子４と放熱板１１の周辺にある複数本のインナーリード３ｉとそれぞれ電気的に接続されたワイヤー２と各インナーリード３ｉと一体的に連結された各アウターリード３ｏは封止樹脂体１０から導出され、これら放熱板１１、接着剤１２、半導体素子４、ワイヤー２及びインナーリード３ｉは封止樹脂体１０で封止されている。また、封止樹脂体１０は４辺形の平板状に成形されると共に、アウターリード３ｏは封止樹脂体１０の４辺からそれぞれ引き出されている。   In this configuration, the adhesive 12 is applied to the heat radiating plate 11 having the notches 5a at each corner, and the semiconductor element 4 is fixed thereon. A plurality of inner leads 3 i around the semiconductor element 4 and the heat sink 11 are electrically connected to the wires 2 and outer leads 3 o integrally connected to the inner leads 3 i are encapsulated resin bodies 10. The heat radiating plate 11, the adhesive 12, the semiconductor element 4, the wire 2 and the inner lead 3 i are sealed with a sealing resin body 10. Further, the sealing resin body 10 is formed into a quadrangular flat plate shape, and the outer leads 3o are drawn out from the four sides of the sealing resin body 10, respectively.

次にその製造工程について説明する。まず、インナーリード３ｉと、これにそれぞれ連結された各アウターリード３ｏをエッチングあるいはプレスで加工する第１の工程と、これらインナーリード３ｉを粘着性のポリイミドテープで直接放熱板１１に接続する第２の工程と、第２の工程を経た放熱板１１に孔と、吊りリード６に挟まれる位置に切り欠き５ａを金型で打ち抜く第３の工程により放熱板１１を整形し、次に、図３（ａ）に示すような半導体素子ボンディング装置（全容は図示せず）のステージ１６上において、この放熱板１１上に半導体素子４を固着するための接着剤１２を塗布する。接着剤１２の塗布はディスペンサ１７を用いて接着剤１２を滴下することにより行う。また、接着剤１２は一例として熱硬化性のエポキシ樹脂にＡｇ粉を混合させたＡｇペーストからなる。   Next, the manufacturing process will be described. First, a first step of processing the inner leads 3i and the respective outer leads 3o connected thereto by etching or pressing, and a second step of directly connecting the inner leads 3i to the heat radiating plate 11 with an adhesive polyimide tape. 3 and the third step of punching out the notch 5a with a mold at a position sandwiched between the hole and the suspension lead 6 in the heat sink 11 that has undergone the second step, On a stage 16 of a semiconductor element bonding apparatus (not shown in its entirety) as shown in (a), an adhesive 12 for fixing the semiconductor element 4 is applied on the heat radiating plate 11. Application of the adhesive 12 is performed by dropping the adhesive 12 using the dispenser 17. Moreover, the adhesive agent 12 consists of Ag paste which mixed Ag powder with the thermosetting epoxy resin as an example.

次に、図３（ｂ）に示すように、接着剤１２を塗布した放熱板１１上にコレット１８を用いて半導体素子４を搭載した後、別途設けられたヒートステージ上で加熱し、接着剤１２を硬化させる。一例として、半導体素子４は外形寸法が６ｍｍ角、厚さが０．２〜０．４ｍｍ程度のシリコン単結晶である。また、加熱条件は１８０〜２５０℃、３０秒から６０秒程度である。なお、接着剤１２の硬化はキュア炉を用いても良い。   Next, as shown in FIG.3 (b), after mounting the semiconductor element 4 using the collet 18 on the heat sink 11 which apply | coated the adhesive agent 12, it heats on the heat stage provided separately, and adhesive agent 12 is cured. As an example, the semiconductor element 4 is a silicon single crystal having an outer dimension of 6 mm square and a thickness of about 0.2 to 0.4 mm. The heating conditions are 180 to 250 ° C. and about 30 to 60 seconds. The curing of the adhesive 12 may be performed using a curing furnace.

次に、図４（ａ）に示すようにボンディングパッド７上にボールボンド実施する。ワイヤーボンド装置（全容は図示せず）のヒートステージ１９は無加工のフラットな状態で、インナーリード３ｉのワイヤーボンディング領域外周部を固定治具（図示せず）によって固定しながらキャピラリー１３により行われる。一例として、ワイヤーは、直径２０〜３５μｍのＡｕワイヤーを用いる。   Next, ball bonding is performed on the bonding pad 7 as shown in FIG. The heat stage 19 of the wire bonding apparatus (the whole is not shown) is performed by the capillary 13 while fixing the outer periphery of the wire bonding area of the inner lead 3i with a fixing jig (not shown) in an unprocessed flat state. . As an example, an Au wire having a diameter of 20 to 35 μm is used as the wire.

次に、図４（ｂ）及び図４（ｃ）に示すように放熱板１１に固着された半導体素子４のボンディングパッド７とインナーリード３ｉとをワイヤー２を用いてキャピラリー１３により電気的に接続する。   Next, as shown in FIGS. 4B and 4C, the bonding pads 7 of the semiconductor element 4 fixed to the heat sink 11 and the inner leads 3 i are electrically connected by the capillaries 13 using the wires 2. To do.

このようにして、各単位のインナーリード３ｉとアウターリード３ｏより形成される各単位のリードフレーム１５はこの単位毎にダイボンディング、ワイヤーボンディングされた後、これら単位リードフレーム群は一括して樹脂封止され、封止樹脂体１０が同時成形される。   In this way, each unit lead frame 15 formed from the inner lead 3i and the outer lead 3o of each unit is die-bonded and wire-bonded for each unit, and these unit lead frames are collectively sealed with resin. The sealing resin body 10 is simultaneously molded.

次に、樹脂封止工程を図５を参照しながら説明する。   Next, the resin sealing step will be described with reference to FIG.

図５はトランスファ成形装置を示しており、シリンダ装置（図示せず）によって型締めされる一対の上型２１と下型２２とを備えており、キャビティー上部２３とキャビティー下部２４とで、キャビティー単体を形成するように、それぞれ複数組み埋設されている。上型２１の合わせ面にはポット２５が開設されており、ポット２５にはシリンダ装置（図示せず）により進退されるプランジャー２６が成形材料としての樹脂を送給し得るように挿入されている。下型２２の合わせ面にはカル２７がポット２５と対向位置に配されて埋設されていると共に、ランナー２８がポット２７とそれぞれ接続されている。更に各ランナー２８の他端部はキャビティー下部２４にそれぞれ接続されており、その接続部にはゲート２９が樹脂をキャビティー内に注入し得るよう形成されている。また、下型２２の合わせ面には、単位リードフレーム１５の集合体であるリードフレーム重合体２０におけるリードフレーム１５の厚み分を逃げ得るように、逃がし部３０がその外形も若干大きめの長方形で、その厚さよりも若干浅い深さに成形されている。   FIG. 5 shows a transfer molding apparatus, which includes a pair of upper mold 21 and lower mold 22 clamped by a cylinder apparatus (not shown). A plurality of sets are embedded so as to form a single cavity. A pot 25 is opened on the mating surface of the upper mold 21, and a plunger 26 that is advanced and retracted by a cylinder device (not shown) is inserted into the pot 25 so that resin as a molding material can be fed. Yes. On the mating surface of the lower die 22, a cull 27 is arranged and buried at a position facing the pot 25, and a runner 28 is connected to the pot 27. Further, the other end of each runner 28 is connected to the cavity lower part 24, and a gate 29 is formed at the connecting part so that the resin can be injected into the cavity. Also, on the mating surface of the lower die 22, the relief portion 30 is a rectangle having a slightly larger outer shape so that the thickness of the lead frame 15 in the lead frame polymer 20 that is an assembly of the unit lead frames 15 can escape. The depth is slightly shallower than the thickness.

このように構成されているトランスファ成形装置を用い、樹脂封止は以下の方法で行われる。   Using the transfer molding apparatus configured as described above, resin sealing is performed by the following method.

即ち、１８０℃程度に加熱された前記トランスファ装置の封止金型の逃がし部３０にリードフレーム重合体２０を装着し封止金型を型締めする。次に、円錐形に打錠された樹脂（図示せず）をポット２５に挿入し、プランジャー２６により樹脂がカル２７、ランナー２８、ゲート２９を通じて各キャビティーに圧入される。注入後、樹脂が熱硬化されて封止樹脂体１０が形成されると、上型２１及び下型２２は型開きされるとともに、エジェクタ・ピン（図示せず）により封止樹脂体１０群が離型され、樹脂成形されたリードフレーム重合体２０はトランスファ成形装置から脱装される。   That is, the lead frame polymer 20 is mounted on the relief part 30 of the sealing mold of the transfer device heated to about 180 ° C., and the sealing mold is clamped. Next, a resin (not shown) compressed in a conical shape is inserted into the pot 25, and the resin is press-fitted into each cavity through a cull 27, a runner 28, and a gate 29 by a plunger 26. After the injection, when the resin is thermally cured to form the sealing resin body 10, the upper mold 21 and the lower mold 22 are opened, and the sealing resin body 10 group is formed by ejector pins (not shown). The lead frame polymer 20 which has been released and resin-molded is detached from the transfer molding apparatus.

このようにして、樹脂成形された封止樹脂体１０の内部には、放熱板１１、接着剤１２、半導体素子４、ワイヤー３、インナーリード３ｉが樹脂封止されることになる。   Thus, the heat sink 11, adhesive 12, semiconductor element 4, wire 3, and inner lead 3i are resin-sealed inside the resin-molded sealing resin body 10.

次に、樹脂成形されたリードフレーム重合体２０の封止樹脂体１０以外の部分に半田外装めっきを施す（図示せず）。リードフレーム１５の少なくとも半導体装置の完成品となる部分にＰｄめっきが施されている場合は、半田外装めっきは必要としない。   Next, solder exterior plating is applied to portions of the resin-molded lead frame polymer 20 other than the sealing resin body 10 (not shown). When Pd plating is applied to at least a portion of the lead frame 15 that is a finished product of the semiconductor device, solder exterior plating is not required.

半田外装めっきを経た後、あるいは半田外装めっきされる前の樹脂成形されたリードフレーム重合体２０を、切断装置（図示せず）によって、各単位リードフレーム毎に順次、ダムバー（図示せず）を切断する。   A dam bar (not shown) is sequentially applied to each unit lead frame by the cutting device (not shown) after the solder outer plating or before the resin outer plating is performed. Disconnect.

次に、リード成形装置（図示せず）によって、アウターリード１４に先端と内枠の一部を切断した後、アウターリード３ｏをガルウイング形状に屈曲成形し、内枠の一部を切断して半導体装置を外枠から切り離すことにより、半導体装置１が完成する。   Next, after cutting the tip of the outer lead 14 and a part of the inner frame with a lead molding device (not shown), the outer lead 3o is bent and formed into a gull wing shape, and a part of the inner frame is cut. The semiconductor device 1 is completed by separating the device from the outer frame.

このようにして製造された半導体装置１は図６に示すようにダイパット１１の四隅に切り欠き５ａが形成されているので半導体装置１の発熱に伴い樹脂厚の厚い上層部で強くなっていた収縮応力を図６（ｂ）示すように吸収し、略上下層部でバランスがとれた状態（矢印の太さは収縮応力の強さを表す）となり、図６（ｃ）示すように従来のものに比し半導体装置全体の反りを大幅に軽減することができ、カスタマでの実装不良を防ぐことが可能となる。   The semiconductor device 1 manufactured in this way has notches 5a formed at the four corners of the die pad 11 as shown in FIG. 6, so that the shrinkage that has been strengthened in the upper layer portion having a thick resin as the semiconductor device 1 generates heat. The stress is absorbed as shown in FIG. 6 (b), and a balance is achieved in the upper and lower layers (the thickness of the arrow indicates the strength of the contraction stress), and the conventional one is shown in FIG. 6 (c). Compared with this, the warpage of the entire semiconductor device can be greatly reduced, and it is possible to prevent mounting defects at the customer.

以上のように、本実施の形態によれば放熱板に切り欠きを設けることにより樹脂と放熱板との収縮応力差を小さくすることができると共に応力バランスを均等にすることも可能であり、反りを低減することができ、実装信頼性を充分確保できる品質の優れた半導体装置を提供することができる。なお、本実施の形態で示したリードフレームの成型にあたっては既存のリードフレームと同一プロセスで実施可能となるため、安定したコスト変動も無い製造が可能であり、さらに、ダイボンド、ワイヤーボンド工程も既存と同じステージを準備するだけで既存設備を活用し、安定した効率の良い製造が可能となる。   As described above, according to the present embodiment, by providing a notch in the heat sink, it is possible to reduce the shrinkage stress difference between the resin and the heat sink, and also to equalize the stress balance and warp. Therefore, it is possible to provide a semiconductor device with excellent quality that can sufficiently secure mounting reliability. In addition, since the lead frame shown in the present embodiment can be molded by the same process as that of the existing lead frame, it is possible to manufacture without stable cost fluctuation, and the die bond and wire bond processes are also existing. Just by preparing the same stage, it is possible to utilize the existing equipment and make stable and efficient production.

（実施の形態２）
図７は本発明半導体装置の実施の形態２における構成図を示し、図７（ａ）は透過平面図、図７（ｂ）は断面図、図７（ｃ）は切り欠き部の拡大透過平面図、図８は本発明半導体装置の実施の形態２における切り欠きを示す放熱板の平面図である。 (Embodiment 2)
FIG. 7 shows a configuration diagram of a semiconductor device according to a second embodiment of the present invention, FIG. 7 (a) is a transmission plan view, FIG. 7 (b) is a cross-sectional view, and FIG. 7 (c) is an enlarged transmission plane of a notch. 8 and 8 are plan views of the heat sink showing the notches in the second embodiment of the semiconductor device of the present invention.

本実施の形態は前記実施の形態１における切り欠きの形状を変更したものであり、その他の部分は実施の形態１と同様であるので同一部分には同一符号を用い、その詳細な説明は省略する。   In the present embodiment, the shape of the notch in the first embodiment is changed, and the other parts are the same as those in the first embodiment, so the same reference numerals are used for the same parts and the detailed description thereof is omitted. To do.

本実施の形態においては図８に示すように放熱板１１に設けられた切り欠き５ｂの形状は幅が広く短くなっており、長さが吊りリードの１／３〜１／２に設定されている。   In the present embodiment, as shown in FIG. 8, the shape of the notch 5b provided in the heat sink 11 is wide and short, and the length is set to 1/3 to 1/2 of the suspension lead. Yes.

以上のように、本実施の形態によれば幅が広く短い切り欠きを設けることにより樹脂と放熱板との収縮応力差を小さくすることができると共に応力バランスを均等にすることも可能であり、反りを低減することができる。この切り欠きの形状は前記実施の形態１の切り欠きよりも機械的強度大である。このように実施の形態１と同様、実装信頼性を充分確保できる品質の優れた半導体装置を提供することができる。   As described above, according to the present embodiment, it is possible to reduce the difference in shrinkage stress between the resin and the heat sink by providing a wide and short notch, and to equalize the stress balance, Warpage can be reduced. The shape of this notch is greater in mechanical strength than the notch of the first embodiment. As described above, similarly to the first embodiment, it is possible to provide a semiconductor device with excellent quality that can sufficiently ensure mounting reliability.

本発明の切り欠きを施した放熱板を含む半導体装置及び製造方法は、放熱性を損なわず実装信頼性を向上させ、半導体装置の安定生産に有用である。   The semiconductor device and the manufacturing method including the notched heat sink of the present invention improve the mounting reliability without impairing the heat dissipation, and are useful for stable production of the semiconductor device.

本発明半導体装置の実施の形態１における構成図Configuration diagram of Embodiment 1 of a semiconductor device of the present invention 本発明半導体装置の実施の形態１における切り欠きを示す放熱板の平面図The top view of the heat sink which shows the notch in Embodiment 1 of the semiconductor device of this invention 本発明半導体装置の実施の形態１におけるダイボンディング工程の前工程の説明図Explanatory drawing of the pre-process of the die bonding process in Embodiment 1 of the semiconductor device of the present invention 本発明半導体装置の実施の形態１におけるダイボンディング工程の説明図Explanatory drawing of the die bonding process in Embodiment 1 of the semiconductor device of this invention. 本発明半導体装置の実施の形態１における樹脂封止工程の説明図Explanatory drawing of the resin sealing process in Embodiment 1 of the semiconductor device of the present invention 図１に示す半導体装置の発熱による変化の説明図Explanatory drawing of the change by the heat_generation | fever of the semiconductor device shown in FIG. 本発明半導体装置の実施の形態２における構成図Configuration diagram of a semiconductor device according to a second embodiment of the present invention 本発明半導体装置の実施の形態２における切り欠きを示す放熱板の平面図The top view of the heat sink which shows the notch in Embodiment 2 of the semiconductor device of this invention 従来の放熱板内蔵の半導体装置を示す構成図Configuration diagram showing a conventional semiconductor device with a built-in heat sink 図９に示す半導体装置の発熱による変化の説明図Explanatory drawing of the change by the heat_generation | fever of the semiconductor device shown in FIG.

符号の説明Explanation of symbols

１ 半導体装置
２ ワイヤー
３ リード
３ｉ インナーリード
３ｏ アウターリード
４ 半導体素子
５ａ 切り欠き
５ｂ 切り欠き
６ 吊りリード
７ ボンディングパッド
９ 矢印
１０ 封止樹脂体
１１ 放熱板
１５ リードフレーム DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Wire 3 Lead 3i Inner lead 3o Outer lead 4 Semiconductor element 5a Notch 5b Notch 6 Hanging lead 7 Bonding pad 9 Arrow 10 Sealing resin body 11 Heat sink 15 Lead frame

Claims (5)

少なくとも切り欠きを１箇所以上設けた放熱板と、複数本のインナーリードからなるリードフレームと、前記放熱板上に搭載された半導体素子及び前記半導体素子上に設けられたボンディングパッドと、前記インナーリードを電気的に接続するワイヤーを封止する樹脂を備えたことを特徴とする半導体装置。   A heat sink having at least one notch, a lead frame including a plurality of inner leads, a semiconductor element mounted on the heat sink, a bonding pad provided on the semiconductor element, and the inner lead A semiconductor device comprising a resin for sealing a wire for electrically connecting the two. 前記放熱板の４コーナーには吊りリードを挟むように各２本の切り欠きが設けられていることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein two cutouts are provided at four corners of the heat sink so as to sandwich a suspension lead. 前記放熱板の４コーナーには長さが吊りリードの１／３から１／２になるような各１本の切り欠きが設けられていることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein each of the four corners of the heat radiating plate is provided with one notch having a length which is 1/3 to 1/2 of the suspension lead. 放熱板を有する半導体装置の製造方法であって、インナーリードと放熱板を粘着テープで接着する工程と、前記放熱板の中央部の孔と吊りリードを挟むように切り欠きを各コーナーに金型で打ち抜く工程を含むことを特徴とする半導体装置の製造方法。   A method of manufacturing a semiconductor device having a heat sink, a step of bonding an inner lead and a heat sink with an adhesive tape, and a mold at each corner with a notch so as to sandwich a hole and a suspension lead in the center of the heat sink A method for manufacturing a semiconductor device, comprising: 切り欠きが施された放熱板を有する半導体装置の製造方法であって、切り欠きが施された放熱板中央部に半導体素子を搭載する工程と、前記半導体素子上のボンディングパッドとインナーリードを電気的に接続する工程と、少なくとも前記半導体素子及び前記電気的接合部を覆うと共に、前記リード電極の他端が導出するよう樹脂により封止する工程を含むことを特徴とする半導体装置の製造方法。   A method of manufacturing a semiconductor device having a notched heat sink, a step of mounting a semiconductor element in the center of a notched heat sink, and bonding pads and inner leads on the semiconductor element. A method of manufacturing a semiconductor device, comprising: a step of electrically connecting; and a step of covering at least the semiconductor element and the electrical junction and sealing with resin so that the other end of the lead electrode is led out.
JP2005114338A 2005-04-12 2005-04-12 Semiconductor device and its manufacturing method Pending JP2006294899A (en)

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