JP2006287257A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain the further physical size reduction of a standard cell and raise its degree of integration. <P>SOLUTION: This standard cell has a substrate region 22 formed beyond the border line with an adjoining cell 21. This substrate region 22 is formed sharing area with the substrate region 22 of one of the cells 21 among adjoining cells 21. In the substrate region 22, contacts 23 that supply predetermined electric potential to the substrate 22 are formed at an uneven interval. The contacts 23 are arranged and formed from the center of the width of the substrate region to the inside of the cell 21. The diffusion layer that forms the part of the substrate region 22, where the contacts 23 are arranged, extends and is formed and configured inside the cell. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device adopting a standard cell system.

  Conventionally, in a standard cell system that constitutes a semiconductor device, a plurality of types of cells having a uniform height are prepared, and each cell is arranged in a line to constitute a part of an integrated circuit. In order to realize high integration of an integrated circuit employing the standard cell system, it is desirable that the size of each cell is small. However, the technique of reducing the cell size by reducing the transistor size causes a trade-off problem with the cell driving capability. Therefore, as a method for reducing the apparent cell size without reducing the transistor size, for example, Japanese Patent Application No. 11-269484 discloses a method of sharing a part of a cell with an adjacent cell.

  FIG. 9 is a diagram showing a configuration of a semiconductor device adopting the above-described conventional technique. FIG. 9A is a plan view of a standard cell constituting a 2-input NAND, and FIG. 9B is a standard cell constituting an inverter. FIG. 2C is a plan view showing a configuration when the cell of FIG. 1A and the cell of FIG. In FIG. 9, for simplification, only the source region, polysilicon (poly-Si), contact, and cell boundary line (cell frame) are shown, and the metal wiring layer is omitted. Although not shown, the substrate region is shared between adjacent cells in the vertical direction, and the cells are arranged adjacent to each other in the vertical and horizontal directions so that the cell boundary lines are in contact with each other, forming cell rows in the vertical and horizontal directions. To do.

  As shown in FIG. 9A, the source regions 105, 106, 107 and a part of the contacts 101, 102, 103 in the region are arranged beyond the cell boundary 109. Source regions 105, 106, and 107 and contacts 101, 102, and 103 are disposed at the upper or lower portion of the cell. In addition, an overlapping region 108 where the source regions of adjacent cells are arranged and a space where the contact 104 can be arranged are provided. In the inverter cell of FIG. 5B, the source region 110 and a part of the contact 111 are disposed beyond the cell boundary line 114. As shown in FIG. 6C, when the NAND cell of FIG. 6A and the inverter cell of FIG. 5B are arranged adjacent to each other, the source region 106 and the contact 102 of FIG. The source region 110 and contact 111 in FIG. 5B are combined into one and shared between these cells. The shape of the source region 112 including the contact 113 shared between cells includes at least a concave shape.

  In such a configuration, since the source region and its contact are shared by adjacent cells, the cell row is reduced in the left-right direction, and the effective size of the cell can be reduced.

  FIG. 10 is a diagram showing a configuration of a semiconductor device employing the above-described conventional technique, and is a plan view of a standard cell constituting a 2-input NAND. In FIG. 10, for simplification, only the source region, polysilicon (poly-Si), contact, and cell boundary line (cell frame) are shown, and the metal wiring layer is omitted. Further, the cells are arranged adjacent to each other in the vertical and horizontal directions so that the cell boundary lines are in contact with each other, and form a cell row in the vertical and horizontal directions.

  As shown in FIG. 10, a part of the source regions 123, 124, and 125 are disposed beyond the cell boundary line 126, and substrate regions 127 and 128 for applying a predetermined potential to the well region are provided above and below the cell. 123, 124, 125 are formed adjacent to each other, and the adjacent source regions 123, 124 and the substrate region 127 are electrically connected to each other by a metal film (not shown) continuously formed on both regions. The contact 121 is provided on the cell boundary line 126, and the adjacent source region 125 and substrate region 128 are electrically connected by a metal film continuously formed on both regions, and the contact 122 serving as both regions is a cell. It is provided on the boundary line 126.

  In such a configuration, the vertically adjacent cells and the substrate regions 127 and 128 are shared, the horizontally adjacent cells and the source regions 123, 124, and 125 are shared, and the contacts on the source regions 123, 124, and 125 are connected. It is unnecessary. According to such a configuration, since the width of the source region that enters the adjacent cell beyond the cell boundary is narrower than the configuration shown in FIG. 9, the height of the cell can be kept low.

  FIG. 11 shows a configuration in which the degree of integration is improved by devising the arrangement of the substrate regions in a conventional semiconductor device adopting the standard cell system. In FIG. 11, this technique is such that when the substrate region 131 and the contact 132 connected thereto are provided above and below the cell to form a cell row, the substrate region 131 of each cell is connected together. Is shared with cells in a cell row adjacent in the vertical direction to improve the degree of integration. In an empty area where no cell is placed in the cell row, a dedicated cell placed in the empty area is placed, and a substrate area and a contact are also provided in that cell.

  Since this method uses a certain percentage of the substrate area regardless of the cell size, the size of the cell is small (same as narrow because the vertical size is the same). However, the larger the cell, the less effective the cell becomes. When the cell size becomes a certain size, the cell size may be smaller if the substrate area is placed in the cell alone. .

  As described above, in the conventional semiconductor device constructed by the standard cell system, the source region, the substrate region, and the contact formed in these regions are shared by the adjacent cells, so that the degree of integration can be increased. It has been improved. However, in order to achieve further progress in semiconductor technology, further reduction in the size of cells has been demanded.

  Accordingly, the present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device that achieves further reduction in standard cells and improves the degree of integration.

  In order to achieve the above object, a means for solving the problem is that in a semiconductor device in which an integrated circuit is constructed in which standard cells including a plurality of MOS transistors formed on a semiconductor substrate are vertically and horizontally arranged adjacently. The cell has a substrate region formed beyond a boundary line with the adjacent cell, and the substrate region is formed in common with the substrate region of any one of the adjacent cells. In the substrate region, contacts for supplying a predetermined potential to the substrate region are formed at non-uniform intervals, and the contact is disposed from the center of the width of the substrate region to the inside of the cell. The diffusion layer formed and forming the substrate region of the portion where the contact is disposed is disposed inside the cell. Characterized in that it is formed by expanded.

  As described above, according to the present invention, the substrate region and the source region are shared between adjacent cells, and a common contact is provided in both regions from the center of the substrate region to the inside of the cell. Thus, it becomes possible to reduce the cell with the same gate width as that of the prior art.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best embodiment for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention, and is a plan view of a standard cell constituting a 2-input NAND. In FIG. 1, only the source region, polysilicon, contact, substrate region, and cell boundary line (cell frame) are shown, and the metal wiring layer is omitted. The source regions 3, 4, and 5 are formed beyond the cell boundary line 9, and an overlapping region 6 is provided as an empty region in which a source region of a cell (not shown) adjacent to this cell can be placed. Yes. The substrate regions 7 and 8 are provided in the cell width direction (left and right direction in FIG. 1) above and below the cell and across the cell boundary line 9, and the source region and the diffusion region are formed in the same diffusion layer as the source region. Are formed by introducing different impurities. The substrate regions 7 and 8 are formed such that the minimum width portion is narrower than the minimum width in which the contact arrangement is allowed in the semiconductor manufacturing process. The integrated source regions 3, 4, 5 and the substrate regions 7, 8 are the cells in any one of the three surrounding cells in the four directions of the surrounding up, down, left, and right when the cells are arranged in a matrix. Shared.

  Contacts 1 and 2 are formed on the source regions 3, 4 and 5, the overlapping region 6 and the substrate regions 7 and 8, including the respective regions. The contact 1 functions as a contact that serves as a contact for both the source regions 3 and 4 and the substrate region 7, and the contact 2 is a contact for both the source region 5, the overlapping region 6, and the substrate region 8. Functions as a contact. The contacts 1 and 2 are arranged so as to be shifted from the center of the width at the position of the minimum width of the substrate regions 7 and 8 in the cell height direction (vertical direction in FIG. 1) toward the cell center, and the center of the contact is In addition, they are arranged and formed so as to overlap on the boundary line 9 with the adjacent cells in the cell width direction.

  Comparing such a configuration with the conventional configuration shown in FIG. 10 described above with reference to FIG. 2A showing the configuration of the above embodiment and FIG. 2B showing the conventional configuration, 2 (a) and 2 (b), the cell frame size is set to be the same, that is, the cell size is set to be the same, but the channel width of the transistor is the same as that of the above embodiment of FIG. 2 (a). It is getting bigger. In other words, if the channel widths of the transistors are aligned and compared, the structure of the above-described embodiment shown in FIG. 5A has a smaller cell size, and a highly integrated cell can be realized.

  FIG. 3 shows a cell row in which two cells shown in FIG. 1 are arranged in the cell width direction. In FIG. 3, the cells 11a and 11b in the cell row overlap each other at the borders 12a and 12b, and the source regions 3 and 4 of the cells 11a and 11b that cross the border over each other. Wrap. In addition, substrate regions 7 and 8 are continuously formed along the cell rows above and below each cell 11a and 11b.

  That is, by arranging the cells 11a and 11b adjacent to each other in rows, the regions (diffusion layers) having the functions of the source regions and the substrate regions of the cells 11a and 11b are connected along the cell rows. The substrate region is also shared with cells in adjacent cell rows.

  FIG. 4 shows a configuration in which the cell columns shown in FIG. 3 are arranged in two rows in the cell height direction. In FIG. 4, since the substrate region 13 is shared between the cell rows, the cells are flipped. The contacts 1 and 2 shown in FIG. 1 are arranged at positions shifted from the center of the substrate regions 7 and 8 at the position of the minimum width to the inside of the cell. This is because the cells are arranged as shown in FIG. In this case, the distance 14 between the contacts shown in FIG. 4 is shifted as necessary so that it does not fall below a value allowed in the manufacturing process. On the other hand, if this distance 14 is made larger than necessary, the cell size in the height direction of the cell will increase, so it is desirable to design it to the minimum necessary. If there are no other restrictions, this distance 14 is allowed. To be the smallest dimension. For example, the distance L between the center of the minimum width portion of the substrate region and the contact end is (C / 2) ≦ L ≦ C, where C is the distance between contacts on the diffusion layer allowed in the manufacturing process. The contacts are arranged and formed as follows.

  FIG. 5 is a diagram showing a configuration of a semiconductor device according to another embodiment of the present invention. In FIG. 5, substrate regions 22 are provided above and below each cell 21, and the cells 21 are arranged without gaps, so that the substrate region 22 on the upper side of the cell 21 can be connected to the left and right and upper cell subordinates of the cell 21. The substrate region 22 connected to the straight region and the cell region 22 below the cell 21 is connected to the substrate region of each of the left and right and lower cells of the cell 21 to form a substrate region 22 connected along the cell 21. The portion where the contact 23 is provided in the substrate region 22 is wider than the minimum width portion of the substrate region 22. That is, instead of providing a substrate region above and below each cell 21, a substrate region 22 is provided between the cell rows.

  The contact 23 on the substrate region 22 is offset from the center of the minimum portion of the width of the substrate region 22. The magnitude of the shift from the center of the minimum width portion of the substrate region 22 to the contact end is ½ or more of the distance between the contacts on the substrate region that is allowed by the design rule. FIG. 6 shows a configuration in which two rows of cell columns are arranged according to the configuration shown in FIG.

  By adopting the configuration shown in FIG. 5, the width of the substrate region can be made narrower than the conventional configuration shown in FIG. 11 (Wsub1 shown in FIG. 11 and Wsub2 shown in FIG. 5). When compared in the same manner, the height of the region usable as the MOS transistor is higher in the configuration of FIG. 5 (Wmos1 shown in FIG. 11 and Wmos2 shown in FIG. 5). On the other hand, in the portion where the contact is provided on the substrate region, the width of the substrate region is wider than that shown in FIG. 11, and the region usable as the MOS transistor is narrowed. In a small (narrow) cell, the area usable as a MOS transistor in the cell may be smaller than that shown in FIG. 11, but in many cells, the area usable as a MOS transistor increases. . In other words, by adopting this configuration, compared with the conventional example, the size of the MOS transistor can be increased if compared with the same cell area, so that the cell driving capability is improved, that is, the speed is increased, and the MOS transistor size is made the same. In comparison, high integration can be achieved by downsizing the cell.

  FIG. 7 is a diagram showing a configuration of a semiconductor device according to another embodiment of the present invention. In FIG. 7, in this embodiment, contacts 26 are arranged at uniform intervals on a substrate region 25 formed above and below the cell row of each cell 24, and the substrate region 25 and the PMOS active region or the NMOS active region are arranged. The substrate region 25 is widened only at a portion where there is a margin between the region.

  The effect of adopting the configuration shown in FIG. 7 is the same as the effect obtained by the configuration shown in FIG. In FIG. 5, it is assumed that the contact 23 on the substrate region 22 must be sufficiently inside the substrate region 22 according to the design rule, whereas in FIG. This is effective when the contact 26 on the substrate region 25 allows deviation from the substrate region 25 due to mask misalignment at the time.

  FIG. 8 shows a configuration in which two cell rows are arranged according to the configuration shown in FIG. In FIG. 8A, there is no misalignment and any contact is on the substrate region, but FIG. 8B shows a case where the contact opening is displaced upward. In FIG. 8B, a part of the contacts 26b and 26c may be displaced from the substrate region, and the contacts 26b and 26c may not be conducted. However, the contact 26a is originally formed on the substrate region in the upper row. The contact 26a can be normally conducted without falling off from the substrate region even when the width is shifted. Further, although not shown, when the contact opening is shifted downward, the contact 26b shown in FIG. 8B normally conducts without dropping from the substrate region 25.

  In the configuration shown in FIG. 5, since the sub-contact 23 has to be separated from the center of the substrate region 22 by a certain distance, in order to arrange the sub-contact 23, the substrate region 22 has to be greatly expanded. In the case of a design rule that allows dropout from the substrate region, by adopting the configuration shown in FIG. 7, the amount of expanding the substrate region is reduced to the minimum, and accordingly, the transistor size is increased and the cell size is increased. This can contribute to reduction.

It is a figure which shows the structure of the semiconductor device of the standard cell which concerns on one Embodiment of this invention. It is a figure which shows the mode of a comparison of the channel width of the structure of embodiment shown in FIG. 1, and the conventional structure. FIG. 2 is a diagram showing a configuration in which two standard cells shown in FIG. 1 are arranged adjacent to each other. FIG. 4 is a diagram showing a configuration in which standard cell rows shown in FIG. It is a figure which shows the structure of the semiconductor device of the standard cell which concerns on other embodiment of this invention. FIG. 6 is a diagram showing a configuration in which standard cell columns shown in FIG. It is a figure which shows the structure of the semiconductor device of the standard cell which concerns on other embodiment of this invention. FIG. 8 is a diagram showing a configuration in which the standard cell rows shown in FIG. It is a figure which shows the structure of the conventional standard cell. It is a figure which shows the structure of the other conventional standard cell. It is a figure which shows the structure of the other conventional standard cell.

Explanation of symbols

1, 2, 23, 26, 26a, 26b Contact 3, 4, 5 Source region 6 Overlapping region 7, 8, 13, 22, 25 Substrate region 9, 12a, 12b Cell boundary line 11a, 11b, 21, 24 cell 14 Contact spacing

Claims (4)

In a semiconductor device in which an integrated circuit is constructed by arranging standard cells including a plurality of MOS transistors formed on a semiconductor substrate adjacent to each other vertically and horizontally,
The standard cell has a substrate region formed beyond a boundary line with the adjacent cell,
The substrate region is formed in common with the substrate region of any one of the adjacent cells, and the substrate region has non-uniform contacts for supplying a predetermined potential to the substrate region. Formed at regular intervals,
The contact is disposed and formed from the center of the width of the substrate region to the inside of the cell, and the diffusion layer forming the substrate region of the portion where the contact is disposed is extended to the inside of the cell. A semiconductor device formed. 2. The semiconductor device according to claim 1, wherein the width of the substrate region is narrower than a width in which contact arrangement is allowed in a manufacturing process of the semiconductor device. The distance between the center of the width of the substrate region and the end of the contact on the side close to the center is not less than ½ of the distance between contacts on the diffusion layer allowed in the manufacturing process of the semiconductor device. The semiconductor device according to claim 1. 2. The semiconductor device according to claim 1, wherein the substrate region is formed in common with the substrate region of any three of the four cells above, below, left, and right of the adjacent cells.

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