JP6542444B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, a configuration in which a gate electrode including an n-type conductive impurity and a gate electrode including a p-type conductive impurity are formed continuously as an integral gate electrode. The present invention relates to a semiconductor device having the same and a method of manufacturing the same.

  There is a problem that variations in threshold voltage among a plurality of load transistors formed in a memory cell region in which a static random access memory (SRAM) memory cell is formed become large. If the threshold voltage among the load transistors in the memory cell area varies, the yield of the entire SRAM memory cell may be reduced. As a cause of the variation of the threshold voltage, a so-called CMOS (Complementary Metal Oxide Semiconductor) in which an n-type gate electrode and a p-type gate electrode formed of polycrystalline silicon in an SRAM memory cell are integrally and continuously formed. Interdiffusion of conductive impurities between the n-type gate electrode and the p-type gate electrode of the gate is considered.

  That is, if a large amount of p-type conductive impurities, for example, are introduced into the n-type gate electrode by interdiffusion, the threshold voltage of the MOS transistor including the n-type gate electrode changes due to that. Then, the characteristics of the MOS transistor are changed due to the change of the threshold voltage, which leads to a decrease in yield.

  Techniques for suppressing the mutual diffusion of conductive impurities in such a CMOS gate are disclosed, for example, in Japanese Patent Application Laid-Open Nos. 5-335503 (Patent Document 1) and 8-17934 (Patent Document 2). There is.

Unexamined-Japanese-Patent No. 5-335503 JP-A-8-17934

  However, as described in JP-A-5-335503, after the formation of the p-type gate electrode for forming the CMOS gate, the heat treatment is first performed before the formation of the n-type gate electrode, or JP-A-8-17934 As described above, the formation of the boundary between the n-type gate electrode and the p-type gate electrode at a distance from the field film may not sufficiently suppress the above-mentioned mutual diffusion. Therefore, it is required to apply a technique for suppressing the mutual diffusion more reliably than in JP-A-5-335503 and JP-A-8-17934.

  Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

A semiconductor device according to an embodiment includes a continuous gate electrode extending across an n-type and a p-type well region on a main surface of a semiconductor substrate. The continuous gate electrode includes both a first gate electrode containing a p-type conductive impurity as majority carriers and a second gate electrode containing an n-type conductive impurity as majority carriers and their buffer regions. . In the buffer region, the concentration of both the n-type conductive impurity and the p-type conductive impurity is 5 × 10 ¹⁹ cm ⁻³ or less, and the buffer region in the direction connecting the first gate electrode and the second gate electrode The width is 100 nm or more.

In the method of manufacturing a semiconductor device according to one embodiment, the end portion is disposed right above the boundary between the n-type and p-type well regions when the p-type conductive impurity is implanted into the conductive film. By forming the first implantation mask, the first gate electrode is formed. When the n-type conductive impurity is implanted into the conductive film, the second implantation mask is formed such that the end is disposed closer to the p-type well region than the boundary portion. A second gate electrode is formed in a region different from the one gate electrode. In a continuous gate electrode including a first gate electrode and a second gate electrode, a concentration of both an n-type conductive impurity and a p-type conductive impurity between the first gate electrode and the second gate electrode A buffer region having a width of 5 × 10 ¹⁹ cm ⁻³ or less and a width of 100 nm or more in the direction connecting the first gate electrode and the second gate electrode is formed.

  In a method of manufacturing a semiconductor device according to another embodiment, when a p-type conductive impurity is implanted into the conductive film, the main part is directed from the boundary between the n-type and p-type well regions to the n-type well region side. The p-type conductive impurity is implanted from an angle inclined to the direction perpendicular to the surface. When implanting an n-type conductive impurity into the conductive film, the n-type conductive impurity is implanted from an angle oblique to a direction perpendicular to the main surface so as to face the p-type well region side from the boundary portion. .

  According to one embodiment and another embodiment, a buffer region having a low concentration of both p-type and n-type conductive impurities is formed widely between the two conductive impurity regions. The effect of suppressing interdiffusion between the n-type conductive impurity and the n-type conductive impurity can be enhanced, and variations in threshold voltage resulting from the interdiffusion can be reduced.

FIG. 1 is a schematic plan view of a chip state of a semiconductor device according to an embodiment. FIG. 1 is an equivalent circuit diagram of a memory cell that constitutes a semiconductor device according to an embodiment. FIG. 3 is a schematic plan view for specifically describing the equivalent circuit of FIG. 2 in the first embodiment. It is a schematic sectional drawing of the part which follows the IV-IV line of FIG. It is a schematic sectional drawing of the part which follows the VV line | wire of FIG. It is a schematic sectional drawing of the part which follows the VI-VI line of FIG. FIG. 5 is an enlarged schematic cross-sectional view of a region VII surrounded by a dotted line in FIG. 4 and a graph showing a concentration distribution of conductive impurities in a continuous gate electrode in the region. FIG. 6 is an enlarged schematic cross-sectional view of a region VIII surrounded by a dotted line in FIG. 5 and a graph showing the concentration distribution of conductive impurities in the isolation insulating film in the region. FIG. 7 is an enlarged schematic cross-sectional view of a region IX surrounded by a dotted line in FIG. 6 and a graph showing the concentration distribution of conductive impurities in the isolation insulating film in the region. FIG. 15 is a schematic cross-sectional view showing a first step of a method of manufacturing the region shown in FIG. 4 of the semiconductor device in the first embodiment. FIG. 15 is a schematic cross-sectional view showing a second step of a method of manufacturing the region shown in FIG. 4 of the semiconductor device in the first embodiment. A schematic cross sectional view (A) showing a third step of a method of manufacturing the region shown in FIG. 4 of the semiconductor device in the first embodiment and a third method of manufacturing the region shown in FIG. 5 of the semiconductor device in the first embodiment FIG. 14 is a schematic cross sectional view (B) showing three steps and a schematic cross sectional view (C) showing a third step of the method for manufacturing the region shown in FIG. 6 of the semiconductor device in the first embodiment. A schematic cross sectional view (A) showing a fourth step of a method of manufacturing the region shown in FIG. 4 of the semiconductor device in the first embodiment and a fourth method of manufacturing the region shown in FIG. 5 of the semiconductor device in the first embodiment FIG. 14 is a schematic cross sectional view (B) showing four steps and a schematic cross sectional view (C) showing a fourth step of the method for manufacturing the region shown in FIG. 6 of the semiconductor device in the first embodiment. FIG. 15 is a schematic cross-sectional view showing a fifth step of the method of manufacturing the region shown in FIG. 4 of the semiconductor device in the first embodiment. FIG. 15 is a schematic cross-sectional view showing a sixth step of the method of manufacturing the region shown in FIG. 4 in the semiconductor device in the first embodiment. A schematic sectional view (A) showing the arrangement and shape of a p-type implantation mask which is a resist pattern formed in the process shown in FIG. 12 and an n-type implantation mask which is a resist pattern formed in the process shown in FIG. And a schematic cross-sectional view (B) showing the arrangement and shape of the It is a schematic sectional drawing which shows a structure of the area | region shown in FIG. 4 of the semiconductor device in a comparative example. FIG. 18 is an enlarged schematic cross-sectional view of a region XVIII surrounded by a dotted line in FIG. 17 and a graph showing concentration distribution of conductive impurities in a continuous gate electrode in the region. FIG. 18 is a schematic cross-sectional view showing a first step of a method of manufacturing the region shown in FIG. 17 of the semiconductor device in the comparative example. FIG. 21 is a schematic cross-sectional view showing the arrangement and the shape of an n-type implantation mask which is a resist pattern formed in the step shown in FIG. 19; It is the graph which compared the dispersion | variation in the absolute value of the threshold voltage of Embodiment 1 and a comparative example. Graph (A) showing variation in threshold voltage when the position of the boundary of the implantation region of p-type conductive impurity and n-type conductive impurity is shifted to the p-type well region side, p-type conductive impurity and n-type It is a graph (B) which shows the dispersion | variation in the threshold voltage when shifting the position of the boundary of the injection region of a conductive impurity to the n-type well region side. FIG. 13 is a schematic plan view for specifically describing a part of the equivalent circuit of FIG. 2 in the second embodiment. It is a schematic sectional drawing of the part which follows the XXIV-XXIV line of FIG. It is a schematic sectional drawing of the part which follows the XXV-XXV line | wire of FIG. FIG. 26 is an enlarged schematic cross-sectional view of a region XXVI surrounded by a dotted line in FIG. 25 and a graph showing the concentration distribution of conductive impurities in the isolation insulating film in the region. A schematic cross sectional view (A) showing a first step of a method of manufacturing the region shown in FIG. 24 of the semiconductor device in the second embodiment and a second method of manufacturing the region shown in FIG. 25 of the semiconductor device in the second embodiment. It is with the schematic sectional drawing (B) which shows 1 process. A schematic cross sectional view (A) showing a second step of a method of manufacturing the region shown in FIG. 24 of the semiconductor device in the second embodiment and a second method of manufacturing the region shown in FIG. 25 of the semiconductor device in the second embodiment. It is with the schematic sectional drawing (B) which shows 2 processes. A schematic sectional view (A) partially showing the arrangement and shape of a p-type implantation mask which is a resist pattern formed in the process shown in FIG. 27 and an n-type which is a resist pattern formed in the process shown in FIG. It is with schematic sectional drawing (B) which shows partially arrangement | positioning and shape of the mask for injection | pouring. 25 is an enlarged schematic cross-sectional view of the same region as region XXVI surrounded by a dotted line in FIG. 25 in the third embodiment and a graph showing concentration distribution of conductive impurities in the isolation insulating film in the region. FIG. A schematic cross sectional view (A) showing a first step of a method of manufacturing the region shown in FIG. 24 of the semiconductor device in the third embodiment, and a method of manufacturing the region shown in FIG. 25 of the semiconductor device in the third embodiment. It is with the schematic sectional drawing (B) which shows 1 process. FIG. 32 is a schematic cross-sectional view partially showing the arrangement and shape of an n-type implantation mask which is a resist pattern to be formed in the step shown in FIG. 31. It is the graph which compared the dispersion | variation in the absolute value of the threshold voltage of Embodiment 2 and Embodiment 3. FIG.

Hereinafter, an embodiment will be described based on the drawings.
Embodiment 1
Referring to FIG. 1, a semiconductor device DV according to an embodiment is a semiconductor chip in which a plurality of types of circuits are formed on a main surface of a semiconductor substrate SUB such as a semiconductor wafer made of silicon single crystal, for example. As an example, as a circuit that configures the semiconductor device DV, a memory cell array (memory cell region), a peripheral circuit region, and a pad region PD are included.

  The memory cell array is a main memory area of the semiconductor device DV including an SRAM. A peripheral circuit area and a pad area PD are formed outside the memory cell array in plan view. A plurality of pad regions PD are formed at intervals, for example, outside the memory cell array.

  Next, the configuration of the semiconductor device according to the present embodiment will be described with reference to the memory cell in FIG.

  Referring to FIG. 2, the semiconductor device in the present embodiment is an SRAM (static memory) having bit line pair BL and ZBL, word line WL, a flip flop circuit, and a pair of access transistors T5 and T6. Cells) in the memory cell area.

  The flip flop circuit has driver transistors T1 and T2 and load transistors T3 and T4. The driver transistor T1 and the load transistor T3 form one Complementary Metal Oxide Semiconductor (CMOS) inverter, and the driver transistor T2 and the load transistor T4 form the other CMOS inverter. The flip flop circuit consists of these two CMOS inverters. The SRAM is a semiconductor memory device that has a flip-flop circuit, thereby eliminating the need for processing called so-called refresh, in which the charge stored as information is returned to its original state in a predetermined cycle.

  Driver transistors T1 and T2 constituting the flip-flop circuit are, for example, n-channel type MOS transistors. Load transistors T3 and T4 are, for example, p-channel MOS transistors. Access transistors T5 and T6 are, for example, n-channel MOS transistors.

  In the flip flop circuit, gate electrodes of driver transistor T2 and load transistor T4 are electrically connected to source electrode S of access transistor T5. The source electrode S of the access transistor T5 is electrically connected to the drain electrode D of the driver transistor T1 and the load transistor T3, and the region where these are connected functions as a first storage node portion N1.

  In the flip flop circuit, gate electrodes of driver transistor T1 and load transistor T3 are electrically connected to source electrode S of access transistor T6. The source electrode S of the access transistor T6 is electrically connected to the driver transistor T2 and the drain electrode D of the load transistor T4, and the region to which these are connected functions as a second storage node N2.

  The source electrodes S of the driver transistors T1 and T2 are electrically connected to the GND potential, and the source electrodes S of the load transistors T3 and T4 are electrically connected to the Vcc wiring to which the voltage Vcc is applied. Each pair of bit line pairs BL and ZBL is connected to the drain electrode D of one pair of access transistors T5 and T6.

  Next, a more specific configuration of the semiconductor device shown in FIG. 2 will be described with reference to the schematic plan view of FIG. 3 and the schematic cross sectional views of FIGS.

  Referring to FIGS. 3 and 4, n-type well region NWR and p-type well region PWR are formed in semiconductor substrate SUB. The n-type well region NWR is formed on the main surface S1 of the n-type well formation region NW of the semiconductor substrate SUB, and the p-type well region PWR is formed on the main surface S1 of the p-type well formation region PW of the semiconductor substrate SUB. There is.

  In FIG. 3, the p-type well formation region PW and the n-type well formation region NW are alternately arranged in the horizontal direction of the figure. The p-type well region PWR and the n-type well region NWR which are adjacent to each other in the left-right direction in the drawing are arranged in contact with each other in the semiconductor substrate SUB. A portion where the p-type well region PWR and the n-type well region NWR are in contact with each other is formed as a boundary portion BDR between the p-type well region PWR and the n-type well region NWR. The p-type well region PWR and the n-type well region NWR have a rectangular planar shape extending in a strip shape in the vertical direction in FIG.

  Although omitted in FIG. 3, basically, a configuration in which the p-type well region PWR, the n-type well region NWR, and the p-type well region PWR are sequentially arranged from the left to the right shown in FIG. The one unit is arranged to be repeated in a matrix in the semiconductor substrate SUB.

  On the main surface S1 on which the n-type well forming region NW and the p-type well forming region PW of the semiconductor substrate SUB are aligned, continuous gate electrodes G1 and G2 extending in a strip shape in the lateral direction of the drawing are formed. The continuous gate electrode G1 is formed as, for example, a gate electrode extending long so that respective gate electrodes of a pair of driver transistor T1 and load transistor T3 forming a CMOS inverter in FIG. 2 are integrally continuous. .

  Specifically, the continuous gate electrode G1 extends in the left-right direction of FIG. 3 so as to straddle the p-type well region PWR on the left side of FIG. 3 and the n-type well region NWR in the center of FIG. The continuous gate electrode G1 includes a gate electrode PG (first gate electrode) formed on the n-type well region NWR side and a gate electrode NG (second gate electrode) formed on the p-type well region PWR side. It contains. The gate electrode PG is a gate electrode of the load transistor T3 formed in the n-type well region NWR as a p-channel MOS transistor, and contains a p-type conductive impurity (for example, boron) as a majority carrier. Similarly, the gate electrode NG is a gate electrode of the driver transistor T1 as an n-channel MOS transistor formed in the p-type well region PWR, and includes an n-type conductive impurity (for example, phosphorus) as a majority carrier.

  Similarly to the above, the continuous gate electrode G2 extends in the left-right direction of FIG. 3 so as to straddle the n-type well region NWR in the center of FIG. 3 and the p-type well region PWR on the right side of FIG. The continuous gate electrode G2 includes a gate electrode PG (first gate electrode) formed on the n-type well region NWR side and a gate electrode NG (second gate electrode) formed on the p-type well region PWR side. It contains. The gate electrode PG is a gate electrode of the load transistor T4 as a p-channel MOS transistor formed in the n-type well region NWR, and contains a p-type conductive impurity as a majority carrier. Similarly, the gate electrode NG is a gate electrode of the driver transistor T2 as an n-channel type MOS transistor formed in the p-type well region PWR, and contains an n-type conductive impurity as a majority carrier.

In the continuous gate electrodes G1 and G2, a buffer region BFR is formed between the gate electrode PG and the gate electrode NG. In buffer region BFR, the concentrations of both p-type conductive impurities as majority carriers of gate electrode PG and n-type conductive impurities as majority carriers of gate electrode NG are significantly higher than those of gate electrodes PG and NG. It is a low area. Specifically, in the buffer region BFR, the concentration of each of the n-type conductive impurity and the p-type conductive impurity is 5 × 10 ¹⁹ cm ⁻³ or less. Buffer region BFR has a width of 100 nm or more in the direction along main surface S1 of semiconductor substrate SUB (the horizontal direction in FIGS. 3 and 4: the direction connecting gate electrode NG and gate electrode PG).

  An access gate electrode GA is formed on the main surface S1 of the semiconductor substrate SUB at a distance from the continuous gate electrodes G1 and G2. The access gate electrode GA is formed as a gate electrode included in each of the access transistors T5 and T6 in FIG.

  Among them, the access gate electrode GA of the access transistor T5, which is an n-channel MOS transistor, alone (as another independent gate electrode which is not integrated with the gate electrode G2) extends the gate electrode G2 of FIG. It is an extension in the left-right direction, and is formed on the main surface S1 of the p-type well region PWR on the left side of FIG. Similarly, the access gate electrode GA of the access transistor T6, which is an n-channel MOS transistor, extends alone (as another independent gate electrode which is not integrated with the gate electrode G1). , And on the main surface S1 of the p-type well region PWR on the right side of FIG.

  All the gate electrodes G1, G2 and GA described above are formed on the main surface S1 of the semiconductor substrate SUB with the gate insulating film GI shown in FIG. 4 interposed therebetween.

  Referring mainly to FIG. 3, each of the transistors T1 to T6 has an active region AR. The active regions AR are arranged at intervals in the vertical direction of FIG. 3 so as to sandwich the continuous gate electrodes G1 of the transistors T1 and T3. In the active region AR, a pair of source / drain regions is formed across the continuous gate electrode G1. Similarly, the active regions AR are arranged at intervals in the vertical direction of FIG. 3 so as to sandwich the continuous gate electrodes G2 of the transistors T2 and T4, and one pair of the active regions AR sandwich the continuous gate electrodes G2 Source / drain regions are formed. Similarly, in each of the transistors T5 and T6, a pair of source / drain regions is formed in an active region AR formed in a pair so as to sandwich the access gate electrode GA.

  Contacts C1 and C2 connected to one active region AR (source electrode) of driver transistors T1 and T2 are electrically connected to the GND potential shown in FIG. Contacts C3 and C4 connected to one active region AR (drain electrode) of access transistors T5 and T6 are electrically connected to bit line pair BL and ZBL shown in FIG. Contacts C5 and C6 connected to one active region AR (source region) of load transistors T3 and T4 are contacts C7 and C8 connected to access gate electrode GA of access transistors T5 and T6 to a Vcc wiring applying voltage Vcc. The word lines WL are respectively connected. Furthermore, the first storage node units N1a and N1b in FIG. 3 correspond to the first storage node unit N1 in FIG. 2, and the second storage node units N2a and N2b in FIG. The second storage node unit N2 corresponds to the second storage node unit N2.

  Referring mainly to FIG. 4, a channel layer CHL is formed on main surface S1 of semiconductor substrate SUB so as to be sandwiched between a pair of active regions AR constituting each transistor. The channel layer CHL is formed in a region overlapping in plan view with a region sandwiched by a pair of active regions AR constituting each transistor among the gate electrodes G1, G2 and GA, in a region where the concentration of conductive impurities is in the periphery It is a relatively high area in comparison. The channel layer CHL is a region in which a channel is formed by the field effect of each transistor.

  In main surface S1 of semiconductor substrate SUB, isolation insulating film SI is formed in p type well region PWR and n type well region NWR in a region where channel layer CHL and active region AR are not formed. Isolation insulating film SI is made of, for example, a silicon oxide film, and electrically isolates a pair of adjacent transistors. For example, driver transistor T1 and load transistor T3 whose gate electrodes are integrated by continuous gate electrode G1 are electrically isolated from each other by isolation insulating film SI disposed between them.

  On the side walls of the gate electrodes G1, G2, GA and the gate insulating film GI, for example, an offset spacer OF made of a silicon oxide film and a sidewall insulating film SW made of a silicon nitride film, for example, are stacked in this order.

  4 to 6, interlayer insulating film II1 is formed on main surface S1 so as to cover gate electrodes G1, G2, GA, active region AR and isolation insulating film SI. A patterned first metal wiring M1 is formed in a partial region on the interlayer insulating film II1. The first-layer metal interconnection M1 is a storage node portion (for example, second storage node portion N2b in FIG. 4) and a contact (for example, contact C8 in FIG. 4) formed to fill the contact holes in interlayer insulating film II1. Are electrically connected to, for example, the gate electrodes G1, G2 and GA and the active region AR of FIG. A barrier metal BRL may be formed on the bottom wall of the contact hole of the interlayer insulating film II1.

  An interlayer insulating film II2 is formed on the interlayer insulating film II1 so as to cover the metal wiring M1. Patterned metal interconnection M2 is formed on interlayer insulating film II2. Although not shown in FIG. 4, metal interconnection M2 and metal interconnection M1 are electrically connected.

  An interlayer insulating film II3 is formed on the interlayer insulating film II2 so as to cover the metal wiring M2. Patterned metal interconnection M3 is formed on interlayer insulating film II3. In FIG. 4, the metal wiring M3 extends in a direction intersecting with the extending direction of the metal wirings M1 and M2 in plan view. Although not shown in FIG. 4, the metal wiring M3 and the metal wiring M2 are electrically connected.

  An interlayer insulating film II4 is formed on the interlayer insulating film II3 so as to cover the metal wiring M3. Patterned metal interconnection M4 is formed on interlayer insulating film II4. Although not shown in FIG. 4, the metal wiring M4 and the metal wiring M3 are electrically connected. An insulating film II5 is formed on the interlayer insulating film II4 so as to cover the metal wiring M4.

  In FIGS. 5 to 6, the illustration is omitted in the upper layer above the interlayer insulating film II2.

  Next, concentration distribution of various conductive impurities in each of the regions constituting the continuous gate electrode G1 will be described with reference to FIG.

  Referring to FIG. 7, the horizontal axis of the lower graph corresponds to a region VII surrounded by a dotted line in FIG. 4, that is, a region including buffer region BFR and a part of gate electrodes NG and PG. The position coordinate x is shown. The position coordinate x in the graph of FIG. 7 corresponds to the position in the enlarged schematic cross-sectional view right above (in the direction extended in the vertical direction). The vertical axis of the graph indicates the concentration of p-type and n-type conductive impurities at each position indicated by the horizontal axis.

The concentration of the n-type conductive impurity indicated by n ⁺ in the graph is substantially constant in the n-type gate electrode NG, but decreases as going from the buffer region BFR toward the p-type gate electrode PG. Similarly, the concentration of the p-type conductive impurity indicated by p ⁺ in the graph is substantially constant in the p-type gate electrode PG, but decreases from the buffer region BFR toward the n-type gate electrode NG.

From FIG. 7, for example, a region having p-type conductive impurities as majority carriers and having a concentration of p-type conductive impurities exceeding 5 × 10 ¹⁹ cm ^-3 is gate electrode PG, and n-type conductive impurities as majority carriers. A region where the concentration of the n-type conductive impurity exceeds 5 × 10 ¹⁹ cm ⁻³ can be considered as a gate electrode NG. At this time, the distance between the pair of gate electrodes PG and the gate electrode NG in each of the continuous gate electrodes G1 and G2 constituting each of the transistors T1 to T4 of the CMOS inverter is 100 nm or more.

The region sandwiched between the pair of gate electrodes PG and the gate electrode NG is a buffer region BFR in which the concentrations of the n-type conductive impurity and the p-type conductive impurity are both 5 × 10 ¹⁹ cm ⁻³ or less. ing. The sum of the concentrations of the n-type conductive impurity and the p-type conductive impurity in the buffer region BFR is the n-type conductive impurity and the p-type conductivity in the gate electrode PG and the gate electrode NG extending integrally therewith. It is relatively smaller than the sum of the concentration with the impurity. Among the buffer regions BFR, the region with the lowest concentration (where the sum of the concentrations of the n-type conductive impurity and the p-type conductive impurity is minimized) is a region substantially overlapping the boundary portion BDR in plan view .

  The buffer region BFR is preferably formed to overlap at least a part of the boundary BDR in plan view. Particularly in FIG. 7, the position where the two graphs intersect so that the concentration of the n-type conductive impurity and the concentration of the p-type conductive impurity in the buffer region BFR are substantially equal to each other almost overlaps the boundary portion BDR (continuous It is formed substantially at the center in the width direction of the isolation insulating film SI just below the gate electrode G1. It is particularly preferable that such an embodiment be adopted.

  Next, concentration distribution of various conductive impurities in a region away from the continuous gate electrode G1 will be described with reference to FIGS. 8 and 9. FIG.

  Referring to FIG. 8, an insulating film region in semiconductor substrate SUB adjacent to continuous gate electrode G1 overlapping a part of boundary portion BDR will be considered. In this insulating film region, isolation insulating film SI is formed slightly below the region where continuous gate electrode G1 and boundary portion BDR overlap in FIG. 3, for example (neither active region AR nor gate electrode is formed) ) Means area. The vertical and horizontal axes of the graph are the same as the graph of FIG.

  In isolation insulating film SI as the insulating film region, basically, the amount of n-type conductive impurities is large on the left side of boundary portion BDR, that is, in a region planarly overlapping with p-type well region PWR, and more than boundary portion BDR. In the right side, that is, the area planarly overlapping with the n-type well area NWR, the amount of p-type conductive impurities is large. However, position coordinates in the x direction in FIG. 8 of the boundary BR between the region containing the n-type conductive impurity as the majority carrier and the region containing the p-type conductive impurity as the majority carrier (in other words, n-type conductive impurity and p-type conductivity A boundary BR), which is a position at which the concentration with the sexual impurity is equal, is located slightly to the left of the boundary BDR, that is, at a position biased toward the p-type well region PWR.

The sum of the concentrations of n-type and p-type conductive impurities in isolation insulating film SI in FIG. 8 is the concentration of n-type and p-type conductive impurities in buffer region BFR in FIG. 7. It is relatively larger than the sum. This can be understood from the fact that the concentration of both the n-type conductive impurity and the p-type conductive impurity is 5 × 10 ¹⁹ cm ⁻³ or more in most of the region shown by the graph in FIG.

  Further, the sum of the concentrations of n-type conductive impurity and p-type conductive impurity in isolation insulating film SI of FIG. 8 is a gate electrode extending so as to be integrated with buffer region BFR adjacent to that shown in FIG. It is relatively larger than the sum of the concentrations of the n-type conductive impurity and the p-type conductive impurity in PG and the gate electrode NG. This is because diffusion of conductive impurities is less likely to occur in the isolation insulating film SI than in the continuous gate electrode G1, and the implanted conductive impurities remain as they are.

  Referring to FIG. 9, an insulating film region in semiconductor substrate SUB overlapping a part of boundary portion BDR and adjacent to access gate electrode GA will be considered. In this insulating film region, isolation insulating film SI is formed, for example, slightly below access gate electrode GA in FIG. 3 and overlapping a part of boundary portion BDR (both active region AR and gate electrode It means the area which is not formed. The vertical and horizontal axes of the graph are the same as the graphs of FIGS. 7 and 8.

  Even in isolation insulating film SI as the insulating film region, basically, the amount of n-type conductive impurities is large in a region overlapping with planar portion BDR on the left side of boundary portion BDR, that is, more than boundary portion BDR. In the right side, that is, the area planarly overlapping with the n-type well area NWR, the amount of p-type conductive impurities is large. However, position coordinates in the x direction in FIG. 8 of the boundary BR between the region containing the n-type conductive impurity as the majority carrier and the region containing the p-type conductive impurity as the majority carrier (in other words, n-type conductive impurity and p-type conductivity A boundary BR), which is a position where the concentration with the sexual impurity is equal, is present at a position approximately overlapping the boundary BDR.

  That is, the boundary BR between the region including n-type conductive impurities as majority carriers and the region including p-type conductive impurities as majority carriers in the insulating film region adjacent to continuous gate electrode G1 in FIG. 8 is the access gate in FIG. The insulating film region adjacent to the electrode GA is formed closer to the p-type well region PWR than a boundary BR between a region containing n-type conductive impurities as majority carriers and a region containing p-type conductive impurities as majority carriers.

  Next, with reference to FIGS. 10 to 17, the manufacturing method in the present embodiment will be described focusing on the region where driver transistor T1, load transistor T3 and access transistor T6 shown in FIG. 4 are formed.

  Referring to FIG. 10, first, semiconductor substrate SUB made of, for example, silicon is prepared. The semiconductor substrate SUB is divided into a p-type well formation region PW and an n-type well formation region NW in plan view. By implanting a desired conductive impurity in a desired region by a normal photolithographic technique and an ion implantation technique, p-type in each of p-type well formation region PW and n-type well formation region NW Well region PWR and n-type well region NWR are formed. The p-type well region PWR and the n-type well region NWR are adjacent to each other so as to form a boundary portion BDR by being in contact with each other as shown in FIG. The p-type well region PWR and the n-type well region NWR are arranged in the order of the p-type well region PWR, the n-type well region NWR, and the p-type well region PWR from left to right in plan view as shown in FIG. As one unit, the one unit is formed to be repeated in a matrix in the semiconductor substrate SUB.

  Further, on main surface S1, an isolation insulating film SI is formed to electrically insulate a pair of transistors adjacent to each other among the finally formed plurality of transistors. Isolation insulating film SI is a silicon oxide film formed by, for example, a generally known LOCOS (Local Oxidation of Silicon) method or STI (Shallow Trench Isolation) method. When the isolation insulating film SI is formed by the STI method, the isolation insulating film SI is planarized by CMP (Chemical Mechanical Polishing).

  Referring to FIG. 11, it is a part of a region sandwiched by a pair of adjacent isolation insulating films SI in FIG. 10, in particular, a region directly below gate electrodes of a plurality of transistors finally formed. , Supply of conductive impurities by additional ion implantation techniques. Thereby, the channel layer CHL is formed on the main surface S1 of the region.

  An insulating film GI to be a gate insulating film is formed on the planarized surface of the semiconductor substrate SUB, and a conductive film PS to be gate electrodes G1 and GA is formed on the insulating film GI. Insulating film GI is formed, for example, by a thermal oxidation method. The conductive film PS is a thin film of amorphous silicon which does not contain conductive impurities and is formed, for example, by a CVD (Chemical Vapor Deposition) method. Insulating film GI and conductive film PS are formed to extend so as to straddle p-type well region PWR and n-type well region NWR in the region shown in FIG. 11 (FIG. 4).

  Referring to FIGS. 12A, 12B, and 12C, a pattern of photoresist PHR as a photosensitive member having an opening just above n-type well region NWR by ordinary photolithography and ion implantation techniques. Is used to implant a p-type conductive impurity (for example, boron) into the conductive film PS directly above the n-type well region NWR.

  Referring to FIGS. 12 (A), (B), (C) and FIG. 16 (A), a pattern of photoresist PHR used here is a mask PMK for p-type implantation (first implantation mask). The planar shape basically overlaps the n-type well region NWR, and the end EG thereof is disposed directly above the boundary BDR between the n-type well region NWR and the p-type well region PWR. Therefore, when using a positive photoresist PHR in which a pattern is formed by removing a portion exposed to light and exposed to light, the p-type implantation mask PMK is formed with an n-type well region NWR in which an opening is to be formed. By the exposure of the overlapping region, as shown in FIG. 16A, a rectangular pattern is formed in the region overlapping with the p-type well region PWR. In the case of using a negative photoresist PHR, conversely, the p-type implantation mask PMK is exposed as a region overlapping the p-type well region PWR where a pattern is to be formed, as shown in FIG. A rectangular pattern is formed in a region overlapping with the p-type well region PWR.

  12A shows a portion along the line XIIA-XIIA in FIG. 16A, and FIG. 12B shows a portion along the line XIIB-XIIB in FIG. ) Show portions along line XIIC-XIIC in FIG. The distance a between the end EG (boundary BDR) and the active region AR extending to the left and right sides thereof is preferably 100 nm, for example.

  Referring to FIGS. 13A, 13B and 13C, a pattern of photoresist PHR as a photosensitive member having an opening just above p-type well region PWR by the usual photolithographic technique and ion implantation technique. Is used to implant an n-type conductive impurity (for example, phosphorus) into the conductive film PS directly above the p-type well region PWR.

  Referring to FIGS. 13 (A), (B), (C) and FIG. 16 (B), a pattern of photoresist PHR used here is an n-type implantation mask NMK (second implantation mask). The planar shape basically has an opening in a region overlapping with the p-type well region PWR. Also in the formation of this, either of the above-mentioned positive photoresist PHR and negative photoresist PHR may be used. However, even in the case where either positive or negative photoresist PHR is used, the end EG of the opening is partially arranged on the p-type well region PWR side (the left side of the figure) with respect to the boundary BDR. . 13A shows a portion along line XIIIA-XIIIA in FIG. 16B, and FIG. 13B shows a portion along line XIIIB-XIIIB in FIG. ) Shows a portion along line XIIIC-XIIIC in FIG. 16 (B), respectively.

  Specifically, in the upper half region of FIG. 16B, ie, in the regions shown in FIGS. 13A and 13B, the p-type well region on the left side of the figure is the continuous gate electrode G1 and the region in the vicinity thereof. An end EG is formed to be closer to the p-type well region PWR side on the left side of the drawing than the boundary BDR between the PWR and the n-type well region NWR. On the other hand, in the access gate electrode GA and the region in the vicinity thereof (similar to the p-type implantation mask PMK), it overlaps the boundary BDR between the n-type well region NWR and the p-type well region PWR on the right side of the figure. The end portion EG of the n-type implantation mask NMK is formed on From the above, the n-type implantation mask NMK has its end EG protruding toward the p-type well region PWR side than the other regions (the regions adjacent to the access gate electrode GA) in the continuous gate electrode G1 and the region thereabout And the protrusion TKI.

  Similarly, in the lower half region of FIG. 16B, ie, the region shown in FIG. 13C, in the region of the access gate electrode GA and the vicinity thereof (similar to the p-type implantation mask PMK) An end portion EG of the n-type implantation mask NMK is formed so as to overlap the boundary portion BDR between the p-type well region PWR on the left side and the n-type well region NWR. On the other hand, in the continuous gate electrode G2 and its neighboring region, it is closer to the p-type well region PWR on the right side of the figure than the boundary BDR between the n-type well region NWR and the p-type well region PWR on the right side of the figure. The end EG is formed on the Therefore, also in this region, n-type implantation mask NMK has its end closer to p-type well region PWR than the other regions (access gate electrode GA and the region in the vicinity thereof) in the continuous gate electrode G2 and the region in the vicinity thereof. It has a projection TKI in which the part EG protrudes.

  The protrusion TKI protrudes by the distance b more than the non-protrusion where the end EG does not protrude. It is conceivable that the distance b is shorter than the distance a in FIG. 16A, for example, 50 nm.

  As described above, particularly in the region where the continuous gate electrodes G1 and G2 are to be formed and in the vicinity thereof, the end portion EG is arranged closer to the p-type well region PWR side than the region in which the access gate electrode GA is to be formed and the vicinity thereof. An n-type implantation mask NMK having a planar shape (protrusion TKI) that protrudes as described above is formed, and n-type conductive impurities are implanted.

  By the above processing, particularly in the continuous gate electrodes G1 and G2, the n-type conductive impurities are spaced apart from the n-type well region NWR into which the p-type conductive impurities are implanted by the p-type well region PWR side. Injected into the

  Referring to FIG. 14, the insulating film GI and the conductive film PS are patterned by ordinary photolithography and etching to laminate the gate insulating film GI and the continuous gate electrode G1 including the gate electrodes NG and PG. A structure is formed. In addition, a stacked structure of the gate insulating film GI and the access gate electrode GA including the n-type conductive impurity is formed.

  Referring to FIG. 15, an n-type region which becomes an LDD (Lightly Doped Drain) on the surface of semiconductor substrate SUB in p-type well region PWR and n-type well region NWR using conventional photoengraving technology and ion implantation technology. And p-type regions are formed. This finally constitutes the source / drain regions of the active region AR of each transistor as shown in FIG. 3 although not shown in FIG.

  The entire semiconductor substrate SUB is heat-treated by RTA (Rapid Thermal Anneal), whereby the p-type conductive impurity and the n-type conductive impurity implanted into the conductive film PS are activated. As a result, the amorphous silicon constituting the conductive film PS is polycrystallized to form a continuous gate electrode G1 of polycrystalline silicon.

  Next, a silicon oxide film and a silicon nitride film, for example, are sequentially stacked and deposited on the entire surface of semiconductor substrate SUB. Thereafter, a laminated structure of offset spacers OF of a silicon oxide film and a sidewall insulating film SW of a silicon nitride film NF is formed on the sidewalls of the continuous gate electrode G1 and the access gate electrode GA by ordinary photolithography and anisotropic etching. It is formed.

The n-type conductive impurities in the polycrystalline silicon constituting the continuous gate electrode G1 and the like are directed toward the gate electrode PG and the p-type conductive impurities by the heating by RTA and the heating at the time of laminating the silicon oxide film etc. Thermal diffusion (interdiffusion) is performed toward the gate electrode NG. As a result, the concentration distribution of the conductive impurities as shown by the graph in FIG. 7 is obtained immediately above and in the vicinity of the boundary BDR, and the concentrations of the n-type conductive impurities and the p-type conductive impurities are as described above. A buffer region BFR is formed which has a width of 5 × 10 ¹⁹ cm ⁻³ or less and a width of 100 nm or more in the direction connecting the gate electrode NG and the gate electrode PG. Among the buffer region BFR, the position of the boundary BR where the concentrations of the p-type conductive impurity and the n-type conductive impurity are approximately equal is the position where the boundary portion BDR substantially overlaps (see FIG. 7).

  Thereafter, interlayer insulating films II1 to II5 and metal interconnections M1 to M4 are formed by a generally known method, and the configuration shown in FIG. 4 is formed, but the detailed description will be omitted.

Next, the operation and effect of the present embodiment will be described with reference to the comparative examples shown in FIGS.
With reference to FIGS. 17 and 18, the comparative example also has basically the same configuration as the schematic cross sectional views of the present embodiment shown in FIGS. 4 and 7, but in the configuration of continuous gate electrode G1. There are some differences. Specifically, the boundary BR between the gate electrode NG in which the n-type conductive impurity is a majority carrier and the gate electrode PG in which the p-type conductive impurity is a majority carrier is closer to the n-type well region NWR than the boundary BDR ( It is biased to the right of the figure). In addition, the width in the direction connecting gate electrode NG and gate electrode PG of buffer region BFR having a relatively low concentration for both n-type conductive impurity and p-type conductive impurity is very narrow compared to the present embodiment. There is.

  Referring to FIGS. 19 and 20, in the comparative example, in the step of implanting n-type conductive impurities in the region forming continuous gate electrode G1 shown in FIG. 13A, the end of n-type implantation mask NMK Portion EG is formed to be disposed directly above boundary portion BDR. This is a step of forming a p-type conductive impurity in the region forming continuous gate electrode G1 in FIG. 12 and in the vicinity thereof, and an n-type conductive impurity in the region forming access gate electrode GA in FIG. Is the same as the step of Therefore, in the comparative example, as shown in FIG. 20, the protrusion TKI (see FIG. 16B) is not formed on the n-type implantation mask NMK. Here, FIG. 19 shows a portion along line XIX-XIX in FIG.

  Also in the comparative example, the step of implanting the p-type conductive impurity is the same as that of the present embodiment shown in FIG. 12, and the end EG of the opening is formed right above the boundary BDR. The p-type implantation mask PMK is used. In addition, the manufacturing method of the comparative example is basically carried out with respect to steps (steps of FIGS. 10 to 12 and 14 to 15 of the first embodiment) other than the steps corresponding to FIG. 13 of the first embodiment. It is similar to the manufacturing method of form 1.

  That is, in the comparative example, in all the regions in the vertical direction of FIG. 20 including the region where continuous gate electrode G1 is to be formed and the vicinity thereof, the boundary of the region where the p-type conductive impurity is implanted and the n-type conductivity The position is almost the same as the boundary of the region into which the impurity is implanted (on the boundary BDR).

  It is to be noted that the configuration of the comparative example other than this is substantially the same as the configuration of the present embodiment, and therefore, the same elements will be denoted by the same reference numerals and the description thereof will not be repeated.

  In the comparative example, in the conductive film PS in which the continuous gate electrode G1 is to be formed, n-type and p-type regions are formed between the region into which the n-type conductive impurity is implanted and the region into which the p-type conductive impurity is implanted. A void is not formed where neither of the conductive impurities are implanted. Therefore, in the conductive film PS in which the continuous gate electrode G1 is to be formed, a region into which the n-type conductive impurity is implanted and a region into which the p-type conductive impurity is implanted are formed in contact with each other.

  In this case, the p-type conductive impurity diffuses in the conductive film PS and easily moves into the region into which the n-type conductive impurity is implanted. Similarly, the n-type conductive impurity diffuses in the conductive film PS and easily moves into the region into which the p-type conductive impurity is implanted. Thus, the n-type and p-type conductive impurities are easily diffused in the conductive film PS. Since the n-type conductive impurity is more easily diffused than the p-type conductive impurity, the range of the gate electrode NG in which the n-type conductive impurity is the majority carrier penetrates further to the gate electrode PG side, and the position of the boundary BR Is shifted to the right of the figure.

  Further, in the comparative example, no region is implanted in the vicinity of the boundary between the region into which the p-type conductive impurity is implanted and the region into which the n-type conductive impurity is implanted. A relatively high concentration of conductive impurities will be present, and the range of the buffer region BFR will be narrower than in the present embodiment.

  Since the range between the gate electrode PG and the gate electrode NG changes when the position of the boundary BR shifts to the n-type well region NWR in this way, the threshold voltage of the MOS transistor including the gate electrodes PG and NG is set to the design value. It will be changed. That is, due to the above-mentioned mutual diffusion, the threshold voltage of the CMOS inverter may vary, which may cause a defect in its performance and the like.

  Therefore, from the viewpoint of suppressing such a situation, in the present embodiment, the projection TKI is provided in the vicinity of the conductive film PS on which the continuous gate electrode G1 is to be formed among the p-type implantation mask PMK. The edge EG, which is the boundary of the implantation region, is previously designed to be shifted away from the boundary of the implantation region of the n-type conductive impurity. As described above, the implantation region of the n-type conductivity impurity is a region of the implantation region of the p-type conductivity impurity in advance by the distance b (see FIG. 13) where migration due to diffusion of the conductivity impurity is expected in the conductive film PS. By separating from the end EG, a region into which neither the n-type conductive impurity nor the p-type conductive impurity is implanted is formed in the conductive film PS for the continuous gate electrode G1. In the vicinity of the region into which neither the n-type conductive impurity nor the p-type conductive impurity is implanted, the buffer region BFR having a relatively low impurity concentration finally becomes the gate electrode NG of the continuous gate electrode G1 and the gate electrode PG. And so as to have a somewhat wide width in the direction connecting the

  In this case, for example, in order for the conductive impurity to move from the gate electrode NG to the gate electrode PG, it has to pass through the (wide) buffer region BFR between them, the gate electrode PG to the gate electrode PG The number of conductive impurities that can be reached is reduced. Therefore, the probability of occurrence of mutual diffusion can be reduced, and variations in threshold voltage of the MOS transistor including the continuous gate electrode G1 can be reduced.

The effect of suppressing the above-mentioned mutual diffusion is particularly related to the direction of connecting the gate electrode NG and the gate electrode PG when the concentration of n-type and p-type conductive impurities in the buffer region BFR is 5 × 10 ¹⁹ cm ⁻³ or less. It becomes large when the width is 100 nm or more. As the buffer region BFR is wider and the concentration of the conductive impurities is lower, the effect of the buffer region BFR to suppress the interdiffusion and the variation in threshold voltage is greater. Therefore, the sum of the concentrations of n-type and p-type conductive impurities in the buffer region is relative to the sum of the concentrations of n-type and p-type conductive impurities in gate electrode NG and gate electrode PG. By reducing the size, the buffer region BFR has a greater effect of suppressing the interdiffusion and the variation in threshold voltage.

  In the present embodiment, although the n-type conductive impurity is implanted toward the p-type well region PWR side, finally, the buffer region BFR after heat treatment has its center near the top of the boundary portion BDR. The reason is that the n-type conductive impurity is more easily diffused than the p-type conductive impurity. Considering that the n-type conductive impurity moves more than the p-type conductive impurity, the implantation position before diffusion is on the n-type conductive impurity side (p-type well region PWR side) as in the present embodiment. It is preferable to shift in advance. If buffer region BFR is formed at a position overlapping at least a part of boundary portion BDR in plan view, both gate electrode PG and gate electrode NG are misaligned in n-type well region NWR and p-type well region PWR, respectively. This is an aspect that fits without, so that variations in threshold voltage among a plurality of transistors including the gate electrodes PG and NG can be eliminated.

  As described above, in the continuous gate electrode G1, using the protrusion TKI, the n-type conductive impurity is separated from the n-type well region NWR into which the p-type conductive impurity is implanted by the distance b closer to the p-type well region PWR. Although provided, in the region where the access transistors T5 and T6 are disposed, the protrusion TKI is not formed and the above-described interval b is not provided.

  The access gate electrodes GA of the access transistors T5 and T6 are not arranged to be continuous with the gate electrodes of the other transistors, and are formed independently. Therefore, it is not necessary to consider interdiffusion with the other gate electrodes described above, and it is not necessary to form buffer region BFR.

  If the projection TKI is provided on the n-type implantation mask NMK in the entire area including the area where the buffer area BFR does not need to be formed, the n-type implantation mask NMK is generated for the entire interval b. The size in the whole planar view becomes large. As a result, the area of the entire memory cell area is increased, and the size of the semiconductor device may be increased.

  Therefore, in the present embodiment, the above-described protrusion TKI on the p-type well region PWR side is performed only in the continuous gate electrode G1 (constituting the flip-flop circuit of the SRAM) requiring formation of the buffer region BFR and the vicinity thereof. An n-type conductive impurity is implanted to form the space b. Then, in the access gate electrode GA and in the vicinity thereof, the implantation region of the p-type conductive impurity and the implantation region of the n-type conductive impurity are substantially in contact in the vicinity of the boundary BDR. In this manner, the area of the entire memory cell area can be reduced as compared to the case where the space b is provided on the whole.

  Incidentally, as shown in FIG. 16B, if the protrusion TKI is formed to have a point-symmetrical shape with respect to the center of the n-type implantation mask NMK, a memory cell area including the formation position of the buffer area BFR. The overall layout efficiency can be further enhanced.

  In the conductive film PS of polycrystalline silicon such as the continuous gate electrode G1, diffusion of conductive impurities is likely to occur due to heat treatment, but almost no diffusion occurs in the isolation insulating film SI. That is, for example, the concentration distribution of the p-type conductive impurity and the n-type conductive impurity in isolation insulating film SI shown in FIGS. 8 and 9 is a p-type conductive impurity compared to the concentration distribution in conductive film PS. And n-type conductive impurities reflect relatively well the distribution of the injected density. Therefore, the boundary between the region including n-type conductive impurities as majority carriers and the region including p-type conductive impurities as majority carriers in isolation insulating film SI adjacent to continuous gate electrode G1 is adjacent to access gate electrode GA. It is formed closer to the p-type well region PWR than the boundary between the region containing the n-type conductive impurity as majority carrier and the region containing the p-type conductive impurity as majority carrier in the matching isolation insulating film SI.

  Next, about the change of the threshold voltage when forming gate electrodes NG and PG on continuous gate electrode G1 using mask PMK for p type implantation and mask NMK for n type implantation shown in FIGS. 16 (A) and 16 (B) explain.

  Referring to FIG. 21, the horizontal axis of this graph indicates the absolute value of the threshold voltage of gate electrodes NG and PG formed on continuous gate electrode G1 described above, and the vertical axis of the graph indicates FIG. The position in the left-right direction of the n-type implantation mask NMK shown in (4) unintentionally indicates the amount of deviation with respect to the position in the left-right direction of the p-type implantation mask PMK.

  For example, in FIG. 16B, focusing on the vicinity of the boundary BDR between the p-type well region PWR on the left side of the figure and the n-type well region NWR in the center, for p-type injection in the lower half of the figure. The end EG of the mask PMK and the mask for n-type implantation NM almost overlap (this end EG also overlaps with the boundary BDR). Assuming now that both the p-type implantation mask PMK and the n-type implantation mask NMK are formed without being deviated from the desired position in the left and right direction, the lower half of FIG. It is assumed that a projection TKI having a length b in the left-right direction with respect to the side half area is provided. In this case, since no displacement occurs in the formation position of the mask, the n-type conductive impurity is implanted at a distance b to the p-type well region PWR side with respect to the p-type conductive impurity. The value of b is 50 nm in the graph of FIG.

  However, if the mask NMK for n-type implantation is shifted 25 nm to the left in the figure with respect to the mask PMK for p-type implantation (in the correct position) unintentionally, the value of b is further increased to 75 nm. That is, the distance (in the lateral direction of FIG. 16B) between the implantation region of p-type conductive impurity for gate electrode PG and the implantation region of n-type conductive impurity for gate electrode NG in continuous gate electrode G1 by this amount Becomes larger. Conversely, in this case, focusing on the vicinity of the boundary BDR between the p-type well region PWR on the right side of the figure and the n-type well region NWR in the center, the value of b is only 25 nm in the region overlapping the continuous gate electrode G2. It becomes smaller. The shift amount of the mask for p-type implantation in the unintended left-right direction here, 25 nm, is the value on the vertical axis of the graph of FIG.

  Assuming that both the n-type implantation mask NMK and the p-type implantation mask PMK can deviate by at most 25 nm, the distance b in FIG. 16B, which should originally be 50 nm, is at most 100 nm and at most 0 It becomes. Taking this into consideration, as shown in FIG. 16A, the distance a between the boundary BDR and the active region AR is 100 nm.

  Referring again to FIG. 21, here, three types of different average values of the sizes of the particles constituting the polycrystalline silicon in the continuous gate electrode G1 (average values of average values of diameters when the particles are approximated to be spherical) Shows the change in the absolute value of the threshold voltage relative to the amount of positional deviation of the n-type implantation mask NMK (the pattern of the photoresist PHR) when the above b is not present as in the comparative example using the continuous gate electrode G1 of ing. Note that L in the graph is about 10% of the average value of M with respect to M when the average value of the grain size of polycrystalline silicon in the continuous gate electrode G1 is about 10% larger than M. The small cases are shown respectively. Here, the displacement amount of the position of the resist (n-type implantation mask NMK) indicates the displacement amount in the case of displacement in the direction in which the distance b in FIG. For example, the shift amount of 25 nm of the resist position in the first embodiment in the graph corresponds to the case where the value of b is 75 nm.

  Referring to FIG. 21, when using a resist pattern having protrusions TKI as in the present embodiment as compared to the case where a resist pattern having no protrusions TKI is used as in the comparative example, the straight lines of each graph Interval is narrow and its inclination is large. This means that in the present embodiment, the variation of the threshold voltage is smaller than that of the comparative example regardless of the grain size of polycrystalline silicon and the amount of positional deviation of the n-type implantation mask NMK. It shows. Such reduction of the variation in threshold voltage is realized by forming the buffer region BFR having a width of 100 nm or more in the continuous gate electrode G1 as described above.

  Moreover, the value of the absolute value of the threshold voltage is generally smaller in the present embodiment than in the comparative example. Therefore, the current flowing to the transistor can be larger in the present embodiment than in the comparative example, and the driving capability of the transistor can be enhanced.

  Next, using FIGS. 22A and 22B, in the present embodiment (instead of shifting the injection position of the p-type conductive impurity to the n-type well region NWR side), the injection of the n-type conductive impurity The reason for shifting the position to the p-type well region PWR will be described.

  Referring to FIGS. 22A and 22B, these graphs show the cumulative distribution of the threshold voltage. That is, the horizontal axis indicates the value of the threshold voltage of the MOS transistor included in a CMOS inverter or the like including the continuous gate electrode G1, and the vertical axis of the graph indicates the standard deviation σ of the threshold voltage.

  In the conductive film PS forming the continuous gate electrode, implantation is performed so that the positions of the boundaries between the region into which the n-type conductive impurity is implanted and the region into which the p-type conductive impurity is implanted are equal as in the comparative example. FIG. 22A shows the calculation result when the position of the boundary is shifted to the n-type conductive impurity implantation region side, and the position of the boundary is shifted to the p-type conductive impurity implantation region side. The calculation result of the time is shown in FIG. A plurality of data shown in FIGS. 22A and 22B indicate data of the conductive film PS in each case where the position of the boundary is different as described above.

  As shown in FIG. 22A, when the position of the boundary is shifted to the n-type conductive impurity injection side (p-type well region PWR side), the data of the respective graphs almost overlap, so that shift Even if the position of the boundary changes, the threshold voltage does not vary due to that. On the other hand, according to FIG. 22B, when the position of the boundary is shifted to the implantation side of the p-type conductive impurity (n-type well region NWR side), the graphs do not overlap each other and to the left and right. From the distributed distribution, it is understood that if the position of the boundary changes due to the shift, the value of the threshold voltage changes because of that.

  From this, even if the boundary of the n-type conductive impurity injection region is shifted to the n-type conductive impurity injection side (p-type well region PWR side), the n-type gate electrode NG of the CMOS inverter formed by this is It can be seen that the threshold voltage of the (driver) transistor that contains Therefore, in the present embodiment, as shown in FIG. 12, the boundary (end portion EG) of the implantation of the p-type conductive impurity is fixed to the boundary BDR of the well region, and as shown in FIG. The implantation boundary (end EG) is moved to the p-type well region PWR side more than the boundary region BDR of the well region.

Second Embodiment
Referring to FIGS. 23-25, in the present embodiment, both of continuous gate electrode G1 and isolation insulating film SI in the vicinity (of adjacent regions) and active region AR are shown in FIGS. 3-5. It has the same appearance shape as that in the first embodiment. In addition, the concentration distribution and technical characteristics of p-type conductive impurities and n-type conductive impurities in gate electrodes NG and PG and buffer region BFR in continuous gate electrode G1 shown in FIG. Since it becomes the same as the concentration distribution of the first embodiment shown in FIG. In the present embodiment, only the continuous gate electrode G1 and the (adjacent) isolation insulating film SI in the vicinity thereof will be described.

  26, in the present embodiment, the distribution of the impurity concentration in isolation insulating film SI adjacent to continuous gate electrode G1 is basically the same as that of FIG. 9 of the first embodiment. That is, similarly to isolation insulating film SI adjacent to access gate electrode GA of the first embodiment, boundary BR between a region having p-type conductive impurity as a majority carrier and a region having n-type conductive impurity region as a majority carrier is It is formed at a position substantially overlapping the boundary portion BDR. However, in FIG. 26, the concentrations of the p-type conductive impurity and the n-type conductive impurity in the vicinity of the boundary BR are slightly smaller than those in FIG.

  In the present embodiment, the p-type conductive impurity and the n-type conductive impurity are implanted at an inclination angle so as to avoid the boundary portion BDR. Further, in the present embodiment, the implantation is performed using p-type implantation mask PMK having no projection TKI in all the regions including continuous gate electrode G1. As described above, since the conductive impurities are not diffused so much by heating in the isolation insulating film SI, the distribution of the implantation density of the conductive impurities is reflected to some extent in the final product after the heat treatment.

  The configuration of the present embodiment other than this is substantially the same as the configuration of the present embodiment, and therefore the same elements are denoted by the same reference characters and description thereof will not be repeated. Next, a manufacturing method according to the present embodiment will be described with reference to FIGS.

  Referring to FIGS. 27 (A), (B) and 29 (A), p-type is performed in the same manner as the process of FIG. An implantation mask PMK is formed, and a p-type conductive impurity (for example, boron) is implanted into the conductive film PS immediately above the n-type well region NWR using this. As in the first embodiment, the p-type implantation mask PMK formed here basically overlaps the n-type well region NWR, and its end portion EG corresponds to the n-type well region NWR and the p-type well region PWR. And the boundary BDR directly above.

  However, in the first embodiment of FIG. 12, the p-type conductive impurity is implanted in the direction (vertical direction in the figure) substantially perpendicular to main surface S1 of semiconductor substrate SUB as shown by the arrow in the figure. In FIG. 27, the n-type conductive impurity is implanted from an angle inclined with respect to the direction perpendicular to the main surface S1 so as to face the n-type well region NWR side from the boundary portion BDR. That is, the implanted p-type conductive impurity moves away from boundary portion BDR as it approaches conductive film PS (as it moves downward) and proceeds toward n-type well region NWR with respect to the direction along main surface S1 (p-type well It is injected so as to have an inclined angle away from the region PWR. This is the same in both the conductive film PS where the continuous gate electrode is to be formed and in the vicinity thereof. FIG. 27A shows a portion along line XXVIIA-XXVIIA in FIG. 29A, and FIG. 27B shows a portion along line XXVIIB-XXVIIB in FIG.

  Referring to FIGS. 28 (A), (B) and 29 (B), a mask NMK for n-type implantation is formed in the same manner as in the step of FIG. An n-type conductive impurity (for example, phosphorus) is implanted into the conductive film PS. However, unlike the n-type implantation mask NMK of the first embodiment, the n-type implantation mask NMK formed here has no protrusion TKI, and is similar to the n-type implantation mask NMK of the comparative example of FIG. The end EG is disposed right above the boundary BDR between the n-type well region NWR and the p-type well region PWR.

  Then, in FIG. 28, the p-type conductive impurity is implanted at an angle inclined to main surface S1 so as to face the p-type well region PWR side from boundary portion BDR. That is, the implanted n-type conductive impurity moves away from boundary portion BDR as it approaches conductive film PS (as it moves downward) and proceeds toward p-type well region PWR with respect to the direction along main surface S1 (n-type well It is injected so as to have an inclined angle away from the region NWR. This is the same in both the conductive film PS where the continuous gate electrode is to be formed and in the vicinity thereof. Note that FIG. 28A shows a portion along line XXVIIIA-XXVIIIA in FIG. 29B, and FIG. 28B shows a portion along line XXVIIIB-XXVIIIB in FIG.

  The subsequent steps are the same as the steps after FIG. 14 of the first embodiment, and therefore the description thereof is omitted.

Next, the operation and effect of the present embodiment will be described.
In the present embodiment, implantation is performed at an angle inclined to the direction perpendicular to main surface S1 so as to face n-type well region NWR or p-type well PWR from boundary portion BDR. Therefore, depending on the implantation angle and the height of the pattern of photoresist PHR (the thickness in the direction perpendicular to main surface S1), a region called a shadowing region, which is interrupted by photoresist PHR and is not implanted with conductive impurities, In particular, it is formed in the vicinity of the boundary portion BDR (end portion EG).

  Therefore, in the same manner as in Embodiment 1 where a region into which neither p-type nor n-type conductive impurities are implanted is formed by protrusion TKI, boundary BDR (end part EG) is also particularly present in this embodiment. There is formed a region where neither p-type nor n-type conductive impurities are implanted. Therefore, also in the present embodiment, as in the first embodiment, buffer region BFR can be formed, whereby the interdiffusion of conductive impurities in continuous gate electrode G1, the variation in threshold voltage associated therewith, etc. Problems can be suppressed.

Third Embodiment
In the present embodiment, technical features of the first embodiment and the second embodiment are combined. More specifically, using n-type implantation mask NMK having protrusions TKI as shown in the first embodiment, p-type and n-type are formed at an angle inclined to the direction perpendicular to main surface S1 as in the second embodiment. Conductive impurities are implanted. As described above, in the present embodiment, a buffer region BFR having a low impurity concentration is widely formed in the first and second embodiments or more by the synergetic effect of the first and second embodiments, and a technique for suppressing variation in threshold voltage. Effects are enhanced. Also in the present embodiment, description will be made focusing on only the continuous gate electrode G1 and the isolation insulating film SI in the vicinity (adjacent) thereof.

  Referring to FIG. 30, which faithfully reflects the density distribution of implantation, the conductive impurity distribution in isolation insulating film SI in the region adjacent to continuous gate electrode G1 in the present embodiment is similar to that of the second embodiment of FIG. In this embodiment, the boundary BR is formed slightly on the left side (p-type well region PWR side) compared to the inside of the isolation insulating film SI. Further, the concentration of the conductive impurities is significantly reduced in the vicinity of the boundary BR as compared with the isolation insulating film SI of the second embodiment. This means that the concentration of the conductive impurities is significantly reduced also in the buffer region BFR in the vicinity of the isolation insulating film SI.

  Referring to FIGS. 31 (A), (B) and FIG. 32, between n-type conductive impurity implanted region and p-type conductive impurity implanted region by n-type implantation mask NMK having protrusion TKI. An air gap is formed. Furthermore, the injection angle is inclined as in the second embodiment, whereby the above-mentioned air gap is formed wider. 31 (A) shows a portion along the line XXXIA-XXXIA in FIG. 32, and FIG. 31 (B) shows a portion along the line XXXIB-XXXIB in FIG.

  In Embodiments 2 and 3, the p-type and n-type conductive impurities are preferably implanted at an angle that can prevent the conductive impurities from penetrating at the bottom of the pattern of photoresist PHR. .

  Referring to FIG. 33, the horizontal axis of this graph indicates the absolute value of the threshold voltage of gate electrodes NG and PG formed on continuous gate electrode G1 described above, and the vertical axis indicates the conductive impurity to be implanted. Denotes an inclination angle with respect to the direction perpendicular to the main surface S1. The “Embodiment 2” in the figure is the case where a resist pattern having no protrusion TKI is used as in the graph of FIG. 21, and the “Embodiment 3” is a protrusion TKI as in the graph of FIG. Shows the results when using a resist pattern having. Further, L, M, and S in the graph are the same as those in the graph of FIG.

  As shown in FIG. 33, compared to the case where the implantation angle is inclined using the resist pattern having no protrusion TKI as in the second embodiment, the resist pattern having a protrusion TKI as in this embodiment is used. When the injection angle is inclined, the distance between the straight lines in each graph is narrower and the inclination is larger. This means that in the present embodiment, the variation in threshold voltage is smaller than in Embodiment 2 regardless of the grain size of polycrystalline silicon and the amount of positional deviation of n-type implantation mask NMK. Is shown.

  In the above, the continuous gate electrodes of the driver transistor and the load transistor constituting the flip-flop circuit of the SRAM have been mainly described, but the present invention is not limited thereto, and gate electrodes having a plurality of different electrical polarities like ordinary CMOS inverters The present embodiment is applicable to any semiconductor device having a continuous structure.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the above-mentioned embodiment, and can be variously changed in the range which does not deviate from the gist. Needless to say.

  AR active region, BDR boundary portion, BFR buffer region, BL, ZBL bit line, BRL barrier metal, C1, C2, C3, C4, C5, C6, C7, C8 contacts, CHL channel layer, D drain electrode, DV semiconductor device , EG end, G1, G2 continuous gate electrode, GA access gate electrode, GI gate insulating film, II1, II2, II3, II4 interlayer insulating film, II5 insulating film, M1, M2, M3, M4 metal wiring, N1, N1a , N1b first storage node unit, N2, N2a, N2b second storage node unit, NG, PG gate electrode, NMK n-type implantation mask, NW n-type well formation region, NWR n-type well region, OF offset Spacer, PD pad area, PHR photoresist, PMK p-type implantation mask, PS conductive film PW p-well forming region, PWR p-well region, S source electrode, S1 main surface, SI isolation insulating film, SUB semiconductor substrate, SW sidewall insulating film, T1, T2 driver transistor, T3, T4 load transistor, T5, T6 access transistor, TKI protrusion, WL word line.

Claims (4)

Forming an n-type well region and an adjacent p-type well region in the semiconductor substrate to form a boundary by contacting the n-type well region in a semiconductor substrate having a main surface;
Forming a conductive film extending across the n-type and p-type well regions on the main surface;
Implanting a p-type conductive impurity into the conductive film directly above the n-type well region;
Implanting an n-type conductive impurity into the conductive film directly above the p-type well region;
Heat treating the conductive film;
In the step of implanting the p-type conductive impurity, the p-type conductive impurity is implanted from an angle inclined to a direction perpendicular to the main surface so as to face the n-type well region side from the boundary portion. ,
In the step of implanting the n-type conductive impurity, the n-type conductive impurity is implanted at an angle inclined to a direction perpendicular to the main surface so as to face the p-type well region side from the boundary portion. Semiconductor device manufacturing method. A continuous gate electrode including a first gate electrode formed in the step of implanting the p-type conductive impurity and a second gate electrode formed in the step of implanting the n-type conductive impurity; between the gate electrode and the second gate electrode of the both concentrations of n-type conductivity impurities and the p-type conductive impurities is not more than 5 × 10 ¹⁹ cm ^-3, said first gate electrode The method for manufacturing a semiconductor device according to claim 1, wherein a buffer region having a width of 100 nm or more in a direction connecting the second gate electrode and the second gate electrode is formed. The continuous gate electrode is formed in a memory cell region in which a static memory cell is formed.
The first gate electrode is formed to be included in a load transistor that configures the static memory cell, and the second gate electrode is formed to be included in a driver transistor that configures the static memory cell. The method of manufacturing a semiconductor device according to claim 2. In the step of implanting the p-type conductive impurity, a first implantation mask is formed so that an end portion is disposed immediately above the boundary portion, thereby forming the first gate electrode on the conductive film. Is formed,
In the step of implanting the n-type conductive impurity, the second implantation mask is formed such that an end portion is disposed closer to the p-type well region than the boundary portion. The method for manufacturing a semiconductor device according to claim 2, wherein the second gate electrode is formed in a region different from the first gate electrode.

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