JP2006278951A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2006278951A
JP2006278951A JP2005099208A JP2005099208A JP2006278951A JP 2006278951 A JP2006278951 A JP 2006278951A JP 2005099208 A JP2005099208 A JP 2005099208A JP 2005099208 A JP2005099208 A JP 2005099208A JP 2006278951 A JP2006278951 A JP 2006278951A
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substrate
semiconductor chip
semiconductor device
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semiconductor
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Mikito Shimoyama
幹人 下山
Yuichi Yanagida
雄一 柳田
Satoshi Kogure
敏 木暮
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Mitsuba Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To increase the certainty of a wire bonding, without lowering a heat radiation of a semiconductor chip. <P>SOLUTION: A semiconductor device 11 has a substrate 12 provided with a wiring pattern 13, and a semiconductor chip 15 secured to the substrate 12 via a heat spreader 16. The bonding pad 15a of the semiconductor chip 15 and the pad 13a of the circuit pattern 13 are electrically connected to a bonding wire 21 by ultrasonic welding. In order to radiate heat generated by the semiconductor chip 15 from a back face side of the substrate 12, a plurality of kinds of through-holes 22, having a different sectional area, are formed in the substrate 12. These through-holes 22 are disposed in the fixed region T of the semiconductor chip 15, enlarged by the heat spreader 16 and at a position where overlap with the bonding pad 15a is avoided. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、配線パターンを備えた基板と、基板上に固定される半導体チップと、半導体チップに設けられるボンディングパッドと配線パターンとを電気的に接続するボンディングワイヤとを有する半導体装置に関し、特に、ボンディングワイヤを超音波溶接により接続するようにしたものに関する。   The present invention relates to a semiconductor device having a substrate provided with a wiring pattern, a semiconductor chip fixed on the substrate, and a bonding wire electrically connecting a bonding pad provided on the semiconductor chip and the wiring pattern. The present invention relates to a bonding wire connected by ultrasonic welding.

従来から、ガラスエポキシにより形成される基板上にダイパッドやヒートスプレッダ等の台座部材を介して半導体チップを搭載するとともに、半導体チップの上面に設けられるボンディングパッドと基板上に形成された配線パターンとをボンディングワイヤにより接続した構造の半導体装置が知られている。このような半導体装置では、ボンディングワイヤとボンディングパッドとを接続するワイヤボンディングは超音波溶接により行われ、超音波溶接においては、ボンディングパッド上に配置されたボンディングワイヤの先端部に超音波溶接機のホーンが押し付けられ、ホーンが発する超音波によりワイヤに摩擦熱が発生して、ワイヤがパッドに溶着される。   Conventionally, a semiconductor chip is mounted on a substrate formed of glass epoxy via a pedestal member such as a die pad or a heat spreader, and a bonding pad provided on the upper surface of the semiconductor chip and a wiring pattern formed on the substrate are bonded. A semiconductor device having a structure connected by a wire is known. In such a semiconductor device, wire bonding for connecting a bonding wire and a bonding pad is performed by ultrasonic welding, and in ultrasonic welding, an ultrasonic welding machine is attached to the tip of the bonding wire arranged on the bonding pad. The horn is pressed, and frictional heat is generated in the wire by ultrasonic waves emitted from the horn, and the wire is welded to the pad.

ガラスエポキシにより形成される基板は熱伝導率が低いので、基板上に実装される半導体チップが発生する熱を効率よく放熱させる構造が必要であり、そのため、特許文献１に示される半導体装置では、基板に厚み方向に貫通する多数のスルーホールを形成し、半導体チップが発する熱をこれらのスルーホールを介して基板の裏面側から放熱させるようにしている。この場合、スルーホールは基板上の半導体チップが固定される固定領域内に形成され、スルーホールの内部には導体が充填されてダイパッドと接するサーマルビアが形成されており、半導体チップが発した熱をダイパッドとサーマルビアとを介してスルーホールから放熱するようにしている。
特開２００１−１３１５１７号公報（第１５頁、図１） Since the substrate formed of glass epoxy has low thermal conductivity, a structure that efficiently dissipates the heat generated by the semiconductor chip mounted on the substrate is necessary. Therefore, in the semiconductor device shown in Patent Document 1, A large number of through holes penetrating in the thickness direction are formed in the substrate, and heat generated by the semiconductor chip is radiated from the back side of the substrate through these through holes. In this case, the through hole is formed in a fixed region where the semiconductor chip on the substrate is fixed, and a thermal via that is filled with a conductor and is in contact with the die pad is formed inside the through hole. Heat is radiated from the through hole through the die pad and the thermal via.
Japanese Patent Laying-Open No. 2001-131517 (page 15, FIG. 1)

しかしながら、特許文献１に示される半導体装置では、スルーホールは半導体チップの固定領域内であってボンディングパッドに対して基板の厚み方向の直下に位置するように基板に形成されているので、ワイヤボンディングのためにボンディングパッド上にホーンを配置すると、このホーンの直下にスルーホールが位置する場合がある。そして、このような状態でホーンから超音波が発せられると、その超音波がスルーホールを介して基板の裏側に逃げ、これによりワイヤボンディングの確実性が低下するおそれがある。これに対して、半導体チップの固定領域内にスルーホールが形成されない基板を用いて半導体装置を製造する方法が考えられるが、この方法では、半導体チップの放熱性が低下することになる。   However, in the semiconductor device disclosed in Patent Document 1, the through hole is formed in the substrate so as to be located in the fixing region of the semiconductor chip and directly below the bonding pad in the thickness direction of the substrate. For this reason, when a horn is disposed on the bonding pad, a through hole may be located immediately below the horn. When ultrasonic waves are emitted from the horn in such a state, the ultrasonic waves escape to the back side of the substrate through the through holes, which may reduce the reliability of wire bonding. On the other hand, a method of manufacturing a semiconductor device using a substrate in which a through hole is not formed in the fixed region of the semiconductor chip is conceivable. However, in this method, the heat dissipation of the semiconductor chip is lowered.

本発明の目的は、半導体チップの放熱性を低下させることなく、ワイヤボンディングの確実性を高めることにある。   An object of the present invention is to increase the reliability of wire bonding without deteriorating the heat dissipation of a semiconductor chip.

本発明の半導体装置は、配線パターンを備えた基板と、前記基板上に固定される半導体チップと、前記半導体チップの前記基板に固定される面とは反対側の面に設けられるボンディングパッドと前記配線パターンとに超音波溶接により電気的に接続されるボンディングワイヤとを有する半導体装置であって、前記基板の前記半導体チップが固定される固定領域内であって、且つ、前記ボンディングパッドとの重複を避けた位置に、前記半導体チップの熱を前記基板の前記半導体チップが固定される面とは反対側の面へ誘導する熱誘導手段が設けられることを特徴とする。   The semiconductor device of the present invention includes a substrate having a wiring pattern, a semiconductor chip fixed on the substrate, a bonding pad provided on a surface of the semiconductor chip opposite to the surface fixed to the substrate, A semiconductor device having a bonding wire electrically connected to a wiring pattern by ultrasonic welding, wherein the semiconductor device is in a fixed region where the semiconductor chip of the substrate is fixed, and overlaps with the bonding pad A heat induction means for guiding the heat of the semiconductor chip to a surface of the substrate opposite to the surface on which the semiconductor chip is fixed is provided at a position avoiding the above.

本発明の半導体装置は、断面積の異なる複数種類の前記熱誘導手段を有することを特徴とする。   The semiconductor device of the present invention has a plurality of types of heat induction means having different cross-sectional areas.

本発明の半導体装置は、前記熱誘導手段は前記基板を貫通するスルーホールであることを特徴とする。   The semiconductor device of the present invention is characterized in that the heat induction means is a through hole penetrating the substrate.

本発明の半導体装置は、前記スルーホールの内壁に導体がメッキされていることを特徴とする。   The semiconductor device of the present invention is characterized in that a conductor is plated on the inner wall of the through hole.

本発明の半導体装置は、導体により形成され前記基板と前記半導体チップとの間に配置されて前記固定領域を拡大する台座部材を有することを特徴とする。   The semiconductor device of the present invention includes a pedestal member that is formed of a conductor and is disposed between the substrate and the semiconductor chip and expands the fixed region.

本発明の半導体装置は、前記台座部材の熱膨張係数は前記基板の熱膨張係数と前記半導体チップの熱膨張係数との中間の値を有することを特徴とする。   The semiconductor device according to the present invention is characterized in that the thermal expansion coefficient of the pedestal member has an intermediate value between the thermal expansion coefficient of the substrate and the thermal expansion coefficient of the semiconductor chip.

本発明の半導体装置の製造方法は、配線パターンを備えた基板と、前記基板上に固定される半導体チップと、前記半導体チップに設けられるボンディングパッドと前記配線パターンとを電気的に接続するボンディングワイヤとを有する半導体装置の製造方法であって、前記基板に設けられ前記半導体チップの熱を前記基板の前記半導体チップが固定される面とは反対側の面へ誘導する熱誘導手段が前記半導体チップの固定領域内に位置し、且つ、前記熱誘導手段と前記ボンディングパッドとの重複を避けるように前記基板上に前記半導体チップを固定する半導体固定工程と、前記配線パターンと前記ボンディングパッドとに超音波溶接により前記ボンディングワイヤを電気的に接続するワイヤ接続工程とを有することを特徴とする。   A method of manufacturing a semiconductor device according to the present invention includes a substrate having a wiring pattern, a semiconductor chip fixed on the substrate, a bonding pad provided on the semiconductor chip, and a bonding wire for electrically connecting the wiring pattern. And a heat induction means for inducing heat of the semiconductor chip provided on the substrate to a surface of the substrate opposite to a surface to which the semiconductor chip is fixed. A semiconductor fixing step of fixing the semiconductor chip on the substrate so as to avoid duplication of the heat induction means and the bonding pad, and the wiring pattern and the bonding pad. A wire connecting step of electrically connecting the bonding wires by sonic welding.

本発明の半導体装置の製造方法は、断面積の異なる複数種類の前記熱誘導手段を有することを特徴とする。   The method of manufacturing a semiconductor device according to the present invention is characterized in that it has a plurality of types of the heat induction means having different cross-sectional areas.

本発明の半導体装置の製造方法は、前記熱誘導手段は前記基板を貫通するスルーホールであることを特徴とする。   In the method of manufacturing a semiconductor device according to the present invention, the heat induction means is a through hole penetrating the substrate.

本発明の半導体装置の製造方法は、前記スルーホールの内壁に導体がメッキされていることを特徴とする。   The semiconductor device manufacturing method of the present invention is characterized in that a conductor is plated on the inner wall of the through hole.

本発明の半導体装置の製造方法は、前記ワイヤ接続工程を行う際に、超音波溶接装置上に前記基板を位置決め固定することを特徴とする。   The method of manufacturing a semiconductor device according to the present invention is characterized in that the substrate is positioned and fixed on an ultrasonic welding apparatus when performing the wire connecting step.

本発明の半導体装置の製造方法は、導体により形成され前記基板と前記半導体チップとの間に配置されて前記固定領域を拡大する台座部材を有することを特徴とする。   The method of manufacturing a semiconductor device according to the present invention is characterized by having a pedestal member that is formed of a conductor and is disposed between the substrate and the semiconductor chip and expands the fixed region.

本発明の半導体装置の製造方法は、前記台座部材の熱膨張係数は前記基板の熱膨張係数と前記半導体チップの熱膨張係数との中間の値を有することを特徴とする。   The semiconductor device manufacturing method of the present invention is characterized in that the thermal expansion coefficient of the base member has an intermediate value between the thermal expansion coefficient of the substrate and the thermal expansion coefficient of the semiconductor chip.

本発明によれば、基板に設けられる熱誘導手段を半導体チップの固定領域内であって、且つ、ボンディングパッドとの重複を避けた位置に配置するようにしたので、ボンディングワイヤをボンディングパッドに超音波溶接する際に、超音波が熱誘導手段を介して基板の裏側に逃げることを防止して、ワイヤボンディングの確実性を高めることができる。これに加えて、熱誘導手段は半導体チップの固定領域内に配置されているので、半導体チップの放熱性を確保することができる。   According to the present invention, since the heat induction means provided on the substrate is arranged in the fixed region of the semiconductor chip and at a position avoiding the overlap with the bonding pad, the bonding wire is superposed on the bonding pad. When performing sonic welding, the ultrasonic waves can be prevented from escaping to the back side of the substrate through the heat induction means, and the reliability of wire bonding can be improved. In addition, since the heat induction means is disposed in the fixed region of the semiconductor chip, the heat dissipation of the semiconductor chip can be ensured.

また、本発明によれば、断面積の異なる複数種類の熱誘導手段を設けるようにしたので、熱誘導手段のレイアウト性を高めることができる。したがって、半導体チップの固定領域内であって、且つ、ボンディングパッドと重複しない範囲に熱誘導手段を設ける場合であっても、その範囲に多数の熱誘導手段を配置して、十分な放熱性を確保することができる。   Further, according to the present invention, since a plurality of types of heat induction means having different cross-sectional areas are provided, the layout of the heat induction means can be improved. Therefore, even in the case where the heat induction means is provided in the fixed region of the semiconductor chip and not overlapping with the bonding pad, a large number of heat induction means are arranged in the range to provide sufficient heat dissipation. Can be secured.

さらに、本発明によれば、基板を貫通するスルーホールにより熱誘導手段を構成するようにしたので、基板を作成する際に、リード部品等を固定する固定孔とともに熱誘導手段を設けることができ、これにより半導体装置の製造コストを低減させることができる。   Furthermore, according to the present invention, since the heat induction means is constituted by the through hole penetrating the substrate, the heat induction means can be provided together with the fixing hole for fixing the lead component or the like when the substrate is formed. As a result, the manufacturing cost of the semiconductor device can be reduced.

さらに、本発明によれば、熱誘導手段として設けられるスルーホールの内面に導体をメッキするようにしたので、半導体チップの熱を導体のメッキ層を介して効率よく外部に放出して、半導体チップの放熱性を高めることができる。   Furthermore, according to the present invention, since the conductor is plated on the inner surface of the through hole provided as the heat induction means, the heat of the semiconductor chip is efficiently discharged to the outside through the plated layer of the conductor, and the semiconductor chip The heat dissipation can be improved.

さらに、本発明によれば、基板と半導体チップとの間に半導体チップの固定領域を拡大する台座部材を設けるようにしたので、スルーホールを配置可能な範囲が拡大され、半導体チップの発する熱を効率よく放熱させることができる。   Furthermore, according to the present invention, since the pedestal member that expands the fixing region of the semiconductor chip is provided between the substrate and the semiconductor chip, the range in which the through hole can be arranged is expanded, and the heat generated by the semiconductor chip is increased. It is possible to dissipate heat efficiently.

さらに、本発明によれば、台座部材の熱膨張係数は基板の熱膨張係数と半導体チップの熱膨張係数との中間の値を有するので、半導体チップと基板の熱膨張率の相違により発生する応力を台座部材により緩和することができる。したがって、半導体チップの熱膨張によるクラックの発生や基板からの離脱を防止することができる。   Further, according to the present invention, since the thermal expansion coefficient of the base member has an intermediate value between the thermal expansion coefficient of the substrate and the thermal expansion coefficient of the semiconductor chip, the stress generated due to the difference in the thermal expansion coefficient between the semiconductor chip and the substrate. Can be relaxed by the base member. Therefore, generation of cracks due to thermal expansion of the semiconductor chip and detachment from the substrate can be prevented.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

図１は本発明の一実施の形態である半導体装置の一部を示す上面図であり、図２は図１に示すＡ−Ａ線に沿う断面図である。   FIG. 1 is a top view showing a part of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line AA shown in FIG.

図１に示す半導体装置１１は平板状に形成された基板１２を有しており、この基板１２上には回路パターン１３が設けられ、回路パターン１３には３つのパッド部１３ａが設けられている。   A semiconductor device 11 shown in FIG. 1 has a substrate 12 formed in a flat plate shape. A circuit pattern 13 is provided on the substrate 12, and the circuit pattern 13 is provided with three pad portions 13a. .

本実施の形態においては、基板１２はガラス繊維をエポキシ樹脂で固めたガラスエポキシ基板となっており、回路パターン１３は銅箔により形成されているが、これに限らず、基板１２をポリイミド樹脂やアラミド樹脂で形成するようにしてもよく、回路パターン１３を導電ペーストや他の金属薄膜等で形成するようにしてもよい。   In the present embodiment, the substrate 12 is a glass epoxy substrate in which glass fibers are hardened with an epoxy resin, and the circuit pattern 13 is formed of a copper foil. You may make it form with an aramid resin, and you may make it form the circuit pattern 13 with an electrically conductive paste or another metal thin film.

基板１２上に設けられた半導体実装領域１４には半導体チップ１５が実装されており、この半導体チップ１５と回路パターン１３及び図示しない電子部品等により基板１２上に回路が形成される。半導体チップ１５はパッケージングが成されていないベアチップとなっており、台座部材としてのヒートスプレッダ１６を介して基板１２上に固定されている。   A semiconductor chip 15 is mounted on the semiconductor mounting region 14 provided on the substrate 12, and a circuit is formed on the substrate 12 by the semiconductor chip 15, the circuit pattern 13, and electronic components (not shown). The semiconductor chip 15 is a bare chip that is not packaged, and is fixed on the substrate 12 via a heat spreader 16 as a base member.

ヒートスプレッダ１６は、たとえば銅やタングステン系合金などの導体により形成されており、半導体チップ１５の発する熱を放熱する機能を有している。図２に示すように、ヒートスプレッダ１６は、その底面（基板１２と対向する面）において接着剤１７により基板１２上に固定され、半導体チップ１５はその底面（基板１２と対向する面）においてヒートスプレッダ１６の天面（基板１２と反対側を向く面）に接着剤１８により固定されており、これにより半導体チップ１５はヒートスプレッダ１６にマウントされた状態で基板１２上に固定される。また、ヒートスプレッダ１６の底面は半導体チップ１５の底面よりも大きく形成されており、これにより、基板１２の半導体チップ１５が固定される固定領域Ｔはヒートスプレッダ１６により拡大されている。つまり、半導体チップ１５を基板１２上に直接固定した場合には、基板１２上の半導体チップ１５の固定領域は半導体チップ１５の底面に対応する面積となり、半導体チップ１５が発する熱の基板１２側への伝達経路は半導体チップ１５の底面の範囲に限られるが、基板１２と半導体チップ１５との間にヒートスプレッダ１６を配置することにより、半導体チップ１５の固定領域Ｔはヒートスプレッダ１６の底面積にまで拡大され、半導体チップ１５が発する熱はヒートスプレッダ１６を介することにより半導体チップ１５が直接基板１２に固定された場合よりも広い伝達経路で基板１２側へ伝達される。   The heat spreader 16 is formed of a conductor such as copper or a tungsten alloy, for example, and has a function of radiating heat generated by the semiconductor chip 15. As shown in FIG. 2, the heat spreader 16 is fixed on the substrate 12 by an adhesive 17 on the bottom surface (surface facing the substrate 12), and the semiconductor chip 15 is heat spreader 16 on the bottom surface (surface facing the substrate 12). The semiconductor chip 15 is fixed on the substrate 12 in a state where it is mounted on the heat spreader 16. The semiconductor chip 15 is fixed to the top surface (the surface facing away from the substrate 12) with an adhesive 18. Further, the bottom surface of the heat spreader 16 is formed to be larger than the bottom surface of the semiconductor chip 15, whereby the fixing region T to which the semiconductor chip 15 of the substrate 12 is fixed is expanded by the heat spreader 16. That is, when the semiconductor chip 15 is directly fixed on the substrate 12, the fixing region of the semiconductor chip 15 on the substrate 12 has an area corresponding to the bottom surface of the semiconductor chip 15, and the heat generated by the semiconductor chip 15 moves toward the substrate 12. However, the heat spreader 16 is disposed between the substrate 12 and the semiconductor chip 15, so that the fixed region T of the semiconductor chip 15 is expanded to the bottom area of the heat spreader 16. Then, the heat generated by the semiconductor chip 15 is transmitted to the substrate 12 side through the heat spreader 16 through a wider transmission path than when the semiconductor chip 15 is directly fixed to the substrate 12.

また、ヒートスプレッダ１６の熱膨張係数は基板１２の熱膨張係数と半導体チップ１５の熱膨張係数の中間の値を有しており、これにより、半導体チップ１５が発する熱により半導体チップ１５、ヒートスプレッダ１６及び基板１２が加熱された場合であっても、これらの熱膨張率の違いにより発生する応力をヒートスプレッダ１６により緩和して、半導体チップ１５のクラックの発生や基板１２からの半導体チップ１５の離脱等を防止することができる。   Further, the thermal expansion coefficient of the heat spreader 16 has an intermediate value between the thermal expansion coefficient of the substrate 12 and the thermal expansion coefficient of the semiconductor chip 15, whereby the semiconductor chip 15, the heat spreader 16 and the heat spreader 16 are heated by the heat generated by the semiconductor chip 15. Even when the substrate 12 is heated, the stress generated by the difference in the coefficient of thermal expansion is relaxed by the heat spreader 16, so that the generation of cracks in the semiconductor chip 15, the separation of the semiconductor chip 15 from the substrate 12, and the like. Can be prevented.

半導体チップ１５の天面（つまり、この半導体チップ１５の基板１２に固定される面とは反対側の面）には３つの電極つまりボンディングパッド１５ａが並べて設けられ、これらのボンディングパッド１５ａと回路パターン１３のパッド部１３ａには、超音波溶接によりボンディングワイヤ２１が電気的に接続されている。これにより、半導体チップ１５は回路パターン１３を介して図示しない電子部品等に接続され、この半導体装置１１の回路を構成する。   Three electrodes, that is, bonding pads 15a, are provided side by side on the top surface of the semiconductor chip 15 (that is, the surface opposite to the surface fixed to the substrate 12 of the semiconductor chip 15). The bonding wire 21 is electrically connected to the 13 pad portions 13a by ultrasonic welding. Thereby, the semiconductor chip 15 is connected to an electronic component or the like (not shown) via the circuit pattern 13 and constitutes a circuit of the semiconductor device 11.

図３は基板に形成され半導体チップの熱を基板の半導体チップが固定される面とは反対側の面へ誘導する熱誘導手段としてのスルーホールのレイアウトを示す上面図であり、図３に示すように、基板１２には半導体チップ１５が発する熱を基板１２の裏面側から外部に放熱するために、半導体実装領域１４内に位置して複数のスルーホール２２が設けられている。図２、図３に示すように、これらのスルーホール２２はそれぞれ断面円形に形成され、それぞれ基板１２の厚み方向に貫通している。また、これらのスルーホール２２は、基板１２の厚み方向から見た場合において、ヒートスプレッダ１６（図３に１点鎖線で示す）には重複し、且つ、半導体チップ１５（図３に２点鎖線で示す）には重複しない範囲に配置されており、つまり、図２に示すように、半導体チップ１５の固定領域Ｔの内側であって、且つ、ボンディングパッド１５ａとの重複を避けた範囲Ｒに配置されている。   FIG. 3 is a top view showing a layout of through-holes as heat induction means formed on the substrate for guiding the heat of the semiconductor chip to the surface of the substrate opposite to the surface on which the semiconductor chip is fixed. As described above, the substrate 12 is provided with a plurality of through holes 22 located in the semiconductor mounting region 14 in order to dissipate the heat generated by the semiconductor chip 15 from the back side of the substrate 12 to the outside. As shown in FIGS. 2 and 3, these through-holes 22 are each formed in a circular cross section and penetrate through the substrate 12 in the thickness direction. These through holes 22 overlap the heat spreader 16 (indicated by a one-dot chain line in FIG. 3) when viewed from the thickness direction of the substrate 12, and the semiconductor chip 15 (in a two-dot chain line in FIG. 3). 2), that is, in the range R that is inside the fixed region T of the semiconductor chip 15 and avoids the overlap with the bonding pad 15a, as shown in FIG. Has been.

範囲Ｒの内側に配置されるスルーホール２２は、その外側に配置されるスルーホール２２よりも直径つまり断面積が大きく形成されており、このように断面積の異なる複数種類のスルーホール２２を設けることにより、スルーホール２２のレイアウト性を高めている。これにより、固定領域Ｔ内であって、且つ、ボンディングパッド１５ａと重複しない限られた範囲に多数のスルーホール２２を設けることを可能としている。   The through hole 22 arranged inside the range R has a larger diameter, that is, a cross-sectional area, than the through hole 22 arranged outside the range R. Thus, a plurality of types of through holes 22 having different cross-sectional areas are provided. As a result, the layout of the through hole 22 is improved. Thereby, it is possible to provide a large number of through holes 22 in a limited range within the fixed region T and not overlapping with the bonding pad 15a.

このような構成により、半導体チップ１５が発生した熱はヒートスプレッダ１６を介して基板１２側に伝達され、これらのスルーホール２２を介して基板１２の裏面側から外部に放熱され、半導体チップ１５の放熱性が確保される。   With such a configuration, the heat generated by the semiconductor chip 15 is transmitted to the substrate 12 side through the heat spreader 16, and is radiated to the outside from the back side of the substrate 12 through these through holes 22. Sex is secured.

図４（ａ）〜（ｃ）は図１に示す半導体装置の製造手順を示す断面図であり、図５はワイヤ接続工程に用いられる超音波溶接装置の概略を示す側面図である。   4A to 4C are cross-sectional views showing the manufacturing procedure of the semiconductor device shown in FIG. 1, and FIG. 5 is a side view schematically showing the ultrasonic welding apparatus used in the wire connecting step.

次に、図４、図５に基づいて、この半導体装置１１の製造方法について説明する。   Next, a method for manufacturing the semiconductor device 11 will be described with reference to FIGS.

まず、前工程において予め基板１２に回路パターン１３やスルーホール２２が形成され、次いで、基板１２上に半導体チップ１５を固定する半導体固定工程が行われる。図４（ａ）に示すように、半導体固定工程においては、基板１２に設けられたスルーホール２２が当該半導体チップ１５の固定領域Ｔ内に位置し、且つ、基板１２の厚み方向から見てボンディングパッド１５ａとスルーホール２２との重複を避けるように半導体チップ１５が基板１２上に固定される。本実施の形態においては、半導体チップ１５はヒートスプレッダ１６を介して基板１２に固定されるので、半導体チップ１５はヒートスプレッダ１６とスルーホール２２が重複し、且つ、半導体チップ１５とスルーホール２２との重複を避けた位置に固定される。   First, in the previous step, the circuit pattern 13 and the through hole 22 are formed in the substrate 12 in advance, and then a semiconductor fixing step for fixing the semiconductor chip 15 on the substrate 12 is performed. As shown in FIG. 4A, in the semiconductor fixing step, the through hole 22 provided in the substrate 12 is located in the fixing region T of the semiconductor chip 15 and bonding is performed when viewed from the thickness direction of the substrate 12. The semiconductor chip 15 is fixed on the substrate 12 so that the pad 15a and the through hole 22 are not overlapped. In the present embodiment, since the semiconductor chip 15 is fixed to the substrate 12 via the heat spreader 16, the heat spreader 16 and the through hole 22 overlap the semiconductor chip 15, and the semiconductor chip 15 and the through hole 22 overlap. It is fixed at a position that avoids.

次に、ワイヤ接続工程により、半導体チップ１５のボンディングパッド１５ａと回路パターン１３のパッド部１３ａとにボンディングワイヤ２１が超音波溶接により電気的に接続される。   Next, the bonding wire 21 is electrically connected to the bonding pad 15a of the semiconductor chip 15 and the pad portion 13a of the circuit pattern 13 by ultrasonic welding in a wire connection process.

図５に示すように、ワイヤ接続工程で用いられる超音波溶接装置２３は、ボンディングワイヤ２１をボンディングパッド１５ａあるいは回路パターン１３のパッド部１３ａに押し付けるためのホーン２４とホーン２４を支持しこれに加圧力を加えるアーム２５および図示しない超音波発生器とを有し、超音波発生器の作動によりホーン２４の先端からは超音波が発せられる。   As shown in FIG. 5, the ultrasonic welding apparatus 23 used in the wire connecting process supports and adds a horn 24 and a horn 24 for pressing the bonding wire 21 against the bonding pad 15a or the pad portion 13a of the circuit pattern 13. An arm 25 for applying pressure and an ultrasonic generator (not shown) are provided, and ultrasonic waves are emitted from the tip of the horn 24 by the operation of the ultrasonic generator.

ワイヤ接続工程を行う際には、まず、図５に示すように、基板１２が超音波溶接装置２３のベース２６上にクランプ２７により位置決め固定され、これにより、超音波溶接時における基板１２の共振が防止される。次いで、図４（ｂ）に示すように、ボンディングワイヤ２１の先端がホーン２４によりボンディングパッド１５ａに押し付けられ、この状態でホーン２４から超音波が発せられる。ホーン２４から超音波が発せられると、基板１２を介してベース２６に固定された状態の半導体チップ１５に対してボンディングワイヤ２１が振動し、その振動により摩擦熱が発生してボンディングワイヤ２１がボンディングパッド１５ａに溶着する。このように、ボンディングワイヤ２１はホーン２４から超音波を加えられることによりボンディングパッド１５ａに電気的に接続される。   When performing the wire connecting step, first, as shown in FIG. 5, the substrate 12 is positioned and fixed by the clamp 27 on the base 26 of the ultrasonic welding apparatus 23, whereby the resonance of the substrate 12 at the time of ultrasonic welding is achieved. Is prevented. Next, as shown in FIG. 4B, the tip of the bonding wire 21 is pressed against the bonding pad 15a by the horn 24, and an ultrasonic wave is emitted from the horn 24 in this state. When an ultrasonic wave is emitted from the horn 24, the bonding wire 21 vibrates with respect to the semiconductor chip 15 fixed to the base 26 via the substrate 12, and frictional heat is generated by the vibration to bond the bonding wire 21. It is welded to the pad 15a. As described above, the bonding wire 21 is electrically connected to the bonding pad 15 a by applying ultrasonic waves from the horn 24.

半導体チップ１５とボンディングワイヤ２１との接続が終了すると、次いで、ボンディングワイヤ２１を超音波溶接により回路パターン１３のパッド部１３ａに電気的に接続する作業が行われる。つまり、図４（ｃ）に示すように、ボンディングワイヤ２１がホーン２４によりパッド部１３ａに押し付けられた状態でホーン２４から超音波が発せられ、その超音波によりパッド部１３ａに対してボンディングワイヤ２１が振動し、その振動による摩擦熱によりボンディングワイヤ２１がパッド部１３ａに溶着する。これにより、ボンディングワイヤ２１は超音波溶接により回路パターン１３のパッド部１３ａに電気的に接続され、ワイヤ接続工程が終了する。   When the connection between the semiconductor chip 15 and the bonding wire 21 is completed, an operation of electrically connecting the bonding wire 21 to the pad portion 13a of the circuit pattern 13 is then performed by ultrasonic welding. That is, as shown in FIG. 4C, an ultrasonic wave is emitted from the horn 24 in a state where the bonding wire 21 is pressed against the pad portion 13a by the horn 24, and the bonding wire 21 is applied to the pad portion 13a by the ultrasonic wave. Vibrates, and the bonding wire 21 is welded to the pad portion 13a by frictional heat due to the vibration. Thereby, the bonding wire 21 is electrically connected to the pad portion 13a of the circuit pattern 13 by ultrasonic welding, and the wire connection process is completed.

ここで、半導体固定工程において、半導体チップ１５は基板１２に設けられたスルーホール２２とボンディングパッド１５ａとが重複するのを避けるように基板１２に固定されているので、ワイヤ接続工程においてボンディングパッド１５ａにボンディングワイヤ２１を接続させるために、ボンディングパッド１５ａ上にホーン２４を配置しても、ホーン２４の直下にスルーホール２２が位置することはない。したがって、ホーン２４が発する超音波がスルーホール２２を介して基板１２の裏面側に逃げることが無く、ホーン２４が発する超音波を効率良くボンディングワイヤ２１に伝達して、ワイヤボンディングの確実性を高めることができる。また、スルーホール２２は、半導体チップ１５のボンディングパッド１５ａに対しては重複を避けるように配置されているが、半導体チップ１５の固定領域Ｔ、つまりヒートスプレッダ１６とは重複しているので、半導体チップ１５が発する熱はヒートスプレッダ１６を介して基板１２側へ伝達され、そこからスルーホール２２を介して基板１２の裏面側から外部に放熱されることになる。したがって、ボンディングパッド１５ａにボンディングワイヤ２１を接続するワイヤボンディングの確実性を高めるために、スルーホール２２をボンディングパッド１５ａとの重複を避ける位置に配置した場合であっても、半導体チップ１５の放熱性を確保することができる。   Here, in the semiconductor fixing step, the semiconductor chip 15 is fixed to the substrate 12 so as to avoid the overlapping of the through hole 22 provided in the substrate 12 and the bonding pad 15a. Therefore, in the wire connecting step, the bonding pad 15a. Even if the horn 24 is disposed on the bonding pad 15 a in order to connect the bonding wire 21 to the through hole 22, the through hole 22 is not located immediately below the horn 24. Therefore, the ultrasonic wave emitted from the horn 24 does not escape to the back side of the substrate 12 through the through hole 22, and the ultrasonic wave emitted from the horn 24 is efficiently transmitted to the bonding wire 21 to improve the reliability of wire bonding. be able to. Further, although the through hole 22 is disposed so as not to overlap the bonding pad 15a of the semiconductor chip 15, the through hole 22 overlaps with the fixed region T of the semiconductor chip 15, that is, the heat spreader 16, and therefore the semiconductor chip. The heat generated by 15 is transmitted to the substrate 12 side through the heat spreader 16, and is radiated from the back side of the substrate 12 to the outside through the through hole 22. Therefore, in order to improve the reliability of wire bonding in which the bonding wire 21 is connected to the bonding pad 15a, the heat dissipation of the semiconductor chip 15 is achieved even when the through hole 22 is disposed at a position avoiding overlapping with the bonding pad 15a. Can be secured.

このように、本発明によれば、基板１２に設けられるスルーホール２２は半導体チップ１５の固定領域Ｔ内であって、且つ、ボンディングパッド１５ａとの重複を避けた位置に配置されるので、ボンディングワイヤ２１をボンディングパッド１５ａに超音波溶接する際に、超音波がスルーホール２２を介して基板１２の裏側に逃げることを防止して、ワイヤボンディングの確実性を高めることができる。また、スルーホール２２は半導体チップ１５の固定領域Ｔ内に配置されるので、スルーホール２２をボンディングパッド１５ａとの重複を避ける位置に配置した場合であっても、半導体チップ１５の放熱性を確保することができる。   As described above, according to the present invention, the through hole 22 provided in the substrate 12 is disposed in the fixed region T of the semiconductor chip 15 and at a position avoiding the overlap with the bonding pad 15a. When ultrasonically welding the wire 21 to the bonding pad 15a, the ultrasonic wave can be prevented from escaping to the back side of the substrate 12 through the through hole 22, and the reliability of wire bonding can be improved. In addition, since the through hole 22 is disposed in the fixed region T of the semiconductor chip 15, the heat dissipation of the semiconductor chip 15 is ensured even when the through hole 22 is disposed at a position that avoids overlapping with the bonding pad 15a. can do.

また、本発明によれば、断面積の異なる複数種類のスルーホール２２を設けるようにしたので、半導体チップ１５の固定領域Ｔ内であって、且つ、ボンディングパッド１５ａと重複しない限られた範囲にスルーホール２２を設ける場合であっても、その範囲に多数のスルーホール２２を配置して、十分な放熱性を確保することができる。   In addition, according to the present invention, a plurality of types of through-holes 22 having different cross-sectional areas are provided, so that they are within a fixed region T of the semiconductor chip 15 and do not overlap with the bonding pads 15a. Even in the case where the through holes 22 are provided, a large number of through holes 22 can be arranged in the range to ensure sufficient heat dissipation.

さらに、本発明によれば、基板１２と半導体チップ１５との間に半導体チップ１５の固定領域Ｔを拡大するヒートスプレッダ１６を設けたので、スルーホール２２が設けられる範囲を拡大して、半導体チップ１５の放熱性をさらに高めることができる。   Furthermore, according to the present invention, since the heat spreader 16 that enlarges the fixing region T of the semiconductor chip 15 is provided between the substrate 12 and the semiconductor chip 15, the range in which the through hole 22 is provided is enlarged, and the semiconductor chip 15. The heat dissipation can be further enhanced.

さらに、本発明によれば、ヒートスプレッダ１６の熱膨張係数は基板１２の熱膨張係数と半導体チップ１５の熱膨張係数との中間の値を有するので、半導体チップ１５と基板１２の熱膨張率の相違により発生する応力をヒートスプレッダ１６により緩和して、半導体チップ１５のクラックの発生や基板１２からの離脱を防止することができる。   Furthermore, according to the present invention, since the thermal expansion coefficient of the heat spreader 16 has an intermediate value between the thermal expansion coefficient of the substrate 12 and the thermal expansion coefficient of the semiconductor chip 15, the difference between the thermal expansion coefficients of the semiconductor chip 15 and the substrate 12 is different. Can be relaxed by the heat spreader 16 to prevent the semiconductor chip 15 from being cracked or detached from the substrate 12.

図６は図１に示す半導体装置の変形例を示す断面図であり、図７は図６に示すスルーホールの詳細を示す拡大断面図である。なお、図６、図７において、前述した部材に対応する部材には同一の符号が付されている。   6 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 1, and FIG. 7 is an enlarged cross-sectional view showing details of the through hole shown in FIG. In FIGS. 6 and 7, members corresponding to those described above are denoted by the same reference numerals.

図１に示す半導体装置１１では、半導体チップ１５はヒートスプレッダ１６を介して基板１２上に固定されているが、図６に示す半導体装置３１では、半導体チップ１５は基板１２上に接着剤３２により直接固定されている。この場合、基板１２の半導体チップ１５が固定される固定領域Ｔは、図６に示すように半導体チップ１５の底面に対応する範囲となり、基板１２の厚み方向から見て、半導体チップ１５と重複し、且つ、ボンディングパッド１５ａとの重複を避ける位置にスルーホール２２が設けられる。したがって、半導体チップ１５のボンディングパッド１５ａにボンディングワイヤ２１を超音波溶接により接続するために、超音波溶接装置２３のホーン２４をボンディングパッド１５ａ上に配置しても、ホーン２４の直下にスルーホール２２が位置することはない。   In the semiconductor device 11 shown in FIG. 1, the semiconductor chip 15 is fixed on the substrate 12 via the heat spreader 16, but in the semiconductor device 31 shown in FIG. 6, the semiconductor chip 15 is directly on the substrate 12 by the adhesive 32. It is fixed. In this case, the fixed region T to which the semiconductor chip 15 of the substrate 12 is fixed is a range corresponding to the bottom surface of the semiconductor chip 15 as shown in FIG. 6 and overlaps with the semiconductor chip 15 when viewed from the thickness direction of the substrate 12. And the through hole 22 is provided in the position which avoids duplication with the bonding pad 15a. Accordingly, in order to connect the bonding wire 21 to the bonding pad 15a of the semiconductor chip 15 by ultrasonic welding, even if the horn 24 of the ultrasonic welding device 23 is disposed on the bonding pad 15a, the through hole 22 is directly below the horn 24. Is never located.

このように、この半導体装置３１においても、超音波溶接により半導体チップ１５のボンディングパッド１５ａにボンディングワイヤ２１を接続する際には、超音波溶接装置２３のホーン２４の直下にスルーホール２２が位置することがないので、ボンディングパッド１５ａとボンディングワイヤ２１とを超音波溶接により確実に接続することができる。   As described above, also in this semiconductor device 31, when the bonding wire 21 is connected to the bonding pad 15 a of the semiconductor chip 15 by ultrasonic welding, the through hole 22 is located immediately below the horn 24 of the ultrasonic welding device 23. Therefore, the bonding pad 15a and the bonding wire 21 can be reliably connected by ultrasonic welding.

一方、図７に示すように、この半導体装置３１に設けられるスルーホール２２の内面には銅や金などの導体がメッキされてメッキ層３３が形成されている。したがって、この半導体装置３１においては、半導体チップ１５が発する熱はスルーホール２２を介して放熱されるとともに、基板１２よりも熱伝達率の高い導体のメッキ層３３を介して積極的に外部に放熱されることになり、これにより、半導体チップ１５の放熱性が高められる。   On the other hand, as shown in FIG. 7, a plated layer 33 is formed by plating a conductor such as copper or gold on the inner surface of the through hole 22 provided in the semiconductor device 31. Therefore, in this semiconductor device 31, the heat generated by the semiconductor chip 15 is radiated through the through hole 22 and actively radiated to the outside through the plated layer 33 of the conductor having a higher heat transfer coefficient than the substrate 12. As a result, the heat dissipation of the semiconductor chip 15 is enhanced.

このように、本発明によれば、スルーホール２２の内面に導体をメッキするようにしたので、半導体チップ１５の放熱性を高めることができる。   As described above, according to the present invention, since the conductor is plated on the inner surface of the through hole 22, the heat dissipation of the semiconductor chip 15 can be improved.

本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。たとえば、図１に示す半導体装置１１においては、スルーホール２２は固定領域Ｔ内にのみ形成されているが、これに限らず、たとえば図６に示す半導体装置３１のように、固定領域Ｔ以外の部分にもスルーホール２２を設けるようにしてもよい。   It goes without saying that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. For example, in the semiconductor device 11 shown in FIG. 1, the through hole 22 is formed only in the fixed region T. However, the present invention is not limited to this. For example, as in the semiconductor device 31 shown in FIG. You may make it provide the through hole 22 also in a part.

また、本実施の形態においては、回路パターン１３は基板１２の表面にのみ形成されているが、これに限らず、たとえば基板１２の両面に回路パターンを形成し、あるいは基板１２としての多層基板を用いるようにしてもよい。これらの場合、スルーホール２２の内面に導体がメッキされることにより形成されるメッキ層３３により各層の回路パターンを電気的に接続するようにしてもよい。   In the present embodiment, the circuit pattern 13 is formed only on the surface of the substrate 12. However, the present invention is not limited to this. For example, a circuit pattern is formed on both surfaces of the substrate 12, or a multilayer substrate as the substrate 12 is formed. You may make it use. In these cases, the circuit patterns of the respective layers may be electrically connected by the plated layer 33 formed by plating a conductor on the inner surface of the through hole 22.

さらに、本実施の形態においては、熱誘導手段としてスルーホール２２を用い、その断面形状が円形に形成されているが、これに限らず、たとえば多角形状としても良い。また、これらスルーホール２２はその内部が空気層のものに限らず、たとえばスルーホール２２内を熱伝導率の高い物質で充填させても良い。   Furthermore, in the present embodiment, the through hole 22 is used as the heat induction means and the cross-sectional shape is formed in a circular shape. Further, the inside of these through holes 22 is not limited to that of an air layer, and for example, the inside of the through holes 22 may be filled with a material having high thermal conductivity.

さらに、本実施の形態においては、台座部材としてヒートスプレッダ１６が用いられているが、これに限らず、たとえば半導体チップ１５の底面に設けられる電極と基板１２上の回路パターン１３あるいはスルーホール２２の内壁に設けられるメッキ層３３等とを電気的に接続するダイパッドを用いるようにしてもよい。   Further, in the present embodiment, the heat spreader 16 is used as the pedestal member. However, the heat spreader 16 is not limited to this. For example, the electrode provided on the bottom surface of the semiconductor chip 15 and the inner wall of the circuit pattern 13 on the substrate 12 or the through hole 22. A die pad that electrically connects the plating layer 33 or the like provided on the substrate may be used.

本発明の一実施の形態である半導体装置の一部を示す上面図である。It is a top view which shows a part of semiconductor device which is one embodiment of this invention. 図１に示すＡ−Ａ線に沿う断面図である。It is sectional drawing which follows the AA line shown in FIG. 基板に形成され半導体チップの熱を基板の半導体チップが固定される面とは反対側の面へ誘導する熱誘導手段としてのスルーホールのレイアウトを示す上面図である。It is a top view which shows the layout of the through hole as a heat induction means which induces the heat | fever of the semiconductor chip formed in a board | substrate to the surface on the opposite side to the surface where the semiconductor chip of a board | substrate is fixed. （ａ）〜（ｃ）は図１に示す半導体装置の製造手順を示す断面図である。(A)-(c) is sectional drawing which shows the manufacture procedure of the semiconductor device shown in FIG. ワイヤ接続工程に用いられる超音波溶接装置の概略を示す側面図である。It is a side view which shows the outline of the ultrasonic welding apparatus used for a wire connection process. 図１に示す半導体装置の変形例を示す断面図である。FIG. 8 is a cross-sectional view showing a modification of the semiconductor device shown in FIG. 1. 図６に示すスルーホールの詳細を示す拡大断面図である。It is an expanded sectional view which shows the detail of the through hole shown in FIG.

符号の説明Explanation of symbols

１１ 半導体装置
１２ 基板
１３ 回路パターン
１３ａ パッド部
１４ 半導体実装領域
１５ 半導体チップ
１５ａ ボンディングパッド
１６ ヒートスプレッダ
１７，１８ 接着剤
２１ ボンディングワイヤ
２２ スルーホール
２３ 超音波溶接装置
２４ ホーン
２５ アーム
２６ ベース
２７ クランプ
３１ 半導体装置
３２ 接着剤
３３ メッキ層
Ｔ 固定領域
Ｒ 範囲 DESCRIPTION OF SYMBOLS 11 Semiconductor device 12 Board | substrate 13 Circuit pattern 13a Pad part 14 Semiconductor mounting area 15 Semiconductor chip 15a Bonding pad 16 Heat spreader 17, 18 Adhesive 21 Bonding wire 22 Through hole 23 Ultrasonic welding apparatus 24 Horn 25 Arm 26 Base 27 Clamp 31 Semiconductor device 32 Adhesive 33 Plating layer T Fixed area R Range

Claims (13)

配線パターンを備えた基板と、前記基板上に固定される半導体チップと、前記半導体チップの前記基板に固定される面とは反対側の面に設けられるボンディングパッドと前記配線パターンとに超音波溶接により電気的に接続されるボンディングワイヤとを有する半導体装置であって、
前記基板の前記半導体チップが固定される固定領域内であって、且つ、前記ボンディングパッドとの重複を避けた位置に、前記半導体チップの熱を前記基板の前記半導体チップが固定される面とは反対側の面へ誘導する熱誘導手段が設けられることを特徴とする半導体装置。 Ultrasonic welding to a substrate provided with a wiring pattern, a semiconductor chip fixed on the substrate, a bonding pad provided on a surface of the semiconductor chip opposite to the surface fixed to the substrate, and the wiring pattern A semiconductor device having a bonding wire electrically connected by
What is the surface of the substrate on which the semiconductor chip is fixed in a fixed region of the substrate where the semiconductor chip is fixed and avoids overlapping with the bonding pad. A semiconductor device comprising heat induction means for guiding to the opposite surface. 請求項１記載の半導体装置において、断面積の異なる複数種類の前記熱誘導手段を有することを特徴とする半導体装置。   2. The semiconductor device according to claim 1, comprising a plurality of types of heat induction means having different cross-sectional areas. 請求項１または２記載の半導体装置において、前記熱誘導手段は前記基板を貫通するスルーホールであることを特徴とする半導体装置。   3. The semiconductor device according to claim 1, wherein the heat induction means is a through hole penetrating the substrate. 請求項３記載の半導体装置において、前記スルーホールの内壁に導体がメッキされていることを特徴とする半導体装置。   4. The semiconductor device according to claim 3, wherein a conductor is plated on the inner wall of the through hole. 請求項１〜４のいずれか１項に記載の半導体装置において、導体により形成され前記基板と前記半導体チップとの間に配置されて前記固定領域を拡大する台座部材を有することを特徴とする半導体装置。   5. The semiconductor device according to claim 1, further comprising a base member that is formed of a conductor and is disposed between the substrate and the semiconductor chip and expands the fixed region. apparatus. 請求項５記載の半導体装置において、前記台座部材の熱膨張係数は前記基板の熱膨張係数と前記半導体チップの熱膨張係数との中間の値を有することを特徴とする半導体装置。   6. The semiconductor device according to claim 5, wherein a thermal expansion coefficient of the pedestal member has an intermediate value between a thermal expansion coefficient of the substrate and a thermal expansion coefficient of the semiconductor chip. 配線パターンを備えた基板と、前記基板上に固定される半導体チップと、前記半導体チップに設けられるボンディングパッドと前記配線パターンとを電気的に接続するボンディングワイヤとを有する半導体装置の製造方法であって、
前記基板に設けられ前記半導体チップの熱を前記基板の前記半導体チップが固定される面とは反対側の面へ誘導する熱誘導手段が前記半導体チップの固定領域内に位置し、且つ、前記熱誘導手段と前記ボンディングパッドとの重複を避けるように前記基板上に前記半導体チップを固定する半導体固定工程と、
前記配線パターンと前記ボンディングパッドとに超音波溶接により前記ボンディングワイヤを電気的に接続するワイヤ接続工程とを有することを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device, comprising: a substrate provided with a wiring pattern; a semiconductor chip fixed on the substrate; a bonding pad provided on the semiconductor chip; and a bonding wire that electrically connects the wiring pattern. And
Heat induction means provided on the substrate for guiding the heat of the semiconductor chip to a surface of the substrate opposite to the surface on which the semiconductor chip is fixed is located in the fixing region of the semiconductor chip, and the heat A semiconductor fixing step of fixing the semiconductor chip on the substrate so as to avoid duplication of the guiding means and the bonding pad;
A method of manufacturing a semiconductor device, comprising: a wire connection step of electrically connecting the bonding wire to the wiring pattern and the bonding pad by ultrasonic welding. 請求項７記載の半導体装置の製造方法において、断面積の異なる複数種類の前記熱誘導手段を有することを特徴とする半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, comprising a plurality of types of heat induction means having different cross-sectional areas. 請求項７または８記載の半導体装置の製造方法において、前記熱誘導手段は前記基板を貫通するスルーホールであることを特徴とする半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 7, wherein the heat induction means is a through hole penetrating the substrate. 請求項９記載の半導体装置の製造方法において、前記スルーホールの内壁に導体がメッキされていることを特徴とする半導体装置の製造方法。   10. The method of manufacturing a semiconductor device according to claim 9, wherein a conductor is plated on an inner wall of the through hole. 請求項７〜１０のいずれか１項に記載の半導体装置の製造方法において、前記ワイヤ接続工程を行う際に、超音波溶接装置上に前記基板を位置決め固定することを特徴とする半導体装置の製造方法。   11. The method of manufacturing a semiconductor device according to claim 7, wherein the substrate is positioned and fixed on an ultrasonic welding apparatus when performing the wire connecting step. Method. 請求項７〜１１のいずれか１項に記載の半導体装置の製造方法において、導体により形成され前記基板と前記半導体チップとの間に配置されて前記固定領域を拡大する台座部材を有することを特徴とする半導体装置の製造方法。   12. The method of manufacturing a semiconductor device according to claim 7, further comprising a base member that is formed of a conductor and is disposed between the substrate and the semiconductor chip and expands the fixed region. A method for manufacturing a semiconductor device. 請求項１２記載の半導体装置の製造方法において、前記台座部材の熱膨張係数は前記基板の熱膨張係数と前記半導体チップの熱膨張係数との中間の値を有することを特徴とする半導体装置の製造方法。   13. The method of manufacturing a semiconductor device according to claim 12, wherein a thermal expansion coefficient of the pedestal member has an intermediate value between a thermal expansion coefficient of the substrate and a thermal expansion coefficient of the semiconductor chip. Method.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011146547A (en) * 2010-01-15 2011-07-28 Murata Mfg Co Ltd Circuit module
JP2018119990A (en) * 2018-05-09 2018-08-02 日立オートモティブシステムズ株式会社 Thermal type flowmeter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011146547A (en) * 2010-01-15 2011-07-28 Murata Mfg Co Ltd Circuit module
JP2018119990A (en) * 2018-05-09 2018-08-02 日立オートモティブシステムズ株式会社 Thermal type flowmeter

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