JP6033011B2 - Power semiconductor device and method for manufacturing power semiconductor device - Google Patents

Power semiconductor device and method for manufacturing power semiconductor device Download PDF

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JP6033011B2
JP6033011B2 JP2012200237A JP2012200237A JP6033011B2 JP 6033011 B2 JP6033011 B2 JP 6033011B2 JP 2012200237 A JP2012200237 A JP 2012200237A JP 2012200237 A JP2012200237 A JP 2012200237A JP 6033011 B2 JP6033011 B2 JP 6033011B2
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electrode
power semiconductor
semiconductor element
bonding
buffer member
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JP2014056917A (en
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米田 裕
裕 米田
藤野 純司
純司 藤野
林 建一
建一 林
茂永 隆
隆 茂永
裕次 坂東
裕次 坂東
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Mitsubishi Electric Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)

Description

本発明は、電力用半導体装置に関し、とくに電力用半導体素子の電極に超音波接合により電極端子を接合した電力用半導体装置の構成およびその製造方法に関するものである。   The present invention relates to a power semiconductor device, and more particularly to a configuration of a power semiconductor device in which an electrode terminal is bonded to an electrode of a power semiconductor element by ultrasonic bonding and a manufacturing method thereof.

電力用半導体装置においては、電力用半導体素子に電流を流すために、電力用半導体素子表面の電極と電極端子間を接続するアルミのワイヤボンドが用いられてきた。しかし、ワイヤの線径には限りがあるので、電流に応じてワイヤの本数を増やす必要があるが、電力用半導体素子の小型大容量化にともない、電極に通電に必要なワイヤの本数を配線することが困難になってきた。そのため、電極端子を電極にはんだ接合することも考えられるが、はんだに対応するために電極表面の処理が必要であったり、運転温度の高温化にともない接合信頼性が低下したりするという問題があった。   In a power semiconductor device, an aluminum wire bond connecting an electrode on the surface of a power semiconductor element and an electrode terminal has been used in order to pass a current through the power semiconductor element. However, since the wire diameter is limited, it is necessary to increase the number of wires in accordance with the current. However, as the power semiconductor element becomes smaller and larger in capacity, the number of wires necessary to energize the electrodes is wired. It has become difficult to do. For this reason, it is conceivable to solder the electrode terminal to the electrode. However, there is a problem that the electrode surface needs to be treated in order to cope with the solder or that the bonding reliability decreases as the operating temperature increases. there were.

これらの問題を解決する方法として、電力用半導体素子の電極に、電極端子を直接超音波接合する方法が考えられる。これにより、電極の表面処理が不要で、高温にも対応可能となる。   As a method for solving these problems, a method in which an electrode terminal is directly ultrasonically bonded to an electrode of a power semiconductor element can be considered. Thereby, the surface treatment of an electrode is unnecessary and it can respond also to high temperature.

しかし、超音波接合は、被接合材料を超音波ホーンで加圧しながら超音波振動させることにより、接合界面に形成されている酸化膜や付着している汚れを除去し、新生面同士を密着させて接合層を形成する技術である。そのため、接合される材料の種類が異なると、硬度が低い方の材料が一方的に塑性変形するため、必要な接合強度が得られないことが考えられる。一方、一般的な電力用半導体装置に用いられる電力用半導体素子の表面電極にはアルミが、電極端子には銅というように硬度の異なる材料が用いられる。そこで、硬度の高い材料の表面にその材料よりも硬度の低い材料を被覆することで、硬度の異なる材料の接合強度を高める技術(例えば、特許文献1または2参照。)を電極端子の接合に応用することが考えられる。   However, ultrasonic bonding is performed by ultrasonically vibrating the material to be bonded with an ultrasonic horn to remove the oxide film formed on the bonding interface and adhering dirt and bringing the new surfaces into close contact with each other. This is a technique for forming a bonding layer. For this reason, if the types of materials to be joined are different, the material having the lower hardness is unilaterally plastically deformed, so that it is possible that the necessary joining strength cannot be obtained. On the other hand, materials having different hardnesses such as aluminum are used for the surface electrode of the power semiconductor element used in a general power semiconductor device and copper is used for the electrode terminal. Therefore, a technique (for example, see Patent Document 1 or 2) for increasing the bonding strength of materials having different hardnesses by coating the surface of a material having a high hardness with a material having a lower hardness than that material for bonding electrode terminals. It can be applied.

特開昭60−206054号公報(頁273左上欄〜頁273左下欄)JP-A-60-206054 (Page 273, upper left column to page 273, lower left column) 特開平8−252679号公報(段落0014〜0016、図1〜図2)JP-A-8-252679 (paragraphs 0014 to 0016, FIGS. 1 to 2)

しかしながら、上述した技術は、被接合材料間の硬度の違いが大きすぎる場合、あるいは、アルミワイヤを硬い材料に接合する際の超音波ホーンと接触する部材の硬度が低い場合に対応する技術である。そのため、硬度の高い被接合材料には、硬度の低い被接合材料の硬度よりも高い硬度を有する材料が被覆されており、硬度の低い側の部材の損傷については考慮されていない。したがって、上述した技術を、そのまま電力用半導体素子の電極と電極端子の接合に応用すると、土台側となる電力用半導体素子の電極側に形成されたトランジスタや電力用半導体素子自体が破壊される可能性があり、信頼性の高い電力用半導体装置を得ることが困難となる。   However, the above-described technique is a technique corresponding to a case where the difference in hardness between the materials to be bonded is too large, or a case where the hardness of the member that comes into contact with the ultrasonic horn when the aluminum wire is bonded to a hard material is low. . Therefore, the material having high hardness is coated with a material having a hardness higher than that of the material having low hardness, and damage to the member on the lower hardness side is not considered. Therefore, if the above-described technique is applied as it is to the junction between the electrode of the power semiconductor element and the electrode terminal, the transistor formed on the electrode side of the power semiconductor element on the base side or the power semiconductor element itself may be destroyed. It is difficult to obtain a power semiconductor device with high reliability.

この発明は、上記のような問題点を解決するためになされたものであり、大電流に対応し、信頼性の高い電力用半導体装置を得ることを目的としている。   The present invention has been made to solve the above-described problems, and an object thereof is to obtain a highly reliable power semiconductor device that can handle a large current.

本発明にかかる電力用半導体装置は、一方の面に回路面が形成された回路基板と、前記回路基板の回路面側に裏面が接合され、表面に電極が形成された電力用半導体素子と、前記電力用半導体素子の電極の主構成材料よりも高い耐力を有する材料で構成されるとともに、一端に前記電力用半導体素子の電極と対向する接合面が形成され、前記接合面が緩衝部材を介して前記電力用半導体素子の電極と超音波接合された電極端子と、を備え、前記緩衝部材は、少なくとも前記電力用半導体素子の電極に接触する部分の材料が、前記電力用半導体素子の電極の主構成材料と同等以下の耐力を有し、前記接合面および前記電力用半導体素子の電極は、離間した状態で、前記緩衝部材を介して前記接合面および前電力用半導体素子の電極との間にそれぞれ接合層を有することを特徴とする。
本発明にかかる電力用半導体装置の製造方法は、電力用半導体素子の裏面が回路面に接合された回路基板を超音波接合装置に固定する工程と、電力用半導体素子の電極に、少なくとも前記電力用半導体素子の電極に接触する部分の材料が前記電力用半導体素子の電極の主構成材料と同等以下の耐力を有する緩衝部材と前記電力用半導体素子の電極の主構成材料よりも高い耐力を有する材料で構成される電極端子とを順次積層する工程と、前記電極端子の接合面の反対側から前記超音波接合装置のホーンを当て、前記電力用半導体素子の電極と前記電極端子とを前記緩衝部材を介して超音波接合する工程と、を含み、前記超音波接合する工程が行われる前の前記緩衝部材の厚みは、前記電力用半導体素子の電極よりも厚く、前記電極端子より薄く、前記超音波接合する工程は、前記接合面および前記電力用半導体素子の電極が、離間した状態で、前記緩衝部材を介して前記接合面および前記電力用半導体素子の電極との間にそれぞれ接合層を形成することを特徴とする。
また、電力用半導体素子の電極および前記電力用半導体素子の電極の主構成材料よりも高い耐力を有する材料で構成される電極端子の接合面の少なくとも一方の表面に少なくとも前記電力用半導体素子の電極に接触する部分の材料が前記電力用半導体素子の電極の主構成材料と同等以下の耐力を有する緩衝部材を形成する工程と、前記電力用半導体素子の裏面が回路面に接合された回路基板を超音波接合装置に固定する工程と、前記電力用半導体素子の電極に前記電極端子を重ねる工程と、前記電極端子の接合面の反対側から前記超音波接合装置のホーンを当て、前記電力用半導体素子の電極と前記電極端子とを前記緩衝部材を介して超音波接合する工程と、を含み、前記超音波接合する工程が行われる前の前記緩衝部材の厚みは、前記電力用半導体素子の電極よりも厚く、前記電極端子より薄く、前記超音波接合する工程は、前記接合面および前記電力用半導体素子の電極が、離間した状態で、前記緩衝部材を介して前記接合面および前記電力用半導体素子の電極との間にそれぞれ接合層を形成することを特徴とする。
A power semiconductor device according to the present invention includes a circuit board having a circuit surface formed on one surface, a power semiconductor element having a back surface bonded to the circuit surface side of the circuit board, and an electrode formed on the surface, The power semiconductor element is made of a material having a higher proof strength than the main constituent material of the electrode, and a joint surface facing the electrode of the power semiconductor element is formed at one end, and the joint surface is interposed through a buffer member. An electrode terminal that is ultrasonically bonded to the electrode of the power semiconductor element, and the buffer member has at least a portion of the material in contact with the electrode of the power semiconductor element of the electrode of the power semiconductor element. It has a proof strength equal to or less than that of the main constituent material, and the bonding surface and the electrode of the power semiconductor element are spaced apart from each other between the bonding surface and the electrode of the front power semiconductor element via the buffer member. To it It is characterized by having a bonding layer.
A method for manufacturing a power semiconductor device according to the present invention includes a step of fixing a circuit board having a back surface of a power semiconductor element bonded to a circuit surface to an ultrasonic bonding apparatus, and an electrode of the power semiconductor element. The material of the portion in contact with the electrode of the semiconductor element for power use has a higher strength than the main constituent material of the electrode of the power semiconductor element and the buffer member having a proof strength equal to or less than the main constituent material of the electrode of the power semiconductor element A step of sequentially stacking electrode terminals made of a material, a horn of the ultrasonic bonding apparatus from the opposite side of the bonding surface of the electrode terminals, and the buffer of the electrode of the power semiconductor element and the electrode terminal It includes a step of ultrasonic bonding through the member, wherein the thickness of the buffer member before the step of bonding ultrasound is performed is thicker than the electrode of the power semiconductor device, the thin from the electrode terminal In the ultrasonic bonding step, the bonding surface and the electrode of the power semiconductor element are bonded to each other between the bonding surface and the electrode of the power semiconductor element via the buffer member in a state where the bonding surface and the electrode of the power semiconductor element are separated from each other. A layer is formed .
Further, at least one electrode of the power semiconductor element is formed on at least one surface of the bonding surface of the electrode terminal composed of a material having higher proof strength than the main constituent material of the electrode of the power semiconductor element and the electrode of the power semiconductor element. Forming a buffer member having a proof strength equal to or less than that of the main component material of the electrode of the power semiconductor element, and a circuit board in which the back surface of the power semiconductor element is bonded to the circuit surface. A step of fixing to the ultrasonic bonding apparatus; a step of overlapping the electrode terminal on the electrode of the power semiconductor element; and a horn of the ultrasonic bonding apparatus from the opposite side of the bonding surface of the electrode terminal, Ultrasonically bonding the electrode of the element and the electrode terminal via the buffer member, and the thickness of the buffer member before the ultrasonic bonding step is performed Thicker than the electrode of the semiconductor element, the electrode rather thin from the terminal, the step of joining ultrasound, electrodes of the joining surface and the power semiconductor element, in a spaced apart condition, the bonding surface via the cushioning member And a bonding layer formed between each of the electrodes of the power semiconductor element .

この発明によれば、電力用半導体素子に損傷を与えることなく、電極端子をしっかりと電力用半導体素子に接合できるので、大電流に対応し、信頼性の高い電力用半導体装置を得ることができる。   According to the present invention, since the electrode terminal can be firmly joined to the power semiconductor element without damaging the power semiconductor element, a highly reliable power semiconductor device corresponding to a large current can be obtained. .

本発明の実施の形態1にかかる電力用半導体装置の構成を説明するための部分断面図である。It is a fragmentary sectional view for demonstrating the structure of the power semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態1にかかる電力用半導体装置の製造方法を説明するための、電力用半導体素子と電極端子との接合部分の各工程における断面図である。It is sectional drawing in each process of the junction part of the power semiconductor element and electrode terminal for demonstrating the manufacturing method of the power semiconductor device concerning Embodiment 1 of this invention. 比較例の電力用半導体装置の構成を説明するための部分断面図である。It is a fragmentary sectional view for demonstrating the structure of the power semiconductor device of a comparative example. 比較例の電力用半導体装置の製造方法を説明するための、電力用半導体素子と電極端子との接合部分の各工程における断面図である。It is sectional drawing in each process of the junction part of the power semiconductor element and electrode terminal for demonstrating the manufacturing method of the power semiconductor device of a comparative example. 本発明の実施の形態2にかかる電力用半導体装置の構成を説明するための部分断面図である。It is a fragmentary sectional view for demonstrating the structure of the power semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態2にかかる電力用半導体装置の製造方法を説明するための、電力用半導体素子と電極端子との接合部分の各工程における断面図である。It is sectional drawing in each process of the junction part of the power semiconductor element and electrode terminal for demonstrating the manufacturing method of the power semiconductor device concerning Embodiment 2 of this invention.

実施の形態1.
図1と図2は、本発明の実施の形態1にかかる電力用半導体装置の構成を説明するための図である。図1は電力用半導体装置の部分断面図、図2は電力用半導体素子と電極端子との接合部分の各工程における部分断面図で、図2(a)は電力用半導体素子に接合対象の電極端子を載置した状態、図2(b)は超音波ホーンを用いて接合を進行させている途中の状態、図2(c)は超音波接合が完了した時の状態である。また、図3と図4は比較例の電力用半導体装置の構成を説明するためのもので、それぞれ本実施の形態1にかかる電力用半導体装置の説明に用いる図1と図2に対応する。
Embodiment 1 FIG.
1 and 2 are diagrams for explaining the configuration of the power semiconductor device according to the first embodiment of the present invention. 1 is a partial cross-sectional view of a power semiconductor device, FIG. 2 is a partial cross-sectional view in each step of a joint portion between a power semiconductor element and an electrode terminal, and FIG. 2A is an electrode to be joined to the power semiconductor element. FIG. 2B shows a state in which the terminal is placed, FIG. 2B shows a state in the middle of joining using an ultrasonic horn, and FIG. 2C shows a state when the ultrasonic joining is completed. FIGS. 3 and 4 are for explaining the configuration of the power semiconductor device of the comparative example, and correspond to FIGS. 1 and 2 used for explaining the power semiconductor device according to the first embodiment, respectively.

なお、本実施の形態および他の実施の形態に用いる図において、同一または同様の構成部分については同じ符号を付している。それぞれの図では、対応する各構成部のサイズや縮尺は独立しており、例えば構成の一部を変更した断面図の間で、変更されていない同一構成部分の図示において、同一構成部分のサイズや縮尺が異なっている場合もある。また、電力用半導体装置の構成は、実際にはさらに複数の部材を備えているが、説明を簡単にするため、説明に必要な部分のみを記載し、他の部分については省略している(例えば他の配線部材や、ケース等)。   Note that in the drawings used in this embodiment and other embodiments, the same or similar components are denoted by the same reference numerals. In each of the drawings, the size and scale of each corresponding component are independent. For example, in the cross-sectional view in which a part of the configuration is changed, in the illustration of the same component that is not changed, the size of the same component And the scale may be different. In addition, although the configuration of the power semiconductor device actually includes a plurality of members, only the portions necessary for the description are shown and the other portions are omitted for the sake of simplicity. For example, other wiring members or cases).

図1に示すように、本発明の実施の形態1にかかる電力用半導体装置100では、絶縁基材51の両側に回路パターン52a、52bが形成された回路基板5には、放熱面側(回路パターン52b側)に放熱部材6がはんだ8によって接合され、回路面側(回路パターン52a側)には、電力用半導体素子であるIGBT1(Insulated Gate Bipolar Transistor)の裏面がはんだ7により接合されている。そして、IGBT1の表面に形成された表面電極2には、緩衝部材4を介して電極端子3が超音波接合されている。以下、詳細に説明する。   As shown in FIG. 1, in the power semiconductor device 100 according to the first embodiment of the present invention, the circuit board 5 on which the circuit patterns 52a and 52b are formed on both sides of the insulating base 51 has a heat radiation surface side (circuit The heat dissipating member 6 is joined to the pattern 52b side) by the solder 8, and the back surface of an IGBT 1 (Insulated Gate Bipolar Transistor), which is a power semiconductor element, is joined to the circuit surface side (circuit pattern 52a side) by the solder 7. . The electrode terminal 3 is ultrasonically bonded to the surface electrode 2 formed on the surface of the IGBT 1 via the buffer member 4. Details will be described below.

IGBT1の表面電極2の下には、複数のトランジスタ11が形成されている。なお、IGBT1は縦型半導体素子であり、表面側だけではなく、裏面側にも電極(裏面電極12)が形成されている。しかし、本発明が解決すべき課題は、表面電極2側での損傷の抑制なので、裏面電極12側の構造は簡略化して、図では、回路基板5の回路パターン52aにはんだ7により接合されていることのみを表現している。   A plurality of transistors 11 are formed under the surface electrode 2 of the IGBT 1. The IGBT 1 is a vertical semiconductor element, and an electrode (back surface electrode 12) is formed not only on the front surface side but also on the back surface side. However, since the problem to be solved by the present invention is to suppress damage on the front electrode 2 side, the structure on the back electrode 12 side is simplified, and the circuit pattern 52a of the circuit board 5 is joined to the circuit pattern 52a by the solder 7 in the figure. It expresses only that

IGBT1は、インバータやコンバータ等を構成する電力用半導体素子である。本実施の形態にかかる電力用半導体装置100は、少なくとも1個以上の電力用半導体素子によって構成されていればよいが、IGBTもしくはMOSFET(Metal Oxide Semiconductor Field Effect Transistor)がダイオードと逆並列に接続されていることが好ましい。IGBT1の材料には、シリコン(Si)や炭化珪素(SiC)、窒化ガリウム(GaN)系材料等が用いられるが、Siと比較して、SiC、GaN系材料、ダイヤモンド等のワイドバンドギャップ半導体材料と呼ばれる材料を用いた素子の方が定格電流に対する表面電極2の面積が小さい。そのため、ワイドバンドギャップ半導体材料を用いた電力用半導体素子の方が、Siの場合と比較して、より高密度の配線技術が求められる。   The IGBT 1 is a power semiconductor element that constitutes an inverter, a converter, and the like. The power semiconductor device 100 according to the present embodiment only needs to be configured by at least one power semiconductor element, but an IGBT or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is connected in reverse parallel to the diode. It is preferable. The material of the IGBT 1 is silicon (Si), silicon carbide (SiC), gallium nitride (GaN) -based material, etc., but wide band gap semiconductor materials such as SiC, GaN-based material, and diamond compared to Si The area using the surface electrode 2 with respect to the rated current is smaller in the element using the material called. Therefore, a power semiconductor element using a wide band gap semiconductor material is required to have a higher-density wiring technique than Si.

そこで、ワイドバンドギャップ半導体材料として、例えばSiCを用いた電力用半導体装置100においては、表面電極2に電極端子3を超音波接合することで、一度に大面積を接合する本発明のメリットがより顕著に顕れる。一方、IGBT1の材料に、一般的なSiを用いた場合でも、定格電流が100A以上の場合や、素子の大きさが10mm×10mm以上の場合に、ワイヤボンドと比較して素子1枚に要するタクトタイムを短く出来、本発明のメリットがより効果的なものとなるため好ましい。また、素子の厚さが厚いほど、超音波接合時における加圧と超音波振動によってチップ自体が割れ難くなるため、IGBT1の厚さは0.1mm以上であるのが好ましい。   Therefore, in the power semiconductor device 100 using, for example, SiC as a wide band gap semiconductor material, the advantages of the present invention in which a large area is bonded at a time by ultrasonically bonding the electrode terminal 3 to the surface electrode 2 are more advantageous. Prominently appear. On the other hand, even when general Si is used as the material of the IGBT 1, one element is required compared to the wire bond when the rated current is 100 A or more or when the element size is 10 mm × 10 mm or more. It is preferable because the tact time can be shortened and the merit of the present invention becomes more effective. In addition, as the thickness of the element increases, the chip itself is less likely to break due to pressurization and ultrasonic vibration during ultrasonic bonding. Therefore, the thickness of the IGBT 1 is preferably 0.1 mm or more.

表面電極2はIGBT1の表面に形成された電極配線用の金属膜である。表面電極2の材料には一般的にはアルミニウム(Al)が用いられるが、AlSiやAlCuのようなAl合金や、Cu、Cu合金等であればAlと比較して表面電極2の硬度が高くなって超音波接合時に変形し難くなる。その場合、緩衝部材4に、表面電極2の主構成材料と同じアルミニウムを用いても、後述するように緩衝部材4の方が、表面電極2より優先的に変形するため、本発明による損傷対策の効果を発揮することができる。   The surface electrode 2 is a metal film for electrode wiring formed on the surface of the IGBT 1. Generally, aluminum (Al) is used as the material of the surface electrode 2, but the hardness of the surface electrode 2 is higher than that of Al if Al alloy such as AlSi or AlCu, Cu, Cu alloy or the like is used. It becomes difficult to be deformed during ultrasonic bonding. In that case, even if the same aluminum as the main constituent material of the surface electrode 2 is used for the buffer member 4, the buffer member 4 is deformed preferentially over the surface electrode 2 as will be described later. The effect of can be demonstrated.

なお、表面電極2は、例えば下地層となるアルミニウムの上部に、Ti、Mo、Ni、Au等の金属被覆層が形成されていることもある。この場合でも、これらの被覆層の厚さが下地層の厚さに比べて薄い場合、被覆層は下地層の動きに連動して、超音波接合時に周囲に排斥される。そのため、これらの被覆層の厚さが下地層の厚さの50%より薄い場合は、表面電極2は、被覆層の硬さに関わらず、下地層(アルミニウム)の硬さに応じた挙動を示すことになる。   In addition, the surface electrode 2 may have a metal coating layer such as Ti, Mo, Ni, Au, or the like formed on, for example, an aluminum layer serving as a base layer. Even in this case, when the thickness of these coating layers is smaller than the thickness of the underlayer, the overcoat layer is displaced to the surroundings during ultrasonic bonding in conjunction with the movement of the underlayer. Therefore, when the thickness of these coating layers is less than 50% of the thickness of the foundation layer, the surface electrode 2 behaves according to the hardness of the foundation layer (aluminum) regardless of the hardness of the coating layer. Will show.

超音波接合時の表面電極2の変形が大きいと、表面電極2の下層に形成されているトランジスタ11にまで影響が及ぶことがある。そのため、接合時のトランジスタ11の損傷(破壊)を抑制するために、表面電極2の厚さは、厚いほどよく、0.07mm以上であるのが好ましい。   If the deformation of the surface electrode 2 during ultrasonic bonding is large, the transistor 11 formed under the surface electrode 2 may be affected. Therefore, in order to suppress damage (destruction) of the transistor 11 at the time of bonding, the thickness of the surface electrode 2 is preferably as thick as possible, and is preferably 0.07 mm or more.

電極端子3はIGBT1の表面電極2と外部回路とを電気接続するための配線部材である。電極端子3の材料は電気抵抗の小さい金属が好ましく、一般的にはCuやAl等の板材をプレス加工したものが用いられ、一端に表面電極2との接合面3jが形成され、他端側は他の回路部材や外部回路と電気接続される。そのため、それ自体で形状を維持できるよう剛性を有する材料が用いられ、同じアルミニウム系の材料であっても表面電極2よりは硬い材料が用いられることが多い。通電可能な電流を大きくするためには、電極端子3の断面積が大きな方が好ましいが、超音波接合時に印加されたパワーを接合対象(本実施の形態では緩衝部材4、表面電極2)に伝わり易くするには厚さが薄い方が好ましい。そのため、電極端子3を構成する板材、あるいは、少なくとも表面電極2と対向する接合面3j部分の厚みは0.1mm〜1.0mm、幅は1.0mm〜5.0mm程度が好ましい。   The electrode terminal 3 is a wiring member for electrically connecting the surface electrode 2 of the IGBT 1 and an external circuit. The material of the electrode terminal 3 is preferably a metal having a low electrical resistance, and generally a material obtained by pressing a plate material such as Cu or Al is used. A joining surface 3j with the surface electrode 2 is formed at one end, and the other end side. Are electrically connected to other circuit members and external circuits. Therefore, a material having rigidity is used so that the shape itself can be maintained, and a material harder than the surface electrode 2 is often used even if it is the same aluminum-based material. In order to increase the current that can be energized, it is preferable that the electrode terminal 3 has a large cross-sectional area, but the power applied during ultrasonic bonding is applied to the object to be bonded (in this embodiment, the buffer member 4 and the surface electrode 2). In order to be easily transmitted, it is preferable that the thickness is small. Therefore, it is preferable that the plate material constituting the electrode terminal 3 or at least the joining surface 3j portion facing the surface electrode 2 has a thickness of about 0.1 mm to 1.0 mm and a width of about 1.0 mm to 5.0 mm.

緩衝部材4は、超音波接合時に表面電極2や電極端子3より優先的に変形し、表面電極2、電極端子3のそれぞれと超音波接合される。緩衝部材4は通電可能な材料であれば良いが、超音波接合時に加わる加圧や振動によって、表面電極2や電極端子3より優先的に変形しなければならない。そのため、両被接合材(表面電極2と電極端子3)のうち、硬度が低い材料(表面電極2)と同等以下の硬度を有する材料である必要がある。なお、硬度の違いは、一般的にはビッカース硬度等の違いで規定することが多いが、超音波接合時において変形が容易か否かは、塑性ひずみを生じやすいか否か、つまり耐力で規定する方が適している。また、上述したように、超音波接合時の表面電極2の挙動は、最表面の被覆層の状態よりも、厚みの半分以上を占める下地の状態が反映される。したがって、緩衝部材4の特性としては、主構成材料が、表面電極2と同等以下の耐力(0.2%耐力)を有するとして規定する。これにより、表面電極2および電極端子3よりも先に緩衝部材4で塑性ひずみ(変形)を生じさせることができる。   The buffer member 4 is deformed preferentially over the surface electrode 2 and the electrode terminal 3 during ultrasonic bonding, and is ultrasonically bonded to each of the surface electrode 2 and the electrode terminal 3. The buffer member 4 may be any material that can be energized, but must be preferentially deformed over the surface electrode 2 and the electrode terminal 3 by pressure and vibration applied during ultrasonic bonding. Therefore, it is necessary that the material to be joined (surface electrode 2 and electrode terminal 3) has a hardness equal to or lower than that of the material having low hardness (surface electrode 2). In general, the difference in hardness is often specified by the difference in Vickers hardness, etc., but whether or not deformation is easy during ultrasonic bonding is determined by whether or not plastic strain is likely to occur, that is, by yield strength. It is better to do. In addition, as described above, the behavior of the surface electrode 2 during ultrasonic bonding reflects the state of the base occupying more than half of the thickness than the state of the outermost coating layer. Therefore, the characteristic of the buffer member 4 is defined as that the main constituent material has a yield strength (0.2% yield strength) equal to or less than that of the surface electrode 2. Thereby, plastic strain (deformation) can be generated in the buffer member 4 before the surface electrode 2 and the electrode terminal 3.

なお、ここで言う耐力は、材料試験において、明確な降伏点をもたない材料に対して降伏強さを規定するために用いられるもので、0.2%の影響ひずみが発生する応力(0.2%耐力)である。   Note that the proof stress referred to here is used to define the yield strength of a material having no clear yield point in a material test, and is a stress (0) that causes an influence strain of 0.2%. .2% yield strength).

例えば、表面電極2に純Al(耐力:30〜150MPa、Hv:10〜50)、電極端子3に無酸素銅(耐力:200〜355MPa、Hv:50〜120)を用いた場合、緩衝部材4の材料には純Al(耐力:30〜150MPa、Hv:10〜50)以下の耐力を有する材料を選定する。   For example, when pure Al (proof strength: 30 to 150 MPa, Hv: 10 to 50) is used for the surface electrode 2 and oxygen-free copper (proof strength: 200 to 355 MPa, Hv: 50 to 120) is used for the electrode terminal 3, the buffer member 4 is used. As the material, a material having a proof strength of pure Al (proof strength: 30 to 150 MPa, Hv: 10 to 50) or less is selected.

また、超音波接合時に加わる加圧と振動によって、緩衝部材4は薄く変形するが、変形しすぎて表面電極2と電極端子3との間から排斥されないように、緩衝部材4の厚さは超音波接合による変形量を考慮して適切な値に設定する必要がある。具体的には、表面電極2の厚さより厚くすることが好ましい。一方、緩衝部材4の厚さを厚くしすぎると、超音波接合時に印加されたパワーが表面電極2と緩衝部材4との接触面まで伝わらず、十分な接合面積が得られない可能性がある。そのため緩衝部材4の厚みは、0.05mm〜0.5mm程度の範囲内でかつ、電極端子3の厚さより薄くすることが好ましい。   In addition, the buffer member 4 is thinly deformed by pressurization and vibration applied during ultrasonic bonding, but the buffer member 4 is too thick so as not to be deformed and discharged from between the surface electrode 2 and the electrode terminal 3. It is necessary to set to an appropriate value in consideration of the amount of deformation by sonic bonding. Specifically, it is preferable to make it thicker than the thickness of the surface electrode 2. On the other hand, if the thickness of the buffer member 4 is too thick, the power applied at the time of ultrasonic bonding is not transmitted to the contact surface between the surface electrode 2 and the buffer member 4, and a sufficient bonding area may not be obtained. . Therefore, the thickness of the buffer member 4 is preferably in the range of about 0.05 mm to 0.5 mm and thinner than the thickness of the electrode terminal 3.

また、緩衝部材4はバイメタルや事前に電極端子3に超音波接合しておくことで、接合工程の前に電極端子3と一体化していてもかまわない。ここで、緩衝部材4は表面電極2、および電極端子3と同じ材料(同等以下の耐力)でも同様の効果を得ることができるため、例えば、本実施の形態1の電極端子3の材料がAlであっても同様の効果を得ることができる。なお、バイメタルのように面によって耐力が異なる場合、例えば、表面電極2(Al)側はアルミニウム、電極端子3(Cu)側は銅材というように、少なくとも表面電極2に対向する部分の耐力が表面電極2の耐力以下になるように構成すればよい。   Further, the buffer member 4 may be integrated with the electrode terminal 3 before the bonding step by ultrasonic bonding to the electrode terminal 3 in advance by bimetal. Here, since the buffer member 4 can obtain the same effect even with the same material (equivalent or less proof stress) as the surface electrode 2 and the electrode terminal 3, for example, the material of the electrode terminal 3 of the first embodiment is Al. However, the same effect can be obtained. When the proof stress differs depending on the surface, such as bimetal, the proof strength of at least the portion facing the surface electrode 2 is, for example, aluminum on the surface electrode 2 (Al) side and copper material on the electrode terminal 3 (Cu) side. What is necessary is just to comprise so that it may become below the yield strength of the surface electrode 2. FIG.

つぎに、このように構成した電力用半導体装置100の効果と製造方法について、図2の工程毎の接合部分近傍の断面図を用いて説明する。   Next, the effect and the manufacturing method of the power semiconductor device 100 configured as described above will be described with reference to a cross-sectional view in the vicinity of a joint portion for each step of FIG.

はじめに、図2(a)に示すように、IGBT1の表面電極2上に緩衝部材4と電極端子3を載置する。この時、IGBT1を実装した回路基板5全体が超音波接合装置に固定されているが、図ではIGBT1と電極端子3部分のみを記載している。そして、電極端子3の上面3zの所定位置に先端が接触するように、超音波ホーン50を下降(z方向)させる。   First, as shown in FIG. 2A, the buffer member 4 and the electrode terminal 3 are placed on the surface electrode 2 of the IGBT 1. At this time, the entire circuit board 5 on which the IGBT 1 is mounted is fixed to the ultrasonic bonding apparatus, but only the IGBT 1 and the electrode terminal 3 are shown in the figure. Then, the ultrasonic horn 50 is lowered (z direction) so that the tip contacts a predetermined position on the upper surface 3z of the electrode terminal 3.

つぎに、図2(b)に示すように、超音波ホーン50を電極端子3に対して加圧し、更に、矢印の方向(xy面内)に超音波振動させる。このときの周波数は、例えば、数10KHzであり、振動させながら超音波ホーン50を降下させていく。これにより、表面電極2と緩衝部材4、および電極端子3と緩衝部材4との接触面同士が摺れて、接触面を覆っている酸化膜等の、接合を阻害する膜等が除去される。電極端子3の上面3z部分には超音波ホーン50の突起部が食い込んでいる。緩衝部材4は、超音波ホーン50による加圧と超音波振動によって、主に振動方向(xy)に引き伸ばされ、特に超音波ホーン50の突起部の下は薄く変形する。   Next, as shown in FIG. 2B, the ultrasonic horn 50 is pressurized against the electrode terminal 3 and further ultrasonically vibrated in the direction of the arrow (in the xy plane). The frequency at this time is, for example, several tens KHz, and the ultrasonic horn 50 is lowered while being vibrated. As a result, the contact surfaces of the surface electrode 2 and the buffer member 4 and the electrode terminals 3 and the buffer member 4 are slid to remove a film or the like that inhibits bonding, such as an oxide film covering the contact surface. . The protruding portion of the ultrasonic horn 50 bites into the upper surface 3z portion of the electrode terminal 3. The buffer member 4 is stretched mainly in the vibration direction (xy) by the pressurization and ultrasonic vibration by the ultrasonic horn 50, and in particular, the portion below the protrusion of the ultrasonic horn 50 is thinly deformed.

最終的には、図2(c)に示すように、表面電極2と緩衝部材4、および電極端子3と緩衝部材4とは、超音波振動により接触面同士が接合され、強固な接合層J2−4、J3−4が形成される。このとき、緩衝部材4は更に変形が進み、薄く引き延ばされた状態となっているが、表面電極2は変形していないため、トランジスタ11が破壊されることはない。 Finally, as shown in FIG. 2 (c), the surface electrode 2 and the buffer member 4, and the electrode terminal 3 and the buffer member 4 are bonded to each other by ultrasonic vibration so that the strong bonding layer J 2-4 , J 3-4 are formed. At this time, the buffer member 4 is further deformed and thinly stretched, but since the surface electrode 2 is not deformed, the transistor 11 is not destroyed.

このように構成した電力用半導体装置100を動作させると、IGBT1に電流が流れて発熱する。このとき、IGBT1の表面電極2と電極端子3とは緩衝部材4を介して強固に接合されているとともに、表面電極2下部に形成されたトランジスタ11は、いずれも損傷を受けずに正常に動作することができる。そのため、IGBT1は効率よく動作するとともに、配線部材や接合不良による余計な電力ロスもない。その結果、電力ロスによる発熱も少なく、安定した動作が可能になる。   When the power semiconductor device 100 configured as described above is operated, a current flows through the IGBT 1 to generate heat. At this time, the surface electrode 2 and the electrode terminal 3 of the IGBT 1 are firmly joined via the buffer member 4, and the transistor 11 formed below the surface electrode 2 operates normally without being damaged. can do. Therefore, the IGBT 1 operates efficiently, and there is no extra power loss due to wiring members or poor bonding. As a result, heat generation due to power loss is small and stable operation is possible.

ここで、表面電極と電極端子との間に緩衝部材を挿入せずに接合した比較例にかかる電力用半導体装置について、図3と図4を用いて説明する。
比較例にかかる電力用半導体装置100Cでは、図3に示すように、IGBT1の表面電極2と電極端子3とが、緩衝部材4を介さずに、直接接合されている。その他の構成にいては、実施の形態1にかかる電力用半導体装置100と同様である。
Here, a power semiconductor device according to a comparative example in which the buffer member is joined without being inserted between the surface electrode and the electrode terminal will be described with reference to FIGS. 3 and 4.
In the power semiconductor device 100 </ b> C according to the comparative example, as illustrated in FIG. 3, the surface electrode 2 and the electrode terminal 3 of the IGBT 1 are directly joined without the buffer member 4 interposed therebetween. Other configurations are the same as those of the power semiconductor device 100 according to the first embodiment.

この場合、図4(a)に示すように、緩衝部材4を挿入せずに表面電極2に電極端子3を載置して超音波接合を開始する。そして、超音波接合時に十分な接合面積を得るために必要な接合条件(加圧力、変形量等)で、図4(b)に示すように接合を行う。すると、電極端子3より表面電極2の方が耐力が小さいために、超音波ホーン50による加圧と超音波振動によって、表面電極2が一方的に変形する。その際、表面電極2が変形する量に比べて、実際の表面電極2の厚さが薄すぎるため、表面電極2の一部が排斥され、その下に形成されているトランジスタ11までもが破壊される。   In this case, as shown in FIG. 4A, the electrode terminal 3 is placed on the surface electrode 2 without inserting the buffer member 4, and ultrasonic bonding is started. And it joins as shown in FIG.4 (b) on joining conditions (pressing force, deformation amount, etc.) required in order to obtain sufficient joining area at the time of ultrasonic joining. Then, since the proof stress of the surface electrode 2 is smaller than that of the electrode terminal 3, the surface electrode 2 is unilaterally deformed by pressurization and ultrasonic vibration by the ultrasonic horn 50. At this time, since the actual thickness of the surface electrode 2 is too thin compared to the amount of deformation of the surface electrode 2, a part of the surface electrode 2 is discarded, and even the transistor 11 formed thereunder is destroyed. Is done.

更に接合が進むと、図4(c)に示すように電極端子3がIGBT1の基材と接触し、場合によっては、亀裂K1が生じてIGBT1自体が破壊されることもある。   When the bonding further proceeds, the electrode terminal 3 comes into contact with the base material of the IGBT 1 as shown in FIG. 4C, and in some cases, the crack K1 is generated and the IGBT 1 itself may be destroyed.

これに対して、上述した本発明の実施の形態1にかかる電力用半導体装置100では、表面電極2と電極端子3の間に緩衝部材4が挿入されている。したがって、超音波接合時には緩衝部材4が選択的に変形するため、表面電極2と電極端子3の硬度の差を考慮する必要が無くなる。そのため、表面電極2や電極端子3に用いる材料の選択の幅を広げることができる。   On the other hand, in the power semiconductor device 100 according to the first embodiment of the present invention described above, the buffer member 4 is inserted between the surface electrode 2 and the electrode terminal 3. Therefore, since the buffer member 4 is selectively deformed during ultrasonic bonding, it is not necessary to consider the difference in hardness between the surface electrode 2 and the electrode terminal 3. Therefore, the range of selection of the material used for the surface electrode 2 and the electrode terminal 3 can be expanded.

また、電極端子3と表面電極2の耐力の差がどれだけ大きくとも、IGBT1や表面電極2直下のトランジスタ11を破壊することなく表面電極2と電極端子3を接合することができ、かつ緩衝部材4が選択的に変形しながらトランジスタ11が形成された凹凸に沿って接合されるため、従来の接合より大きな接合面積を得ることが出来る。さらに、緩衝部材4は表面電極2と電極端子3の間に別の部材として挿入すれば良いため、蒸着やめっき等を用いる必要がなく、必要な厚みに容易に調整することができる。そのため、緩衝部材4の厚さを調整することで、超音波接合時に効率よくパワーを印加することができ、目的の電流を通電させるために十分な接合面積を得ることができる。   Further, no matter how large the difference in the proof stress between the electrode terminal 3 and the surface electrode 2, the surface electrode 2 and the electrode terminal 3 can be joined without destroying the IGBT 1 or the transistor 11 immediately below the surface electrode 2, and a buffer member Since the transistors 4 are selectively deformed and bonded along the unevenness in which the transistor 11 is formed, a larger bonding area than the conventional bonding can be obtained. Furthermore, since the buffer member 4 may be inserted as a separate member between the surface electrode 2 and the electrode terminal 3, it is not necessary to use vapor deposition or plating, and can be easily adjusted to a required thickness. Therefore, by adjusting the thickness of the buffer member 4, power can be efficiently applied during ultrasonic bonding, and a sufficient bonding area can be obtained to pass a target current.

さらにIGBT1の動作に伴って生じる熱応力についても、緩衝部材4が優先的に変形するため、熱応力によるIGBT1やトランジスタ11の破壊を防止することができる。   Further, with respect to the thermal stress caused by the operation of the IGBT 1, since the buffer member 4 is preferentially deformed, the destruction of the IGBT 1 and the transistor 11 due to the thermal stress can be prevented.

なお、緩衝部材4の形状は上記の機能を満たす形状であればどのような形状でもかまわないが、例えば断面が円形のワイヤや球のように、厚み方向に沿って幅(断面積)が変化する形状が好ましい。このような形状にすることで、超音波接合時に幅の狭い部分が潰れ拡がるように変形し、酸化膜等の接合を阻害する膜等が段階的に周囲に排斥されるため、最終的に得られる接合面積をより大きくすることができる。同様に、緩衝部材4の所望の位置に突起が配置されているような形状とすることで、上記の効果に加えて、より低い荷重で優先的な変形が可能となり、表面電極2へのダメージを低減することができる。   The buffer member 4 may have any shape as long as it satisfies the above functions. However, the width (cross-sectional area) varies along the thickness direction, for example, a wire or a sphere having a circular cross section. The shape is preferred. By adopting such a shape, the narrow portion is deformed so as to be crushed and expanded during ultrasonic bonding, and a film that inhibits bonding such as an oxide film is gradually discharged to the surroundings. The bonded area can be increased. Similarly, by adopting a shape in which the protrusion is arranged at a desired position of the buffer member 4, in addition to the above effects, preferential deformation is possible with a lower load and damage to the surface electrode 2 is achieved. Can be reduced.

さらに、緩衝部材4を予め表面電極2もしくは電極端子3に接合しておくことで、各部材を載置する際の位置決めを容易にすることができる。例えば、緩衝部材4としてAlワイヤを予めIGBT1の表面電極2にワイヤボンドしておき、その上に電極端子3を載置して超音波接合を行うことで、位置決めを容易に行うことができる。さらに、厚み方向に沿ってワイヤの断面が変化するので、Alワイヤが段階的に変形することで、平板を用いる場合と比較して、接合面積をより大きくすることができる。   Further, by preliminarily bonding the buffer member 4 to the surface electrode 2 or the electrode terminal 3, positioning when placing each member can be facilitated. For example, an Al wire is previously bonded to the surface electrode 2 of the IGBT 1 as the buffer member 4, and the electrode terminal 3 is placed thereon to perform ultrasonic bonding so that positioning can be performed easily. Furthermore, since the cross section of the wire changes along the thickness direction, the Al wire is deformed in stages, so that the bonding area can be increased as compared with the case where a flat plate is used.

以上のように、本発明の実施の形態1にかかる電力用半導体装置100によれば、一方の面に回路面が形成された回路基板5と、回路基板5の回路面側に裏面が接合され、表面に電極(表面電極2)が形成された電力用半導体素子であるIGBT1と、電力用半導体素子(IGBT1)の電極(表面電極2)の主構成材料(例えば、Al)よりも高い耐力を有する材料(例えば、Cu)で構成されるとともに、一端に電力用半導体素子(IGBT1)の電極(表面電極2)と対向する接合面3jが形成され、緩衝部材4を介して接合面3jが電力用半導体素子(IGBT1)の電極(表面電極2)と超音波接合された電極端子3と、を備え、緩衝部材4は、少なくとも電力用半導体素子(IGBT1)の電極(表面電極2)に接触する部分の材料が、電力用半導体素子(IGBT1)の電極(表面電極2)の主構成材料と同等以下の耐力を有するように構成したので、超音波接合時に緩衝部材4が選択的に塑性変形する。これによって表面電極2を一方的に塑性変形させずに接合できるため、電力用半導体素子(IGBT1)の表面側に形成されたトランジスタ11や素子自体が超音波接合時に破壊されるのを防止し、大電流に対応し、信頼性の高い電力用半導体装置100を得ることができる。さらに、表面電極2と緩衝部材4との接合、および電極端子3と緩衝部材4との接合が良好に行われることで、十分な接合面積を得ることができる。   As described above, according to the power semiconductor device 100 of the first embodiment of the present invention, the circuit board 5 having the circuit surface formed on one surface and the back surface is bonded to the circuit surface side of the circuit substrate 5. IGBT1, which is a power semiconductor element having an electrode (surface electrode 2) formed on the surface, and a higher yield strength than the main constituent material (for example, Al) of the electrode (surface electrode 2) of the power semiconductor element (IGBT1) A joint surface 3j that is made of a material (for example, Cu) and that faces the electrode (surface electrode 2) of the power semiconductor element (IGBT1) is formed at one end, and the joint surface 3j is connected to the power via the buffer member 4. The electrode (surface electrode 2) of the semiconductor element (IGBT1) and the electrode terminal 3 ultrasonically bonded are provided, and the buffer member 4 contacts at least the electrode (surface electrode 2) of the power semiconductor element (IGBT1). Partial Fee, since it is configured to have a main component material and equal to or less than the yield strength of the electrode (surface electrode 2) of the power semiconductor element (IGBT 1), the buffer member 4 is selectively plastically deformed during ultrasonic welding. As a result, the surface electrode 2 can be joined without unilateral plastic deformation, so that the transistor 11 formed on the surface side of the power semiconductor element (IGBT1) and the element itself are prevented from being destroyed during ultrasonic joining, A highly reliable power semiconductor device 100 that can handle a large current can be obtained. Furthermore, sufficient joining area can be obtained by joining the surface electrode 2 and the buffer member 4 and joining the electrode terminal 3 and the buffer member 4 well.

実施の形態2.
本実施の形態2にかかる電力用半導体装置では、実施の形態1と較べて電極端子の接合面に突起を形成するようにしたものである。図5と図6は、本発明の実施の形態2にかかる電力用半導体装置の構成を説明するための図である。図5は電力用半導体装置の部分断面図、図6は電力用半導体素子と電極端子部分の各工程における部分断面図で、図6(a)は電力用半導体素子に接合対象の電極端子を載置した状態、図6(b)は超音波ホーンを当てて接合している途中の状態、図6(c)は、超音波接合が完了した時の状態であり、それぞれ、実施の形態1にかかる電力用半導体装置の説明で用いた図1と図2に対応する。突起に対応して緩衝部材の形状を調整する場合はあるが、基本的に他の構成については実施の形態1で説明したものと同様であり、その部分の説明は省略する。
Embodiment 2. FIG.
In the power semiconductor device according to the second embodiment, a protrusion is formed on the bonding surface of the electrode terminal as compared with the first embodiment. 5 and 6 are diagrams for explaining the configuration of the power semiconductor device according to the second embodiment of the present invention. 5 is a partial cross-sectional view of the power semiconductor device, FIG. 6 is a partial cross-sectional view in each step of the power semiconductor element and the electrode terminal portion, and FIG. 6A shows the electrode terminal to be bonded to the power semiconductor element. 6B is a state in the middle of joining by applying an ultrasonic horn, and FIG. 6C is a state when the ultrasonic joining is completed. This corresponds to FIGS. 1 and 2 used in the description of the power semiconductor device. Although the shape of the buffer member may be adjusted in accordance with the protrusion, the other configuration is basically the same as that described in the first embodiment, and the description thereof is omitted.

図5に示すように、本実施の形態2にかかる電力用半導体装置200では、電極端子3の接合面3jの一部に突起3pが形成され、突起3pの周囲に緩衝部材4が存在し、表面電極2と緩衝部材4、および電極端子3と緩衝部材4との接合層に加えて、電極端子3の突起3pの表面と表面電極2との接合層を有することである。   As shown in FIG. 5, in the power semiconductor device 200 according to the second embodiment, the protrusion 3p is formed on a part of the joint surface 3j of the electrode terminal 3, and the buffer member 4 exists around the protrusion 3p. In addition to the bonding layer between the surface electrode 2 and the buffer member 4 and the electrode terminal 3 and the buffer member 4, the bonding layer between the surface of the protrusion 3 p of the electrode terminal 3 and the surface electrode 2 is provided.

電極端子3に形成された突起3pの数、形状は必要な電極端子3と表面電極2との接合面積を勘案して決める。突起3pの高さは、緩衝部材4の厚みと同等以下であればよいが、接合時の変形により、緩衝部材4の厚みが薄くなることを考えると、さらに低くする方が望ましい。突起3pの高さが緩衝部材4の厚みと同等の場合、超音波接合前の段階において突起3pが表面電極2に接触することになり、接合の進行に伴って突起3pが表面電極2を変形させてしまい、トランジスタ11を破壊する可能性が考えられるからである。そのため、突起3pの高さは、接合時に突起3pの先端部から緩衝部材4が排斥される程度に緩衝部材4(の外縁部)の厚みより低いことが好ましい。   The number and shape of the protrusions 3p formed on the electrode terminal 3 are determined in consideration of the required bonding area between the electrode terminal 3 and the surface electrode 2. The height of the protrusion 3p may be equal to or less than the thickness of the buffer member 4, but it is desirable that the height of the projection 3p be further reduced in view of the fact that the thickness of the buffer member 4 becomes thinner due to deformation during joining. When the height of the protrusion 3p is equal to the thickness of the buffer member 4, the protrusion 3p comes into contact with the surface electrode 2 before the ultrasonic bonding, and the protrusion 3p deforms the surface electrode 2 as the bonding proceeds. This is because there is a possibility that the transistor 11 is destroyed. Therefore, it is preferable that the height of the protrusion 3p is lower than the thickness of the buffer member 4 (outer edge portion thereof) to the extent that the buffer member 4 is rejected from the tip of the protrusion 3p at the time of joining.

さらに、突起3pの接合面3j内での配置は、機械的な接合強度を考慮すると、表面電極2と緩衝部材4、および電極端子3と緩衝部材4の接合層が突起3pの周りを取り囲むようにすることが望ましい。そのため、突起3pの面積は、表面電極2または電極端子3(の接合面3j)の面積の小さい方、または緩衝部材4の全体面積の30〜70%程度とするのが好ましい。本実施の形態2においては、突起3pとして電極端子3の接合面の中央部に円柱形のものを1箇所形成するようにしているが、突起3pの形状は円柱形に限らず、角柱等でもかまわない。また数も同様に複数個形成されていてもかまわないが、突起3pは超音波ホーン50で加圧したときに電極端子3が傾かないように、対向面を支持できるような配置が好ましい。   Further, the arrangement of the protrusion 3p in the bonding surface 3j is such that the bonding layer of the surface electrode 2 and the buffer member 4 and the electrode terminal 3 and the buffer member 4 surrounds the protrusion 3p in consideration of mechanical bonding strength. It is desirable to make it. Therefore, the area of the protrusion 3p is preferably about 30 to 70% of the smaller area of the surface electrode 2 or the electrode terminal 3 (joint surface 3j thereof) or the entire area of the buffer member 4. In the second embodiment, one protrusion is formed at the center of the joint surface of the electrode terminal 3 as the protrusion 3p. However, the shape of the protrusion 3p is not limited to the cylindrical shape, and may be a prism or the like. It doesn't matter. Similarly, a plurality of the projections 3p may be formed, but the projection 3p is preferably arranged so that the opposing surface can be supported so that the electrode terminal 3 does not tilt when pressed by the ultrasonic horn 50.

つぎに、本実施の形態2にかかる電力用半導体装置200の効果と製造方法について、図6の工程毎の接合部分近傍の断面図を用いて説明する。   Next, the effect and the manufacturing method of the power semiconductor device 200 according to the second embodiment will be described with reference to the cross-sectional view in the vicinity of the joining portion for each step in FIG.

はじめに、図6(a)に示すように、IGBT1の表面電極2上に緩衝部材4と電極端子3を載置し、電極端子3の上面3zの所定位置に先端が接触するように、超音波ホーン50を下降(z方向)させる。ここで、本実施の形態2における緩衝部材4は、突起3pの形状に対応して、突起3pに対応する部分は、周縁部に対して薄くなるように凹部4cが形成されている。緩衝部材4の形状は必ずしも、突起3pに対応した形状に合わせなくてもよい。しかし、例えば、突起3pが円柱状で、緩衝部材4を突起3pに応じたリング状とすれば、突起3pをリング内に収めることで、確実に表面電極2と突起3pとを直接接触させることができる。   First, as shown in FIG. 6A, the buffer member 4 and the electrode terminal 3 are placed on the surface electrode 2 of the IGBT 1, and ultrasonic waves are applied so that the tip contacts a predetermined position on the upper surface 3z of the electrode terminal 3. The horn 50 is lowered (z direction). Here, in the buffer member 4 according to the second embodiment, the concave portion 4c is formed so as to correspond to the shape of the projection 3p and the portion corresponding to the projection 3p is thinner than the peripheral portion. The shape of the buffer member 4 is not necessarily matched with the shape corresponding to the protrusion 3p. However, for example, if the protrusion 3p has a cylindrical shape and the buffer member 4 has a ring shape corresponding to the protrusion 3p, the surface electrode 2 and the protrusion 3p are surely brought into direct contact with each other by accommodating the protrusion 3p in the ring. Can do.

このように緩衝部材4をリング状にした場合、緩衝部材4が接合面の延在方向(xy面)において、突起3pを取り囲むことになる。すると、変形が大きく熱応力の発生が大きい外周部(周縁部)に緩衝部材4を用いた強固な接合層を形成することができる。さらに、外周側から緩衝部材4をハンドリングすることができるので、緩衝部材4の位置決めも容易になる。そのため、緩衝部材4の形状は、リング状のように突起3pを取り囲むような形状とすることが好ましい。   Thus, when the buffer member 4 is made into a ring shape, the buffer member 4 surrounds the protrusion 3p in the extending direction (xy plane) of the joint surface. Then, a strong bonding layer using the buffer member 4 can be formed on the outer peripheral portion (peripheral portion) where deformation is large and thermal stress is generated. Furthermore, since the buffer member 4 can be handled from the outer peripheral side, positioning of the buffer member 4 is facilitated. Therefore, it is preferable that the buffer member 4 has a shape surrounding the protrusion 3p like a ring.

なお、図6(a)の超音波接合前の段階において、突起3pが表面電極2に接触していると、実施の形態1の比較例のように、接合時に電極端子3(の突起3p)が表面電極2を変形させてしまい、トランジスタ11を破壊する可能性も考えられる。そのため、図6(a)の段階においては、突起3pは表面電極2に接触していないことが好ましい。そのためには、緩衝部材4の厚みと突起3pの高さの関係を調整する必要があるが、高さのみの調整で損傷を抑制するには、接合時の変形量等の精度を高くする必要がある。そこで、本実施の形態2では、高さ関係を調整した上で、さらに、凹部4cには、接合の進行にともなって容易に周縁部に排斥される程度の厚みを残すようにした。   If the protrusion 3p is in contact with the surface electrode 2 in the stage before ultrasonic bonding in FIG. 6A, the electrode terminal 3 (protrusion 3p) at the time of bonding as in the comparative example of the first embodiment. However, the surface electrode 2 may be deformed and the transistor 11 may be destroyed. Therefore, it is preferable that the protrusion 3p is not in contact with the surface electrode 2 in the stage of FIG. For that purpose, it is necessary to adjust the relationship between the thickness of the buffer member 4 and the height of the protrusion 3p, but in order to suppress damage by adjusting only the height, it is necessary to increase the accuracy of the deformation amount at the time of joining. There is. Therefore, in the second embodiment, after adjusting the height relationship, the concave portion 4c is left with a thickness that can be easily eliminated by the peripheral edge as the joining progresses.

そして、図6(b)に示すように、超音波ホーン50を電極端子3に対して加圧し、矢印の方向(xy面内)に超音波振動させる。これにより、表面電極2と緩衝部材4、および電極端子3と緩衝部材4との接触面同士が摺れて、接触面を覆っている酸化膜等の、接合を阻害する膜等が除去される。緩衝部材4は、超音波ホーン50による加圧と超音波振動によって、主に振動方向(xy)に引き伸ばされ、特に超音波ホーン50の突起部の下は薄く変形する。このとき、突起3pと表面電極2の間の緩衝部材4は超音波ホーン50による加圧と超音波振動により、変形して排斥され、酸化膜や、接合を阻害する膜等が除去された突起3pの先端面と表面電極2が直接接触する。   And as shown in FIG.6 (b), the ultrasonic horn 50 is pressurized with respect to the electrode terminal 3, and ultrasonically vibrates in the direction of an arrow (in xy plane). As a result, the contact surfaces of the surface electrode 2 and the buffer member 4 and the electrode terminals 3 and the buffer member 4 are slid to remove a film or the like that inhibits bonding, such as an oxide film covering the contact surface. . The buffer member 4 is stretched mainly in the vibration direction (xy) by the pressurization and ultrasonic vibration by the ultrasonic horn 50, and in particular, the portion below the protrusion of the ultrasonic horn 50 is thinly deformed. At this time, the buffer member 4 between the protrusion 3p and the surface electrode 2 is deformed and rejected by pressurization and ultrasonic vibration by the ultrasonic horn 50, and the protrusion from which the oxide film, the film inhibiting the bonding, and the like are removed. The tip surface of 3p and the surface electrode 2 are in direct contact.

最終的には、図6(c)に示すように、周縁部では、表面電極2と緩衝部材4、および電極端子3と緩衝部材4とは、超音波振動により接触面同士が接合され、強固な接合層J2−4、J3−4が形成される。さらに、表面電極2と突起3pの先端面とによる、超音波振動による接合層J2−3が形成されている。突起3pと表面電極2とが接触した段階で接合が完了するように調整しているため、表面電極2の変形が生じることはなく、トランジスタ11が破壊されることもない。 Finally, as shown in FIG. 6 (c), the contact surfaces of the surface electrode 2 and the buffer member 4 and the electrode terminal 3 and the buffer member 4 are joined to each other by ultrasonic vibration at the peripheral portion, so that they are strong. The bonding layers J 2-4 and J 3-4 are formed. In addition, a bonding layer J2-3 is formed by ultrasonic vibration by the surface electrode 2 and the tip surface of the protrusion 3p. Since the adjustment is made so that the bonding is completed when the protrusion 3p and the surface electrode 2 are in contact with each other, the surface electrode 2 is not deformed and the transistor 11 is not destroyed.

これにより、電極端子3と表面電極2とは、緩衝部材4を介した接合層J2−4、J3−4により機械的に強固に接合される。一方、突起3p部分は、電極端子3と表面電極2との直接の接合層J2−3により、電気的に強固に接合される。つまり、IGBT1への通電は、表面電極2と突起3pとの接合層J2−3を介して行うことができるようになる。そのため、緩衝部材4は、材料の電気抵抗率に関係なく選択できるようになるため、より多くの材料から選択することができるようになる。 Thereby, the electrode terminal 3 and the surface electrode 2 are mechanically firmly joined by the joining layers J 2-4 and J 3-4 through the buffer member 4. On the other hand, the protrusion 3p portion, by direct bonding layer J 2-3 between the electrode terminals 3 and the surface electrode 2 is electrically firmly bonded. In other words, energization of the IGBT1 will be able to perform through the bonding layer J 2-3 of the surface electrode 2 and the protrusion 3p. Therefore, since the buffer member 4 can be selected regardless of the electrical resistivity of the material, it can be selected from more materials.

以上のように、本実施の形態2にかかる電力用半導体装置200では、電極端子3の接合面3jには、電力用半導体素子(IGBT1)の電極(表面電極2)に向かって突出する突起3pが形成されているように構成したので、表面電極2と電極端子3とが直接接合することで、効率よく通電が行えるようになる。さらに、緩衝部材4の材料選択肢が広がる。   As described above, in the power semiconductor device 200 according to the second embodiment, the protrusion 3p protruding toward the electrode (surface electrode 2) of the power semiconductor element (IGBT1) is formed on the bonding surface 3j of the electrode terminal 3. Since the surface electrode 2 and the electrode terminal 3 are directly joined to each other, it is possible to efficiently energize. Furthermore, the material choice of the buffer member 4 is expanded.

また、上記各実施の形態にかかる電力用半導体装置100、200の製造方法によれば、電力用半導体素子(IGBT1)が接合された回路基板5を超音波接合装置に固定する工程と、電力用半導体素子(IGBT1)の電極(表面電極2)に、緩衝部材4と電極端子3を順次積層する工程と、電極端子3の接合面3jの反対側となる上面3zから超音波接合装置のホーン(超音波ホーン50)を当て、電力用半導体素子(IGBT1)の電極(表面電極2)と電極端子3とを緩衝部材4を介して超音波接合する工程と、を含むように構成したので、上述した電力用半導体装置100、200を容易に得ることができる。   Moreover, according to the manufacturing method of the power semiconductor devices 100 and 200 according to each of the above embodiments, the step of fixing the circuit board 5 to which the power semiconductor element (IGBT1) is bonded to the ultrasonic bonding apparatus, The step of sequentially stacking the buffer member 4 and the electrode terminal 3 on the electrode (surface electrode 2) of the semiconductor element (IGBT1), and the horn of the ultrasonic bonding apparatus from the upper surface 3z opposite to the bonding surface 3j of the electrode terminal 3 ( The ultrasonic horn 50) is applied and the electrode (surface electrode 2) of the power semiconductor element (IGBT1) and the electrode terminal 3 are ultrasonically bonded via the buffer member 4, so that the above-mentioned is included. The obtained power semiconductor devices 100 and 200 can be easily obtained.

また、上記各実施の形態にかかる電力用半導体装置100、200の別の製造方法によれば、例えば、ワイヤボンドや蒸着、めっき等により、電力用半導体素子(IGBT1)の電極(表面電極2)および電極端子3の接合面3jの少なくとも一方の表面に緩衝部材4を形成する工程と、電力用半導体素子(IGBT1)が接合された回路基板5を超音波接合装置に固定する工程と、電力用半導体素子(IGBT1)の電極(表面電極2)に、電極端子3を重ねる工程と、電極端子3の接合面3jの反対側となる上面3zから超音波接合装置のホーン(超音波ホーン50)を当て、電力用半導体素子(IGBT1)の電極(表面電極2)と電極端子3とを緩衝部材4を介して超音波接合する工程と、を含むように構成したので、上述した電力用半導体装置100、200を容易に得ることができる。   Moreover, according to another manufacturing method of the power semiconductor devices 100 and 200 according to the above embodiments, the electrode (surface electrode 2) of the power semiconductor element (IGBT1) is formed by, for example, wire bonding, vapor deposition, plating, or the like. And a step of forming the buffer member 4 on at least one surface of the bonding surface 3j of the electrode terminal 3, a step of fixing the circuit board 5 to which the power semiconductor element (IGBT1) is bonded to the ultrasonic bonding apparatus, The step of superimposing the electrode terminal 3 on the electrode (surface electrode 2) of the semiconductor element (IGBT1), and the horn (ultrasonic horn 50) of the ultrasonic bonding apparatus from the upper surface 3z opposite to the bonding surface 3j of the electrode terminal 3 And the step of ultrasonically bonding the electrode (surface electrode 2) and the electrode terminal 3 of the power semiconductor element (IGBT1) via the buffer member 4, so that the power described above is included. It is possible to obtain a semiconductor device 100, 200 with ease.

とくに、緩衝部材4は、超音波接合の工程が行われる前には、厚み方向に沿って断面積が変化するようなもの、例えばワイヤで形成したので、断面積が小さな部分から段階的に変形して、より強固な接合が可能となる。さらに、ワイヤを事前に表面電極2あるいは電極端子3に接合(ボンディング)することで緩衝部材4を形成するようにしておけば、位置決めも容易になる。   In particular, the buffer member 4 is formed of a wire whose cross-sectional area changes along the thickness direction, for example, a wire, before the ultrasonic bonding process is performed. As a result, stronger bonding is possible. Further, if the buffer member 4 is formed by bonding (bonding) the wire to the surface electrode 2 or the electrode terminal 3 in advance, positioning is facilitated.

とくに、緩衝部材4の超音波接合の工程が行われる前の厚みは、電力用半導体素子(IGBT1)の電極(表面電極2)よりも厚くなるように構成したので、緩衝部材4の変形能が高まり、より大きなパワーで接合することができる。   In particular, since the thickness before the ultrasonic bonding step of the buffer member 4 is performed is configured to be thicker than the electrode (surface electrode 2) of the power semiconductor element (IGBT1), the deformability of the buffer member 4 is improved. It can be joined with higher power.

1:IGBT(電力用半導体素子)、
2:表面電極、
3:電極端子、
3j:接合面、3p:突起部、
4:緩衝部材、
5:回路基板、
6:放熱部材、
50:超音波ホーン、
100,200:電力用半導体装置。
1: IGBT (power semiconductor element),
2: Surface electrode
3: Electrode terminal,
3j: bonding surface, 3p: protrusion
4: Buffer member,
5: Circuit board,
6: heat dissipation member,
50: Ultrasonic horn,
100, 200: Power semiconductor device.

Claims (6)

一方の面に回路面が形成された回路基板と、
前記回路基板の回路面側に裏面が接合され、表面に電極が形成された電力用半導体素子と、
前記電力用半導体素子の電極の主構成材料よりも高い耐力を有する材料で構成されるとともに、一端に前記電力用半導体素子の電極と対向する接合面が形成され、前記接合面が緩衝部材を介して前記電力用半導体素子の電極と超音波接合された電極端子と、を備え、
前記緩衝部材は、少なくとも前記電力用半導体素子の電極に接触する部分の材料が、前記電力用半導体素子の電極の主構成材料と同等以下の耐力を有し、
前記接合面および前記電力用半導体素子の電極は、離間した状態で、前記緩衝部材を介して前記接合面および前記電力用半導体素子の電極との間にそれぞれ接合層を有することを特徴とする電力用半導体装置。
A circuit board having a circuit surface formed on one surface;
A power semiconductor element in which a back surface is bonded to the circuit surface side of the circuit board and an electrode is formed on the surface;
The power semiconductor element is made of a material having a higher proof strength than the main constituent material of the electrode, and a joint surface facing the electrode of the power semiconductor element is formed at one end, and the joint surface is interposed through a buffer member. An electrode terminal ultrasonically bonded to the electrode of the power semiconductor element,
The buffer member has at least a proof stress equal to or less than that of a main constituent material of the electrode of the power semiconductor element, at least a material of a portion in contact with the electrode of the power semiconductor element.
The bonding surface and the electrode of the power semiconductor element each have a bonding layer between the bonding surface and the electrode of the power semiconductor element via the buffer member in a state of being separated from each other. Semiconductor device.
前記電極端子の接合面には、前記電力用半導体素子の電極に向かって突出する突起が形成されていることを特徴とする請求項1に記載の電力用半導体装置。   2. The power semiconductor device according to claim 1, wherein a protrusion projecting toward an electrode of the power semiconductor element is formed on a bonding surface of the electrode terminal. 前記緩衝部材は、前記接合面および前記電力用半導体素子の電極との間全体に形成されていることを特徴とする請求項1または2に記載の電力用半導体装置。   The power semiconductor device according to claim 1, wherein the buffer member is formed between the joint surface and an electrode of the power semiconductor element. 電力用半導体素子の裏面が回路面に接合された回路基板を超音波接合装置に固定する工程と、
電力用半導体素子の電極に、少なくとも前記電力用半導体素子の電極に接触する部分の材料が前記電力用半導体素子の電極の主構成材料と同等以下の耐力を有する緩衝部材と前記電力用半導体素子の電極の主構成材料よりも高い耐力を有する材料で構成される電極端子とを順次積層する工程と、
前記電極端子の接合面の反対側から前記超音波接合装置のホーンを当て、前記電力用半導体素子の電極と前記電極端子とを前記緩衝部材を介して超音波接合する工程と、
を含み、
前記超音波接合する工程が行われる前の前記緩衝部材の厚みは、前記電力用半導体素子の電極よりも厚く、前記電極端子より薄く、
前記超音波接合する工程は、前記接合面および前記電力用半導体素子の電極が、離間した状態で、前記緩衝部材を介して前記接合面および前記電力用半導体素子の電極との間にそれぞれ接合層を形成することを特徴とする電力用半導体装置の製造方法。
Fixing the circuit board having the back surface of the power semiconductor element bonded to the circuit surface to the ultrasonic bonding apparatus;
A buffer member having a proof strength equal to or less than that of a main constituent material of the electrode of the power semiconductor element, at least a portion of a material contacting the electrode of the power semiconductor element, and an electrode of the power semiconductor element of the power semiconductor element A step of sequentially laminating electrode terminals made of a material having higher proof strength than the main constituent material of the electrode;
Applying the horn of the ultrasonic bonding device from the opposite side of the bonding surface of the electrode terminal, and ultrasonically bonding the electrode of the power semiconductor element and the electrode terminal via the buffer member;
Including
When the thickness of the buffer member before the step of bonding ultrasound is performed it is thicker than the electrode of the semiconductor element for electric power, rather thin from the electrode terminal,
The ultrasonic bonding step includes bonding layers between the bonding surface and the electrode of the power semiconductor element via the buffer member, with the bonding surface and the electrode of the power semiconductor element being separated from each other. Forming a power semiconductor device.
電力用半導体素子の電極および前記電力用半導体素子の電極の主構成材料よりも高い耐力を有する材料で構成される電極端子の接合面の少なくとも一方の表面に少なくとも前記電力用半導体素子の電極に接触する部分の材料が前記電力用半導体素子の電極の主構成材料と同等以下の耐力を有する緩衝部材を形成する工程と、
前記電力用半導体素子の裏面が回路面に接合された回路基板を超音波接合装置に固定する工程と、
前記電力用半導体素子の電極に前記電極端子を重ねる工程と、
前記電極端子の接合面の反対側から前記超音波接合装置のホーンを当て、前記電力用半導体素子の電極と前記電極端子とを前記緩衝部材を介して超音波接合する工程と、
を含み、
前記超音波接合する工程が行われる前の前記緩衝部材の厚みは、前記電力用半導体素子の電極よりも厚く、前記電極端子より薄く、
前記超音波接合する工程は、前記接合面および前記電力用半導体素子の電極が、離間した状態で、前記緩衝部材を介して前記接合面および前記電力用半導体素子の電極との間にそれぞれ接合層を形成することを特徴とする電力用半導体装置の製造方法。
Contact with at least one of the electrodes of the power semiconductor element and at least one surface of the joint surface of the electrode terminal composed of a material having higher proof strength than the main constituent material of the electrode of the power semiconductor element and the electrode of the power semiconductor element Forming a buffer member having a yield strength equal to or less than that of the main constituent material of the electrode of the power semiconductor element;
Fixing a circuit board having a back surface of the power semiconductor element bonded to a circuit surface to an ultrasonic bonding apparatus;
Superimposing the electrode terminal on the electrode of the power semiconductor element;
Applying the horn of the ultrasonic bonding device from the opposite side of the bonding surface of the electrode terminal, and ultrasonically bonding the electrode of the power semiconductor element and the electrode terminal via the buffer member;
Including
When the thickness of the buffer member before the step of bonding ultrasound is performed it is thicker than the electrode of the semiconductor element for electric power, rather thin from the electrode terminal,
The ultrasonic bonding step includes bonding layers between the bonding surface and the electrode of the power semiconductor element via the buffer member, with the bonding surface and the electrode of the power semiconductor element being separated from each other. Forming a power semiconductor device.
前記超音波接合する工程が行われる前の前記緩衝部材の厚みは、0.05mm〜0.5mmの範囲であることを特徴とする請求項またはに記載の電力用半導体装置の製造方法。 When the thickness of the buffer member before the step of bonding ultrasound is performed, method of manufacturing the power semiconductor device according to claim 4 or 5, characterized in that in the range of 0.05 mm to 0.5 mm.
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US9337113B2 (en) 2012-11-20 2016-05-10 Toyota Jidosha Kabushiki Kaisha Semiconductor device
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CN107615464B (en) 2015-06-11 2020-03-17 三菱电机株式会社 Method for manufacturing power semiconductor device and power semiconductor device
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US10249552B2 (en) * 2017-02-22 2019-04-02 Jmj Korea Co., Ltd. Semiconductor package having double-sided heat dissipation structure
US10882134B2 (en) 2017-04-04 2021-01-05 Kulicke And Soffa Industries, Inc. Ultrasonic welding systems and methods of using the same
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