JP2006269725A - Ceramic device and its manufacturing method - Google Patents

Ceramic device and its manufacturing method Download PDF

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JP2006269725A
JP2006269725A JP2005085476A JP2005085476A JP2006269725A JP 2006269725 A JP2006269725 A JP 2006269725A JP 2005085476 A JP2005085476 A JP 2005085476A JP 2005085476 A JP2005085476 A JP 2005085476A JP 2006269725 A JP2006269725 A JP 2006269725A
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ceramic substrate
dividing
ceramic
groove
surface side
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Japanese (ja)
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Hiroshi Kagata
博司 加賀田
Ichiro Kameyama
一郎 亀山
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2005085476A priority Critical patent/JP2006269725A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To suppress deterioration of a characteristic in a manufacturing process of a ceramic device in the ceramic device which is mainly used for high frequency use and in a manufacturing method of the device. <P>SOLUTION: In collective production of a plurality of ceramic devices 1 by dividing a large ceramic substrate 8 into small pieces, an upper division groove 9 and a lower division groove 10 are installed for dividing the large ceramic substrate 8. Opening width and depth of the lower division groove 10 are set to be larger than the upper division groove 9. Division stress is added in a direction where the large ceramic substrate 8 is bent to project to a lower face-side. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、主に高周波用途で使用されるセラミックデバイスおよびその製造方法に関するものである。   The present invention relates to a ceramic device mainly used for high frequency applications and a method for manufacturing the same.

近年、セラミック基板を用いた電子部品の形態として、セラミック基板の内層部分に高周波フィルタなどの所定の電子回路を形成する内部電極を適宜配置したセラミックデバイスが知られている。   In recent years, a ceramic device in which an internal electrode for forming a predetermined electronic circuit such as a high-frequency filter is appropriately disposed on an inner layer portion of a ceramic substrate is known as a form of an electronic component using a ceramic substrate.

また、このようなセラミックデバイスは、大判のセラミックグリーンシートに内部電極を印刷したものを適宜積層し大判のセラミック基板を形成し、この大判のセラミック基板を小片分割することで多数個のセラミックデバイスを一括生産する手法が用いられている。   In addition, such a ceramic device is formed by appropriately stacking large ceramic green sheets with internal electrodes printed thereon to form a large ceramic substrate, and dividing the large ceramic substrate into small pieces to divide a large number of ceramic devices. A batch production method is used.

そして、この大判のセラミック基板を小片分割するにあたっては、従来、大判のセラミック基板の分割ラインに予め分割溝を形成しておき、この分割溝に応力を加えることで分割していた。   In dividing the large-sized ceramic substrate into small pieces, conventionally, dividing grooves are formed in advance on the dividing line of the large-sized ceramic substrate, and the dividing grooves are applied with stress.

なお、この出願の発明に関する先行技術文献情報としては、例えば、特許文献1が知られている。
特開平7−99263号公報
As prior art document information relating to the invention of this application, for example, Patent Document 1 is known.
JP-A-7-99263

しかしながら、このような小片分割方法においては、分割時の大判のセラミック基板に大きな応力が加わることになり、この応力により大判のセラミック基板内に設けられた所定の回路を形成する内部電極に影響を及ぼし、これにより小片化されたセラミックデバイスの電気特性を劣化させてしまうという問題を有していた。   However, in such a small piece dividing method, a large stress is applied to the large-sized ceramic substrate at the time of dividing, and this stress affects the internal electrodes forming a predetermined circuit provided in the large-sized ceramic substrate. Thus, there has been a problem that the electrical characteristics of the ceramic device fragmented are deteriorated.

そこで、本発明はこのような問題を解決し、セラミックデバイスの製造過程における特性劣化を抑制することを目的とする。   Therefore, the present invention aims to solve such problems and suppress characteristic deterioration in the manufacturing process of ceramic devices.

この目的を達成するために本発明は、特に内層部分において所定の電子回路を形成する内部電極を有する大判のセラミック基板を小片分割するにあたり、大判のセラミック基板の上面側に設けられた上部分割溝と、大判のセラミック基板の下面側に設けられ上部分割溝と対峙する下部分割溝とを設け、下部分割溝の開口幅および深さを上部分割溝のものより大きく設定し、分割応力を大判のセラミック基板が下面側に向けて突出するように撓ませる方向に加えることにしたのである。   In order to achieve this object, the present invention provides an upper dividing groove provided on the upper surface side of a large-sized ceramic substrate, particularly when dividing a large-sized ceramic substrate having internal electrodes that form a predetermined electronic circuit in the inner layer portion. And a lower dividing groove provided on the lower surface side of the large-sized ceramic substrate and facing the upper dividing groove, the opening width and depth of the lower dividing groove are set larger than those of the upper dividing groove, and the dividing stress is The ceramic substrate was added in a direction to bend so that it protrudes toward the lower surface.

このようにしてセラミックデバイスを製造することで、小片分割時に大判のセラミック基板に加わる応力を抑制でき、結果として小片化されたセラミックデバイスにおける製造過程での電気特性の劣化を抑制することが出来るのである。   By manufacturing a ceramic device in this way, stress applied to a large-sized ceramic substrate at the time of dividing a small piece can be suppressed, and as a result, deterioration of electrical characteristics in the manufacturing process of the small-sized ceramic device can be suppressed. is there.

以下、本発明の一実施形態について図面を用いて説明する。   Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

図1は、本発明のセラミックデバイス1を模式的に示した断面図である。   FIG. 1 is a cross-sectional view schematically showing a ceramic device 1 of the present invention.

このセラミックデバイス1はセラミック基板2の内層部分に内部電極3を適宜配置し、高周波フィルタなどの所定の電子回路を形成したものである。また、セラミック基板2の内部にて形成しにくい回路素子例えば半導体素子、SAWデバイス素子、抵抗素子などは適宜セラミック基板2の上面にディスクリート部品4として搭載されている。   In the ceramic device 1, an internal electrode 3 is appropriately disposed on an inner layer portion of a ceramic substrate 2, and a predetermined electronic circuit such as a high frequency filter is formed. Further, circuit elements that are difficult to form inside the ceramic substrate 2, such as semiconductor elements, SAW device elements, resistance elements, and the like are appropriately mounted on the upper surface of the ceramic substrate 2 as discrete components 4.

なお、このセラミックデバイス1の下面つまりセラミックデバイス1を回路基板5に実装する実装面には、内部電極3と電気的に接続された端子電極6が設けられた構造となっている。   Note that a terminal electrode 6 electrically connected to the internal electrode 3 is provided on the lower surface of the ceramic device 1, that is, the mounting surface on which the ceramic device 1 is mounted on the circuit board 5.

そして、このようなセラミックデバイス1を形成するにあたっては、図2に示されるよう先ず未焼結状態にある大判のグリーンシート7上に多数個と利用の内部電極3を形成したものを準備し、この内部電極3が印刷された大判グリーンシート7を積層して大判のセラミック基板8を形成し、この大判のセラミック基板8の表面に小片分割用の分割溝9,10を形成し、この大判のセラミック基板8を焼成した後に必要に応じてディスクリート部品4を実装し、その後先に述べた分割溝9,10に沿って応力を加えることで個々のセラミックデバイス1に小片分割するのである。   And in forming such a ceramic device 1, as shown in FIG. 2, first prepared a large number of green electrodes 7 in an unsintered state and a plurality of internal electrodes 3 formed, A large-sized ceramic substrate 8 is formed by laminating the large-sized green sheets 7 on which the internal electrodes 3 are printed. Dividing grooves 9 and 10 for dividing small pieces are formed on the surface of the large-sized ceramic substrate 8. After the ceramic substrate 8 is fired, the discrete component 4 is mounted as necessary, and thereafter, a small piece is divided into individual ceramic devices 1 by applying stress along the dividing grooves 9 and 10 described above.

ここで、このセラミックデバイス1の製造方法においては、小片分割用の分割溝9,10は断面が略V字状であり、大判のセラミック基板8の上下両側に対峙するように設けられ、かつセラミックデバイス1の実装面となる下面側に設けられた下部分割溝10の開口幅および深さを、必要に応じてディスクリート部品4が搭載される上面側に設けられた上部分割溝9のものより大きく設定している。   Here, in the method for manufacturing the ceramic device 1, the dividing grooves 9 and 10 for dividing the small piece have a substantially V-shaped cross section, are provided so as to face both the upper and lower sides of the large ceramic substrate 8, and The opening width and depth of the lower dividing groove 10 provided on the lower surface side that is the mounting surface of the device 1 are larger than those of the upper dividing groove 9 provided on the upper surface side on which the discrete component 4 is mounted as necessary. It is set.

そして、この対峙する上部分割溝9および下部分割溝10を用いて大判のセラミック基板8を小片分割する際に加える分割応力を矢印11で示すよう大判のセラミック基板8が下方に向けて撓む方向で加えて小片分割することにより、下部分割溝10の開口端から頂部に至る辺の長さが大きくなり、これに伴いこの頂部に加わるモーメントが大きくなるため、より小さな分割応力で大判のセラミック基板8を分割できるようになるとともに、隣り合うセラミックデバイス1の連結幅が小さくなることで分割に要する応力を小さなものとでき、この小片分割によりセラミックデバイス1の電気特性の劣化を抑制できるのである。   The direction in which the large ceramic substrate 8 bends downward as indicated by the arrow 11 indicates the dividing stress applied when the large ceramic substrate 8 is divided into small pieces using the opposed upper divided groove 9 and lower divided groove 10. In addition to the above, by dividing into small pieces, the length of the side from the opening end of the lower dividing groove 10 to the top portion is increased, and the moment applied to the top portion is increased accordingly. 8 can be divided, and the connection width between the adjacent ceramic devices 1 is reduced, so that the stress required for the division can be reduced, and the deterioration of the electrical characteristics of the ceramic device 1 can be suppressed by this small piece division.

また、このように大判のセラミック基板8の上下面に上部分割溝9、下部分割溝10を設けたことにより、これにより製造されたセラミックデバイス1においては図1に示されるように、その側面と上面との上部稜線部分には上部切り欠き部12が、また側面と下面との下部稜線部分には下部切り欠き部13が形成されることとなり、この上部切り欠き部12と下部切り欠き部13がセラミックデバイス1に対して面取りを施したものと実質的に同じものとなるからセラミックデバイス1の強度を向上させたことになる。   Further, by providing the upper divided grooves 9 and the lower divided grooves 10 on the upper and lower surfaces of the large-sized ceramic substrate 8 as described above, in the ceramic device 1 manufactured thereby, as shown in FIG. An upper notch portion 12 is formed at the upper ridge line portion with the upper surface, and a lower notch portion 13 is formed at the lower ridge line portion between the side surface and the lower surface, and the upper notch portion 12 and the lower notch portion 13 are formed. Since this is substantially the same as that obtained by chamfering the ceramic device 1, the strength of the ceramic device 1 is improved.

さらに、図2に示される下部分割溝10の開口幅および深さを上部分割溝9より大きく設定したことにより、図1における下部切り欠き部13が上部切り欠き部12より大きなものとなり、この下部切り欠き部13が設けられたセラミックデバイス1の下面が回路基板5に実装する実装面となるため、落下衝撃などによる回路基板5の撓みによるセラミックデバイス1の角部分の破損などを抑制したものとなっている。   Further, by setting the opening width and depth of the lower dividing groove 10 shown in FIG. 2 to be larger than that of the upper dividing groove 9, the lower notch portion 13 in FIG. Since the lower surface of the ceramic device 1 provided with the notch portion 13 is a mounting surface to be mounted on the circuit board 5, damage to the corner portion of the ceramic device 1 due to bending of the circuit board 5 due to drop impact or the like is suppressed. It has become.

また、上部分割溝9を小さく設定したことにより、セラミック基板2の上面、つまりディスクリート部品4を搭載する面積を有効に確保でき、ディスクリート部品4の実装性も高められた構造となっている。   In addition, since the upper dividing groove 9 is set to be small, the upper surface of the ceramic substrate 2, that is, the area for mounting the discrete component 4 can be effectively secured, and the mountability of the discrete component 4 is improved.

なお、上述した一実施形態においては図2に示される上部分割溝9および下部分割溝10の断面形状を略V字状であるとして説明したが、本発明はこの断面形状にとらわれるものでなく、特に図示はしていないがV字状の斜辺を階段状とした形状や、U字状といった小片分割が可能な形状であれば良く、また、このように上部分割溝9や下部分割溝10の形状を変えることに伴って図1に示すセラミックデバイス1の上部切り欠き部12や下部切り欠き部13の形状も変わることとなるが、下部切り欠き部13が上部切り欠き部12より大きく設定されていることには変わりなく先に述べたものと同様の作用効果を奏するものである。   In the above-described embodiment, the cross-sectional shapes of the upper dividing groove 9 and the lower dividing groove 10 shown in FIG. 2 are described as being substantially V-shaped, but the present invention is not limited to this cross-sectional shape. Although not particularly illustrated, it may be any shape that can be divided into small pieces such as a V-shaped oblique side or a U-shape, and the upper dividing groove 9 and the lower dividing groove 10 may be formed in this way. As the shape changes, the shapes of the upper notch 12 and the lower notch 13 of the ceramic device 1 shown in FIG. 1 also change, but the lower notch 13 is set larger than the upper notch 12. However, it has the same effect as described above.

以上のように、本発明のセラミックデバイスにおいては、製造過程における電気特性の劣化を抑制できるという効果を有し、特に携帯電話のように小型化が進められる移動体通信用のセラミックデバイスとして有効である。   As described above, the ceramic device of the present invention has an effect of suppressing the deterioration of electrical characteristics in the manufacturing process, and is particularly effective as a ceramic device for mobile communication that is being reduced in size like a mobile phone. is there.

本発明の一実施形態におけるセラミックデバイスの断面図Sectional drawing of the ceramic device in one Embodiment of this invention 同セラミックデバイスの製造方法を示す模式図Schematic diagram showing the manufacturing method of the same ceramic device

符号の説明Explanation of symbols

1 セラミックデバイス
2 セラミック基板
3 内部電極
8 大判のセラミック基板
9 上部分割溝
10 下部分割溝
12 上部切り欠き部
13 下部切り欠き部
DESCRIPTION OF SYMBOLS 1 Ceramic device 2 Ceramic substrate 3 Internal electrode 8 Large format ceramic substrate 9 Upper division groove 10 Lower division groove 12 Upper notch 13 Lower notch

Claims (2)

内層部分において所定の電子回路を形成する内部電極を有する大判のセラミック基板と、この大判のセラミック基板を小片分割するために前記大判のセラミック基板の上面側に設けられた上部分割溝と、前記大判のセラミック基板の下面側に設けられ前記上部分割溝と対峙する下部分割溝とを備え、前記下部分割溝の開口幅および深さを前記上部分割溝のものより大きく設定し、前記大判のセラミック基板を小片分割するにあたり分割応力を前記大判のセラミック基板が下面側に向けて突出するように撓ませる方向に加えることを特徴とするセラミックデバイスの製造方法。 A large ceramic substrate having an internal electrode forming a predetermined electronic circuit in the inner layer portion; an upper dividing groove provided on the upper surface side of the large ceramic substrate for dividing the large ceramic substrate into small pieces; A lower divided groove provided on the lower surface side of the ceramic substrate and facing the upper divided groove, wherein an opening width and a depth of the lower divided groove are set larger than those of the upper divided groove, and the large-sized ceramic substrate A method for manufacturing a ceramic device is characterized in that, when a small piece is divided, a dividing stress is applied in a direction in which the large-sized ceramic substrate is bent so as to protrude toward the lower surface side. 内層部分において所定の電子回路を形成する内部電極を有する大判のセラミック基板と、この大判のセラミック基板を小片分割するために前記大判のセラミック基板の上面側に設けられた上部分割溝と、前記大判のセラミック基板の下面側に設けられ前記上部分割溝と対峙する下部分割溝とを備え、前記下部分割溝の開口幅および深さを前記上部分割溝のものより大きく設定し、前記大判のセラミック基板が前記下面側に向けて突出するように撓む方向に分割応力を加えて前記大判のセラミック基板を小片に分割することにより形成されたセラミックデバイスであって、前記セラミックデバイスの下面と側面とで形成される下部稜線部分を前記下部分割溝を形成する切り込み面で下部切り欠き部を形成し、前記セラミックデバイスの上面と前記側面とで形成される上部稜線部分を前記上部分割溝を形成する切り込み面で上部切り欠き部を形成するとともに、下部切り欠き部を上部切け欠き部より大きくしたことを特徴とするセラミックデバイス。 A large ceramic substrate having an internal electrode forming a predetermined electronic circuit in the inner layer portion; an upper dividing groove provided on the upper surface side of the large ceramic substrate for dividing the large ceramic substrate into small pieces; A lower divided groove provided on the lower surface side of the ceramic substrate and facing the upper divided groove, wherein an opening width and a depth of the lower divided groove are set larger than those of the upper divided groove, and the large-sized ceramic substrate Is a ceramic device formed by dividing the large-sized ceramic substrate into small pieces by applying a dividing stress in a direction to bend so as to protrude toward the lower surface side, the lower surface and the side surface of the ceramic device being The lower ridge line portion to be formed is formed with a lower notch portion by a cut surface forming the lower dividing groove, and the upper surface of the ceramic device and the front The upper ridge portion formed at the side surface to form the upper notch in the cut surface forming the upper dividing groove, ceramic devices, characterized in that the lower cut-out portion larger than the upper cut only out portion.
JP2005085476A 2005-03-24 2005-03-24 Ceramic device and its manufacturing method Pending JP2006269725A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022025834A (en) * 2020-07-30 2022-02-10 日本特殊陶業株式会社 Semiconductor package and semiconductor package manufacturing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0359660U (en) * 1989-10-12 1991-06-12
JPH06310821A (en) * 1993-04-27 1994-11-04 Nikko Electron Kk Ceramic package assembly, dividing and fabrication of ceramic package
JP2003249755A (en) * 2002-02-22 2003-09-05 Kyocera Corp Method for producing ceramic multilayer printed wiring board and ceramic multilayer printed wiring board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0359660U (en) * 1989-10-12 1991-06-12
JPH06310821A (en) * 1993-04-27 1994-11-04 Nikko Electron Kk Ceramic package assembly, dividing and fabrication of ceramic package
JP2003249755A (en) * 2002-02-22 2003-09-05 Kyocera Corp Method for producing ceramic multilayer printed wiring board and ceramic multilayer printed wiring board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022025834A (en) * 2020-07-30 2022-02-10 日本特殊陶業株式会社 Semiconductor package and semiconductor package manufacturing method

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