JP2006261652A - Package for semiconductor device, method of manufacturing the same, and semiconductor device - Google Patents

Package for semiconductor device, method of manufacturing the same, and semiconductor device Download PDF

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JP2006261652A
JP2006261652A JP2006035791A JP2006035791A JP2006261652A JP 2006261652 A JP2006261652 A JP 2006261652A JP 2006035791 A JP2006035791 A JP 2006035791A JP 2006035791 A JP2006035791 A JP 2006035791A JP 2006261652 A JP2006261652 A JP 2006261652A
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substrate
conductor
window
package
semiconductor device
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Hiroshi Miyagawa
弘志 宮川
Mitsuhiro Odagiri
光広 小田切
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01006—Carbon [C]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/181—Encapsulation
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a package for semiconductor device capable of meeting high-speed operation. <P>SOLUTION: The package for semiconductor device 10 has at least one of a ground plane 22 and a power plane 23, and both are formed on a substrate 16; a connection conductor 25 formed on an inner wall surface in the window 21 of the substrate 16, and electrically connected to the corresponding plane 22 or 23; a bonding pattern 26 formed on the surface of the substrate 16 near the edge of the window 21, and connected to the connection conductor 25; and a second external connection 28 formed on the surface side of the substrate 16, and electrically connected to the corresponding plane 22 or 23 via a through-hole conductor 27 formed in the substrate 16. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置用パッケージ、その製造方法、および半導体装置に関する。 The present invention relates to a package for a semiconductor device, a manufacturing method thereof, and a semiconductor device.

特開平１０−９２９７２号公報に、いわゆるＢＯＣ（ボードオンチップ）用のパッケージが開示されている。このＢＯＣ用パッケージは、主としてメモリー用の半導体チップを搭載するものであるが、プリント基板表層側に所要配線パターンと、該配線パターンを外部に接続するための外部接続部とが形成され、基板中央部に、基板裏面側に搭載される半導体チップの端子部が臨み、該端子部と表層側の配線パターンとの間を電気的に接続するワイヤが引き出される窓部が開口されたものである。
特開平１０−９２９７２号公報 Japanese Patent Application Laid-Open No. 10-92972 discloses a package for so-called BOC (board on chip). This BOC package mainly mounts a semiconductor chip for memory. A required wiring pattern and an external connection part for connecting the wiring pattern to the outside are formed on the printed circuit board surface layer side. In this part, a terminal part of a semiconductor chip mounted on the back side of the substrate faces, and a window part through which a wire for electrically connecting the terminal part and the wiring pattern on the surface layer side is drawn is opened.
Japanese Patent Laid-Open No. 10-92972

ところで、近年、半導体装置のますますの高速化が要求されており、メモリー用のパッケージであっても、内層（接地用プレーン、電源プレーン）が必要とされ始めている。
本発明は、上記要望に応えるべくなされたものであり、高速化に対応できる半導体装置用パッケージ、その製造方法、および半導体装置を提供することを目的とする。 Incidentally, in recent years, there has been a demand for higher speed of semiconductor devices, and an inner layer (a ground plane and a power plane) has begun to be required even for a memory package.
The present invention has been made to meet the above-described demand, and an object of the present invention is to provide a package for a semiconductor device, a method for manufacturing the same, and a semiconductor device that can cope with a higher speed.

本発明に係る半導体装置用パッケージは、基板表層側に所要配線パターンと、該配線パターンを外部に接続するための第１の外部接続部とが形成され、基板の所要部位に、基板裏面側に搭載される半導体チップの端子部が臨み、該端子部と表層側の配線パターンとの間を電気的に接続するワイヤが引き出される窓部が開口された半導体装置用パッケージにおいて、前記基板に形成された、接地プレーンおよび電源プレーンの少なくとも一方のプレーンと、前記基板の窓部内壁面に形成され、対応する前記プレーンに電気的に接続する接続導体部と、前記窓部の縁近傍の基板表層部に形成され、前記接続導体部に接続するボンディングパターンと、前記基板の表層側に形成され、基板に形成されたスルーホール導体部を介して、対応する前記プレーンに電気的に接続する第２の外部接続部とを具備することを特徴とする。   In the package for a semiconductor device according to the present invention, a required wiring pattern and a first external connection part for connecting the wiring pattern to the outside are formed on the substrate surface layer side. In a semiconductor device package in which a terminal portion of a semiconductor chip to be mounted faces and a window portion through which a wire for electrically connecting the terminal portion and a wiring pattern on the surface layer side is opened is formed on the substrate. Further, at least one of a ground plane and a power plane, a connection conductor portion formed on the inner wall surface of the window portion of the substrate and electrically connected to the corresponding plane, and a substrate surface layer portion near the edge of the window portion The bonding pattern formed and connected to the connection conductor portion and the corresponding pattern formed on the surface layer side of the substrate through the through-hole conductor portion formed on the substrate. Characterized by comprising a second external connection portion electrically connected to the over down.

前記接続導体部が、前記窓部内壁面全体に形成された導体部の一部が除去されることによって所用複数の独立した接続導体部に形成されていることを特徴とする。
あるいは、前記窓部内壁面の部位に凹溝が形成され、前記接続導体部が、該凹溝壁面に形成されていることを特徴とする。
また、前記第１および第２の外部接続部にバンプが形成されていることを特徴とする。 The connection conductor portion is formed in a plurality of independent connection conductor portions where necessary by removing a part of the conductor portion formed on the entire inner wall surface of the window portion.
Alternatively, a concave groove is formed in a portion of the inner wall surface of the window portion, and the connection conductor portion is formed in the concave groove wall surface.
Further, a bump is formed on the first and second external connection portions.

また、本発明に係る半導体装置は、上記パッケージの基板裏面側に、半導体チップが搭載され、基板の前記窓部に臨む半導体チップの端子部のうちの所要端子部と、基板表層側に形成された前記配線パターンとの間、および前記半導体チップの端子部のうちの所要端子部と、対応する前記ボンディングパターンとの間がワイヤにより電気的に接続されていることを特徴とする。
また、前記半導体チップとワイヤとが封止樹脂により封止されていることを特徴とする。 In addition, a semiconductor device according to the present invention has a semiconductor chip mounted on the back side of the substrate of the package, and is formed on a required terminal portion of the terminal portion of the semiconductor chip facing the window portion of the substrate and on the substrate surface side. In addition, the wiring patterns and the required terminal portions of the terminal portions of the semiconductor chip and the corresponding bonding patterns are electrically connected by wires.
The semiconductor chip and the wire are sealed with a sealing resin.

また本発明に係る半導体装置用パッケージの製造方法は、基板表層側に所要配線パターンと、該配線パターンを外部に接続するための第１の外部接続部とが形成され、基板の所要部位に、基板裏面側に搭載される半導体チップの端子部が臨み、該端子部と表層側の配線パターンとの間を電気的に接続するワイヤが引き出される窓部が開口された半導体装置用パッケージの製造方法において、接地プレーンおよび電源プレーンの少なくとも一方のプレーンを有し、表層側に導体層を有する多層の基板を形成する工程と、該基板の、形成すべき前記窓部の開口縁に一致する位置に、所要数の第１のスルーホールを形成し、該第１のスルーホール内壁に、対応する前記プレーンの端面を露出させる工程と、前記基板の前記窓部となる部位以外の部位に、第２のスルーホールを形成し、該第２のスルーホール内壁に、対応する前記プレーンの端面を露出させる工程と、前記第１および第２のスルーホール内壁にめっきにより導体部を形成し、該導体部とスルーホール内壁に露出している前記プレーンの端面とを電気的に接続する工程と、前記基板の前記導体層をエッチング加工して、前記配線パターン、前記第１の外部接続部、前記第２のスルーホール内壁に形成された導体部に接続する第２の外部接続部、および前記第１のスルーホール内壁に形成された導体部に接続するボンディングパターンを形成するエッチング工程と、前記基板に、前記第１のスルーホール上を開口線が通るようにして前記窓部を開口する工程とを具備することを特徴とする。   In the method for manufacturing a package for a semiconductor device according to the present invention, a required wiring pattern and a first external connection portion for connecting the wiring pattern to the outside are formed on the substrate surface layer side. Manufacturing method of package for semiconductor device in which terminal portion of semiconductor chip mounted on back side of substrate faces, and window portion through which wire electrically connecting between terminal portion and surface layer side wiring pattern is opened is opened The step of forming a multilayer substrate having at least one of a ground plane and a power plane and having a conductor layer on the surface layer side, and a position corresponding to the opening edge of the window portion to be formed on the substrate A step of forming a required number of first through holes, exposing an end face of the corresponding plane on the inner wall of the first through hole, and a portion other than a portion to be the window portion of the substrate Forming a second through hole, exposing a corresponding end face of the plane on the inner wall of the second through hole, and forming a conductor portion by plating on the inner walls of the first and second through holes, Electrically connecting the conductor portion and an end face of the plane exposed on the inner wall of the through hole; and etching the conductor layer of the substrate to form the wiring pattern, the first external connection portion, An etching step for forming a second external connection portion connected to the conductor portion formed on the inner wall of the second through hole, and a bonding pattern connected to the conductor portion formed on the inner wall of the first through hole; And a step of opening the window portion so that an opening line passes through the first through hole in the substrate.

また、前記第１のスルーホール、第２のスルーホールを同一の工程により形成することを特徴とする。
また、前記第１および第２の外部接続部上にバンプを形成する工程を含むことを特徴とする。 Further, the first through hole and the second through hole are formed by the same process.
The method further includes a step of forming bumps on the first and second external connection portions.

また、本発明に係る半導体装置用パッケージの製造方法は、基板表層側に所要配線パターンと、該配線パターンを外部に接続するための第１の外部接続部とが形成され、基板の所要部位に、基板裏面側に搭載される半導体チップの端子部が臨み、該端子部と表層側の配線パターンとの間を電気的に接続するワイヤが引き出される窓部が開口された半導体装置用パッケージの製造方法において、接地プレーンおよび電源プレーンの少なくとも一方のプレーンを有し、表層側に導体層を有する多層の基板を形成する工程と、該基板の中央部に前記窓部を開口し、該窓部内壁に、対応する前記プレーンの端面を露出させる工程と、前記基板の前記窓部となる部位以外の部位に、第２のスルーホールを形成し、該第２のスルーホール内壁に、対応する前記プレーンの端面を露出させる工程と、前記窓部および第２のスルーホール内壁にめっきにより導体部を形成し、該導体部とスルーホール内壁に露出している前記プレーンの端面とを電気的に接続する工程と、前記基板の前記導体層をエッチング加工して、前記配線パターン、前記第１の外部接続部、前記第２のスルーホール内壁に形成された導体部に接続する第２の外部接続部、および前記窓部内壁に形成された導体部に接続するボンディングパターンを形成するエッチング工程とを具備することを特徴とする。
また前記窓部内壁に形成された導体部を一部除去し、所要複数の独立した導体部に分割する工程を具備することを特徴とする。 Also, in the method for manufacturing a package for a semiconductor device according to the present invention, a required wiring pattern and a first external connection portion for connecting the wiring pattern to the outside are formed on the substrate surface layer side. Manufacturing of a package for a semiconductor device in which a terminal portion of a semiconductor chip mounted on the back side of the substrate faces and a window portion through which a wire for electrically connecting the terminal portion and a wiring pattern on the surface layer is drawn is opened In the method, a step of forming a multilayer substrate having at least one of a ground plane and a power plane, and having a conductor layer on a surface layer side, and opening the window at the center of the substrate, the inner wall of the window And exposing a corresponding end face of the plane, and forming a second through hole in a portion other than the portion to be the window portion of the substrate, and corresponding to the inner wall of the second through hole. A step of exposing the end surface of the plane, and forming a conductor portion by plating on the window portion and the inner wall of the second through hole, and electrically connecting the conductor portion and the end surface of the plane exposed to the inner wall of the through hole. And a second external connection for connecting to the wiring pattern, the first external connection portion, and the conductor portion formed on the inner wall of the second through hole by etching the conductive layer of the substrate. And an etching process for forming a bonding pattern connected to the conductor formed on the inner wall of the window.
The method further comprises a step of removing a part of the conductor formed on the inner wall of the window and dividing it into a plurality of required independent conductors.

本発明に係る半導体装置用パッケージ、半導体装置によれば、接地プレーンおよび／または電源プレーンを設けたので、信号伝播の高速化および安定化が図れる。また、窓部内壁面に、対応する接地プレーンおよび／または電源プレーンに電気的に接続する複数の接続導体部を設け、窓部の縁近傍の基板表層部に前記接続導体部に接続するボンディングパターンを設けたので、基板表層部に接地用および／または電源用の配線パターンを設ける必要がなく、それだけ、信号用の配線密度を高めることができると共に、接地用、電源用のパスを短くでき、信号のリターン電流を接地プレーンおよび／または電源プレーンに流すことができ、基板の配線部の特性インピーダンスを容易に制御することができ、電気的特性を向上させることができる。   According to the semiconductor device package and the semiconductor device according to the present invention, since the ground plane and / or the power supply plane are provided, the signal propagation can be speeded up and stabilized. In addition, a plurality of connection conductor portions that are electrically connected to the corresponding ground plane and / or power plane are provided on the inner wall surface of the window portion, and a bonding pattern that is connected to the connection conductor portion is formed on the substrate surface layer portion near the edge of the window portion. Since it is provided, it is not necessary to provide a wiring pattern for grounding and / or power supply on the surface layer portion of the board, and accordingly, the wiring density for signals can be increased, and the path for grounding and power supply can be shortened, Return current can be passed through the ground plane and / or the power supply plane, the characteristic impedance of the wiring portion of the substrate can be easily controlled, and the electrical characteristics can be improved.

以下本発明における最良の実施の形態を詳細に説明する。
図１は、ＢＯＣ用の半導体装置用パッケージ１０に、半導体チップ１２を搭載した半導体装置１４の概略的な説明断面図である。図２はパッケージ１０の一部切り欠き斜視図である。
半導体装置用パッケージ１０は、プリント配線基板１６の表層側に形成された所要の配線パターン１７と、該配線パターン１７を外部に接続するための第１の外部接続部１８とが形成され、基板１６の中央部に、基板１６の裏面側に搭載される半導体チップ１２の端子部１９が臨み、該端子部１９と表層側の配線パターン１７との間を電気的に接続するワイヤ２０が引き出される窓部２１が開口されている点は従来の半導体装置用パッケージと同一である。
なお、窓部２１は基板１６の中央部以外の部位、例えば基板１６の周縁部に設けてもよい（図示せず）。以下では、窓部２１を基板１６の中央部に設ける場合を例として説明する。 The best mode of the present invention will be described in detail below.
FIG. 1 is a schematic cross-sectional view of a semiconductor device 14 in which a semiconductor chip 12 is mounted on a BOC semiconductor device package 10. FIG. 2 is a partially cutaway perspective view of the package 10.
The semiconductor device package 10 is formed with a required wiring pattern 17 formed on the surface layer side of the printed wiring board 16 and a first external connection portion 18 for connecting the wiring pattern 17 to the outside. A window from which the terminal portion 19 of the semiconductor chip 12 mounted on the back surface side of the substrate 16 faces the central portion of the substrate 16 and a wire 20 for electrically connecting the terminal portion 19 and the wiring pattern 17 on the surface layer side is drawn out. The point that the portion 21 is opened is the same as that of the conventional package for a semiconductor device.
Note that the window portion 21 may be provided at a portion other than the central portion of the substrate 16, for example, at the peripheral portion of the substrate 16 (not shown). Below, the case where the window part 21 is provided in the center part of the board | substrate 16 is demonstrated as an example.

本実施の形態に係るパッケージ１０では、基板１６の内層に形成された、接地プレーン２２および電源プレーン２３の少なくとも一方のプレーンと、基板１６の窓部２１の内壁面に形成され、対応するプレーン２２、２３に電気的に接続する複数の接続導体部２５と、窓部２１の縁近傍の基板１６表層部に形成され、接続導体部２５に接続するボンディングパターン２６と、基板１６の表層側に形成され、基板１６に形成されたスルーホール導体部２７を介して、対応するプレーン２２、２３に電気的に接続する第２の外部接続部２８とを具備することを特徴とする。
なお、３０はソルダーレジスト膜である。
また、配線パターン１７や導体部２５等の外部に露出する部位には、Ni／Au等の耐食めっき皮膜を形成するとよい。 In the package 10 according to the present embodiment, at least one of the ground plane 22 and the power supply plane 23 formed on the inner layer of the substrate 16 and the inner wall surface of the window portion 21 of the substrate 16, the corresponding plane 22 is formed. Are formed on the surface layer portion of the substrate 16 near the edge of the window portion 21 and formed on the surface layer side of the substrate 16. And a second external connection portion 28 electrically connected to the corresponding planes 22 and 23 through through-hole conductor portions 27 formed on the substrate 16.
Reference numeral 30 denotes a solder resist film.
Moreover, it is good to form corrosion-resistant plating films, such as Ni / Au, in the site | part exposed outside, such as the wiring pattern 17 and the conductor part 25. FIG.

図１、図２に示す例では、接地プレーン２２、電源プレーン２３の両方を基板１６の内層側に設けたが、どちらか一方でもよい。また、図１では、接地プレーン２２と接続導体部２５とが電気的に接続され、また、接地プレーン２２がスルーホール導体部２７を介して第２の外部接続部２８に接続されている部位を断面で示したが、電源プレーン２３も、窓部２１内壁面における他の部位の接続導体部２５に電気的に接続し（図２参照）、また、他の部位におけるスルーホール導体部２７を介して他の部位における第２の外部接続部２８に接続している。なお、図２では、第２の外部接続部２８の図示を省略している。   In the example shown in FIGS. 1 and 2, both the ground plane 22 and the power plane 23 are provided on the inner layer side of the substrate 16, but either one may be used. In FIG. 1, the ground plane 22 and the connection conductor portion 25 are electrically connected, and the portion where the ground plane 22 is connected to the second external connection portion 28 via the through-hole conductor portion 27 is shown. Although shown in a cross section, the power supply plane 23 is also electrically connected to the connection conductor portion 25 in the other portion of the inner wall surface of the window portion 21 (see FIG. 2), and through the through-hole conductor portion 27 in the other portion. And connected to the second external connection portion 28 in another part. In addition, in FIG. 2, illustration of the 2nd external connection part 28 is abbreviate | omitted.

第１の外部接続部１８、第２の外部接続部２８には、はんだボール等のバンプ３２を取り付けている。
また、窓部２１内壁面に形成する接続導体部２５は、窓部２１の内壁面に形成した断面が半円状をなす凹溝の壁面上に形成されている（図２）。 Bumps 32 such as solder balls are attached to the first external connection portion 18 and the second external connection portion 28.
Moreover, the connection conductor part 25 formed in the inner wall surface of the window part 21 is formed on the wall surface of the ditch | groove which the cross section formed in the inner wall surface of the window part 21 makes | forms a semicircle shape (FIG. 2).

そして、半導体装置用パッケージ１０の基板１６の裏面側に、半導体チップ１２が搭載され、基板１６の窓部２１に臨む半導体チップ１２の端子部１９のうちの所要端子部１９と、基板１６の表層側に形成された配線パターン１７のボンディングエリア１７ａとの間、および半導体チップ１２の端子部１９のうちの所要端子部１９と、対応するボンディングパターン２６との間がワイヤ２０により電気的に接続されて半導体装置１４に完成されている。
なお、半導体チップ１２とワイヤ２０とが封止樹脂３５により封止されている。 The semiconductor chip 12 is mounted on the back side of the substrate 16 of the semiconductor device package 10, and the required terminal portion 19 of the terminal portions 19 of the semiconductor chip 12 facing the window portion 21 of the substrate 16 and the surface layer of the substrate 16. The wire 20 is electrically connected to the bonding area 17a of the wiring pattern 17 formed on the side, and the required terminal portion 19 of the terminal portions 19 of the semiconductor chip 12 and the corresponding bonding pattern 26. Thus, the semiconductor device 14 is completed.
The semiconductor chip 12 and the wire 20 are sealed with a sealing resin 35.

続いて、図３〜図９によりパッケージ１０の製造方法について説明する。
なお、各図の（ａ）は断面図、（ｂ）は平面図（部分、または全体平面図）である。
まず、図３に示すように、内層に所要パターンの接地プレーン２２および電源プレーン２３の少なくとも一方のプレーンを有し、少なくとも表層側に銅箔等からなる導体層３６を有する多層の樹脂製基板１６を形成もしくは準備する。この多層の基板１６は、通常の多層プリント配線基板を形成する方法によって製造できる。 Next, a method for manufacturing the package 10 will be described with reference to FIGS.
In addition, (a) of each figure is sectional drawing, (b) is a top view (part or whole top view).
First, as shown in FIG. 3, a multilayer resin substrate 16 having at least one of a ground plane 22 and a power plane 23 having a required pattern on the inner layer and a conductor layer 36 made of copper foil or the like on at least the surface layer side. Form or prepare. The multilayer substrate 16 can be manufactured by a method of forming a normal multilayer printed wiring board.

次いで図４に示すように、基板１６の、形成すべき前記窓部２１の開口縁に一致する位置に、所要複数の第１のスルーホール３７を形成し、該第１のスルーホール３７内壁に、対応するプレーン（図示では接地プレーン２２）の端面を露出させる。電源プレーン２３も他の部位における第１のスルーホール３７内壁に端面が露出する。
また、基板１６の窓部２１となる部位以外の所要部位に、第２のスルーホール３８（図１）を形成し、該第２のスルーホール３８内壁に、対応するプレーンの端面を露出させる。この第１のスルーホール３７と第２のスルーホール３８は、適宜大きさのドリルを用いて、同一工程で行うことができる。 Next, as shown in FIG. 4, a plurality of required first through holes 37 are formed on the substrate 16 at positions corresponding to the opening edges of the window portion 21 to be formed, and the inner walls of the first through holes 37 are formed. The end face of the corresponding plane (the ground plane 22 in the figure) is exposed. The end face of the power supply plane 23 is also exposed on the inner wall of the first through hole 37 in another part.
Further, the second through hole 38 (FIG. 1) is formed in a required portion other than the portion to be the window portion 21 of the substrate 16, and the end face of the corresponding plane is exposed on the inner wall of the second through hole 38. The first through hole 37 and the second through hole 38 can be formed in the same process using a drill of an appropriate size.

次に、図５に示すように、第１および第２のスルーホール内壁および導体部３６上に、無電解銅めっき、次いで電解銅めっきを施してめっき層３８を形成し、第１および第２のスルーホール内壁に導体部２５、導体部２７（図１）を形成し、導体部２５、２７とスルーホール内壁に露出している対応するプレーン２２、２３の端面とを電気的に接続する。   Next, as shown in FIG. 5, electroless copper plating and then electrolytic copper plating are performed on the inner walls of the first and second through holes and the conductor portion 36 to form a plating layer 38. The conductor portion 25 and the conductor portion 27 (FIG. 1) are formed on the inner wall of the through hole, and the conductor portions 25 and 27 are electrically connected to the end faces of the corresponding planes 22 and 23 exposed on the inner wall of the through hole.

次に、図６に示すように、フォトリソグラフィー工程により、基板１６の導体層３６およびめっき層３８をエッチング加工して、図１および図２に示す、所要の配線パターン１７、第１の外部接続部１８、第２のスルーホール内壁に形成された導体部２７に接続する第２の外部接続部２８、および第１のスルーホール３７内壁に形成された導体部２５に接続するボンディングパターン２６を形成する。   Next, as shown in FIG. 6, the conductor layer 36 and the plating layer 38 of the substrate 16 are etched by a photolithography process, so that the required wiring pattern 17 and the first external connection shown in FIGS. Part 18, a second external connection part 28 connected to the conductor part 27 formed on the inner wall of the second through hole, and a bonding pattern 26 connected to the conductor part 25 formed on the inner wall of the first through hole 37. To do.

次いで、図７に示すように、基板１６に、第１のスルーホール３７上を開口線が通るようにして窓部２１を開口して、パッケージ１０に完成する。この窓部２１は、適宜ルーター等の刃物を用いて切削により形成したり、またはプレスにより打ち抜きして形成することができる。これにより、導体部２５は、半割りにされたスルーホール（断面半円状の凹溝）３７壁面上に形成されることになる。   Next, as shown in FIG. 7, the window portion 21 is opened in the substrate 16 so that the opening line passes through the first through hole 37, and the package 10 is completed. The window portion 21 can be formed by cutting using a cutter such as a router as appropriate, or can be formed by punching with a press. As a result, the conductor portion 25 is formed on the wall surface of the through hole (semicircular groove having a semicircular cross section) 37 that is divided in half.

また、図８に示すように、基板１６表層部の必要個所をソルダーレジスト膜３０で被覆するようにする。
また、図９に示すように、露出している配線パターン１７、第１および第２の外部接続部１８、２８、導体部２５、２７上には、ニッケルめっき、さらに金めっき等の耐食めっき皮膜３９を形成するとよい。
また、第１および第２の外部接続部１８、２８上にはんだボール等のバンプ３２を形成するようにする。 Further, as shown in FIG. 8, necessary portions of the surface layer portion of the substrate 16 are covered with a solder resist film 30.
Further, as shown in FIG. 9, on the exposed wiring pattern 17, the first and second external connection portions 18, 28, and the conductor portions 25, 27, a corrosion-resistant plating film such as nickel plating or gold plating is provided. 39 may be formed.
Further, bumps 32 such as solder balls are formed on the first and second external connection portions 18 and 28.

図１０、図１１は他の実施の形態を示し、図１０はその半導体装置１４の概略的な説明断面図であり、図１１はその半導体装置用パッケージ１０の一部切り欠き斜視図である。図１、図２に示す実施の形態と同一の部材は同一符号を付し、その説明を省略する。
本実施の形態では、基板１６の内層側に設けた接地プレーン２２、電源プレーン２３の他に、基板１６の裏面側に、半円筒状の接続導体部２５に接続する接地プレーンもしくは電源プレーン４２を設けている。この接地プレーンもしくは電源プレーン４２を覆ってソルダーレジスト膜３０が形成されている。本実施の形態のパッケージ１０も、４層の基板１６を用いることにより、図１、図２のパッケージ１０の製造工程（図３〜図９）と同一の工程により製造することができる。 10 and 11 show another embodiment, FIG. 10 is a schematic sectional view of the semiconductor device 14, and FIG. 11 is a partially cutaway perspective view of the semiconductor device package 10. The same members as those in the embodiment shown in FIGS. 1 and 2 are denoted by the same reference numerals, and the description thereof is omitted.
In the present embodiment, in addition to the ground plane 22 and the power plane 23 provided on the inner layer side of the substrate 16, a ground plane or power plane 42 connected to the semi-cylindrical connecting conductor portion 25 is provided on the back surface side of the substrate 16. Provided. A solder resist film 30 is formed so as to cover the ground plane or the power plane 42. The package 10 of the present embodiment can also be manufactured by the same process as the process of manufacturing the package 10 of FIGS. 1 and 2 (FIGS. 3 to 9) by using the four-layer substrate 16. FIG.

図１２、図１３はさらに他の実施の形態を示し、図１２はその半導体装置１４の概略的な説明断面図であり、図１４はその半導体装置用パッケージ１０の一部切り欠き斜視図である。図１、図２に示す実施の形態と同一の部材は同一符号を付し、その説明を省略する。
本実施の形態では、基板１６の内層側に接地プレーン２２、電源プレーン２３を設けず、基板１６の裏面側に、半円筒状の接続導体部２５に接続する接地プレーンもしくは電源プレーン４２を設けている。この接地プレーンもしくは電源プレーン４２を覆ってソルダーレジスト膜３０が形成されている。本実施の形態のパッケージ１０も、２層の基板１６を用いることにより、図１、図２のパッケージ１０の製造工程（図３〜図９）と同一の工程により製造することができる。 12 and 13 show still another embodiment. FIG. 12 is a schematic sectional view of the semiconductor device 14. FIG. 14 is a partially cutaway perspective view of the package 10 for the semiconductor device. . The same members as those in the embodiment shown in FIG. 1 and FIG.
In the present embodiment, the ground plane 22 and the power plane 23 are not provided on the inner layer side of the substrate 16, and the ground plane or the power plane 42 connected to the semi-cylindrical connection conductor portion 25 is provided on the back side of the substrate 16. Yes. A solder resist film 30 is formed so as to cover the ground plane or the power plane 42. The package 10 of the present embodiment can also be manufactured by the same process as the process of manufacturing the package 10 of FIGS. 1 and 2 (FIGS. 3 to 9) by using the two-layer substrate 16.

図１４は、パッケージ１０のさらに他の実施の形態を示す一部切り欠き斜視図である。図１、図２に示す実施の形態と同一の部材は同一符号をもって示した。
本実施の形態でも、パッケージ１０は、基板１６の内層に形成された、接地プレーン２２および電源プレーン２３の少なくとも一方のプレーンと、基板１６の窓部２１の内壁面に形成され、対応するプレーン２２、２３に電気的に接続する複数の接続導体部２５と、窓部２１の縁近傍の基板１６表層部に形成され、接続導体部２５に接続するボンディングパターン２６と、基板１６の表層側に形成され、基板１６に形成されたスルーホール導体部（図１４では省略）２７を介して、対応するプレーン２２、２３に電気的に接続する第２の外部接続部（図１４では省略）２８とを具備することを特徴とする。 FIG. 14 is a partially cutaway perspective view showing still another embodiment of the package 10. The same members as those in the embodiment shown in FIGS. 1 and 2 are denoted by the same reference numerals.
Also in the present embodiment, the package 10 is formed on at least one of the ground plane 22 and the power plane 23 formed on the inner layer of the substrate 16 and the inner wall surface of the window portion 21 of the substrate 16, and the corresponding plane 22. Are formed on the surface layer portion of the substrate 16 near the edge of the window portion 21 and formed on the surface layer side of the substrate 16. And a second external connection portion (not shown in FIG. 14) 28 electrically connected to the corresponding planes 22 and 23 via through-hole conductor portions (not shown in FIG. 14) 27 formed on the substrate 16. It is characterized by comprising.

上記第１の実施の形態では、第１のスルーホール３７を窓部２１の開口縁上に一致する位置に所要配列で形成し、めっきにより導体部２５を形成した後、窓部２１を開口するように形成したが、第２の実施の形態では、第１のスルーホール３７を設けることなく、直接、基板１６に窓部２１を開口し、この窓部２１の壁面全体にめっきにより導体部を形成した後、必要個所に所要複数の独立した導体部２５が残るように、窓部２１の内壁を切削加工等によって除去するようにした。   In the first embodiment, the first through holes 37 are formed in a required arrangement at positions corresponding to the opening edges of the window portion 21, the conductor portion 25 is formed by plating, and then the window portion 21 is opened. However, in the second embodiment, the window portion 21 is directly opened in the substrate 16 without providing the first through hole 37, and the conductor portion is formed on the entire wall surface of the window portion 21 by plating. After the formation, the inner wall of the window portion 21 is removed by cutting or the like so that the required plurality of independent conductor portions 25 remain at the necessary portions.

図１５〜図１９に、図１４に示すパッケージ１０の製造工程を示す。
なお、各図の（ａ）は断面図、（ｂ）は平面図（部分、または全体平面図）である。
まず、図１５に示すように、内層に所要パターンの接地プレーン２２および電源プレーン２３の少なくとも一方のプレーンを有し、少なくとも表層側に銅箔等からなる導体層３６を有する多層の樹脂製基板１６を形成もしくは準備する。この多層の基板１６は、通常の多層プリント配線基板を形成する方法によって製造できる。 15 to 19 show a manufacturing process of the package 10 shown in FIG.
In addition, (a) of each figure is sectional drawing, (b) is a top view (part or whole top view).
First, as shown in FIG. 15, a multilayer resin substrate 16 having at least one of a ground plane 22 and a power plane 23 having a required pattern on the inner layer and a conductor layer 36 made of copper foil or the like on at least the surface layer side. Form or prepare. The multilayer substrate 16 can be manufactured by a method of forming a normal multilayer printed wiring board.

次いで図１６に示すように、基板１６の中央部に窓部２１を開口し、窓部２１の内壁に、対応するプレーン（図示では接地プレーン２２）の端面を露出させる。電源プレーン２３も他の部位における窓部２１内壁に端面が露出する。窓部２１は、ルーター等の刃物による切削加工やプレスによる打ち抜き加工によって形成できる。
また、基板１６の窓部２１となる部位以外の所要部位に、第２のスルーホール３８（図１）を形成し、該第２のスルーホール３８内壁に、対応するプレーンの端面を露出させる。第２のスルーホール３８は、適宜大きさのドリルを用いて明けることができる。 Next, as shown in FIG. 16, a window portion 21 is opened at the center of the substrate 16, and an end face of a corresponding plane (ground plane 22 in the drawing) is exposed on the inner wall of the window portion 21. The end face of the power supply plane 23 is also exposed on the inner wall of the window portion 21 in another part. The window portion 21 can be formed by cutting with a blade such as a router or punching with a press.
Further, the second through hole 38 (FIG. 1) is formed in a required portion other than the portion to be the window portion 21 of the substrate 16, and the end face of the corresponding plane is exposed on the inner wall of the second through hole 38. The second through-hole 38 can be opened using an appropriately sized drill.

次に、窓部２１の内壁、第２のスルーホール３８内壁および導体部３６上に、無電解銅めっき、次いで電解銅めっきを施してめっき層３８を形成し、窓部２１の内壁および第２のスルーホール内壁に導体部２５、導体部２７（図１）を形成し、導体部２５、２７と、窓部２１内壁、第２のスルーホール３８内壁に露出している対応するプレーン２２、２３の端面とを電気的に接続する。
次に、図１７に示すように、フォトリソグラフィー工程により、基板１６の導体層３６およびめっき層３８をエッチング加工して、図１および図１４に示す、所要の配線パターン１７、第１の外部接続部１８、第２のスルーホール内壁に形成された導体部２７に接続する第２の外部接続部２８、および窓部２１内壁に形成された導体部２５に接続するボンディングパターン２６を形成する。 Next, electroless copper plating and then electrolytic copper plating are performed on the inner wall of the window portion 21, the inner wall of the second through hole 38, and the conductor portion 36 to form a plating layer 38. The conductor portion 25 and the conductor portion 27 (FIG. 1) are formed on the inner wall of the through hole, and the corresponding planes 22 and 23 exposed on the conductor portions 25 and 27, the inner wall of the window portion 21, and the inner wall of the second through hole 38 are formed. Electrically connected to the end face of
Next, as shown in FIG. 17, the conductor layer 36 and the plating layer 38 of the substrate 16 are etched by a photolithography process, so that the required wiring pattern 17 and the first external connection shown in FIGS. The bonding pattern 26 connected to the conductor 18, the second external connection portion 28 connected to the conductor portion 27 formed on the inner wall of the second through hole, and the conductor portion 25 formed on the inner wall of the window portion 21 is formed.

次に図１８、図１４に示すように、窓部２１内壁の所要箇所をルーターで切削して凹部４０を形成し、窓部２１内壁に形成された導体部２５を独立した所要複数の導体部２５に分割する。
また、図１８に示すように、基板１６表層部の必要個所をソルダーレジスト膜３０で被覆するようにする。
また、図１９に示すように、露出している配線パターン１７、第１および第２の外部接続部１８、２８、導体部２５、２７上には、ニッケルめっき、さらに金めっき等の耐食めっき皮膜３９を形成するとよい。
また、第１および第２の外部接続部１８、２８上にはんだボール等のバンプ３２を形成するようにする。
以上のようにしてパッケージ１０を製造できる。 Next, as shown in FIG. 18 and FIG. 14, a required portion of the inner wall of the window portion 21 is cut by a router to form a recess 40, and the conductor portions 25 formed on the inner wall of the window portion 21 are independently provided with a plurality of required conductor portions. Divide into 25.
Further, as shown in FIG. 18, necessary portions of the surface layer portion of the substrate 16 are covered with a solder resist film 30.
Further, as shown in FIG. 19, on the exposed wiring pattern 17, the first and second external connection portions 18 and 28, and the conductor portions 25 and 27, a corrosion-resistant plating film such as nickel plating and further gold plating is provided. 39 may be formed.
Further, bumps 32 such as solder balls are formed on the first and second external connection portions 18 and 28.
The package 10 can be manufactured as described above.

図２０、図２１はさらに他の実施の形態を示し、図２０はその半導体装置１４の概略的な説明断面図であり、図２１はその半導体装置用パッケージ１０の一部切り欠き斜視図である。図１４に示す実施の形態と同一の部材は同一符号を付し、その説明を省略する。
本実施の形態では、内層側に接地プレーン２２、電源プレーン２３を設けず、基板１６の裏面側に、接続導体部２５に接続する接地プレーンもしくは電源プレーン４２を設けている。また、接続導体部２５は、窓部２１の内壁に形成した導体部を分離せず、ベタパターンのままとしている。この接地プレーンもしくは電源プレーン４２を覆ってソルダーレジスト膜３０が形成されている。本実施の形態のパッケージ１０も、２層の基板１６を用いることにより、図４のパッケージ１０の製造工程（図１５〜図１９）と同一の工程により製造することができる。
なお、前記のように内層側に接地プレーンあるいは電源プレーンを有する場合にも、ベタパターンの接続導体部２５であってもよい。 20 and 21 show still another embodiment. FIG. 20 is a schematic sectional view of the semiconductor device 14 and FIG. 21 is a partially cutaway perspective view of the package 10 for the semiconductor device. . The same members as those in the embodiment shown in FIG. 14 are denoted by the same reference numerals, and the description thereof is omitted.
In the present embodiment, the ground plane 22 and the power plane 23 are not provided on the inner layer side, and the ground plane or the power plane 42 connected to the connection conductor portion 25 is provided on the back side of the substrate 16. Further, the connection conductor portion 25 does not separate the conductor portion formed on the inner wall of the window portion 21, and remains a solid pattern. A solder resist film 30 is formed so as to cover the ground plane or the power plane 42. The package 10 of the present embodiment can also be manufactured by the same process as the process of manufacturing the package 10 of FIG. 4 (FIGS. 15 to 19) by using the two-layer substrate 16.
Note that the connection conductor portion 25 having a solid pattern may be used even when the ground plane or the power supply plane is provided on the inner layer side as described above.

なお、上記各実施の形態では、１つのパッケージ１０を製造する例で示したが、実際には、多数個取りの基板１６に複数個のパッケージ１０を作りこみ、各パッケージ１０に半導体チップ１２を搭載し、必要なワイヤボンディング、樹脂封止等の工程を行った後、個片の半導体装置に切断分離するようにする。   In each of the above-described embodiments, an example is shown in which one package 10 is manufactured. However, actually, a plurality of packages 10 are formed on a multi-piece substrate 16, and a semiconductor chip 12 is mounted on each package 10. After mounting and performing necessary steps such as wire bonding and resin sealing, the semiconductor device is cut and separated into individual semiconductor devices.

半導体装置の説明断面図である。It is explanatory sectional drawing of a semiconductor device. 半導体装置用パッケージの一部切り欠き斜視図である。It is a partially cutaway perspective view of a package for a semiconductor device. 図３〜図９はパッケージの製造工程図を示し、図３（ａ）は多層の基板の説明断面図、（ｂ）は部分平面図、3 to 9 show manufacturing process diagrams of the package, FIG. 3A is an explanatory sectional view of a multilayer substrate, FIG. 3B is a partial plan view, 図４（ａ）は、基板にスルーホールを形成した状態の説明断面図、（ｂ）は部分平面図、FIG. 4A is an explanatory cross-sectional view of a state in which a through hole is formed in the substrate, and FIG. 4B is a partial plan view. 図５（ａ）は、基板にスルーホールめっきを施した状態の説明断面図、（ｂ）は部分平面図、FIG. 5 (a) is an explanatory cross-sectional view of a state in which through-hole plating is applied to the substrate, (b) is a partial plan view, 図６（ａ）は、エッチング加工して配線パターン等を形成した状態の説明断面図、（ｂ）は部分平面図、6A is an explanatory cross-sectional view of a state where a wiring pattern or the like is formed by etching, and FIG. 6B is a partial plan view. 図７（ａ）は、基板に窓部を開口した状態の説明断面図、（ｂ）は部分平面図、FIG. 7A is an explanatory cross-sectional view of a state in which a window is opened in the substrate, and FIG. 7B is a partial plan view. 図８（ａ）は、ソルダーレジスト膜を形成した状態の説明断面図、（ｂ）は部分平面図、FIG. 8A is an explanatory sectional view of a state in which a solder resist film is formed, and FIG. 8B is a partial plan view. 図９（ａ）は、接続導体部等に耐食めっき皮膜を形成した状態の説明断面図、（ｂ）は全体平面図である。FIG. 9A is an explanatory cross-sectional view of a state in which a corrosion-resistant plating film is formed on the connection conductor portion and the like, and FIG. 9B is an overall plan view. 他の実施の形態を示す半導体装置の説明断面図である。It is explanatory sectional drawing of the semiconductor device which shows other embodiment. 図１０の半導体装置のパッケージの部位の一部切り欠き斜視図である。FIG. 11 is a partially cutaway perspective view of a portion of the package of the semiconductor device of FIG. 10. さらに他の実施の形態を示す半導体装置の説明断面図である。It is explanatory sectional drawing of the semiconductor device which shows other embodiment. 図１２の半導体装置のパッケージの部位の一部切り欠き斜視図である。FIG. 13 is a partially cutaway perspective view of a portion of the package of the semiconductor device of FIG. 12. 半導体装置用パッケージの第２の実施の形態を示す一部切り欠き斜視図である。It is a partially cutaway perspective view showing a second embodiment of a package for a semiconductor device. 図１５〜図１９は第２の実施の形態のパッケージの製造工程図を示し、図１５（ａ）は多層の基板の説明断面図、（ｂ）は部分平面図、15 to 19 show manufacturing process diagrams of the package of the second embodiment, FIG. 15 (a) is an explanatory sectional view of a multilayer substrate, (b) is a partial plan view, 図１６（ａ）は、基板に窓部を開口した状態の説明断面図、（ｂ）は部分平面図、FIG. 16A is an explanatory cross-sectional view of a state in which a window is opened in the substrate, and FIG. 16B is a partial plan view. 図１７（ａ）は、エッチング加工して配線パターン等を形成した状態の説明断面図、（ｂ）は部分平面図、FIG. 17A is an explanatory sectional view showing a state in which a wiring pattern or the like is formed by etching, and FIG. 17B is a partial plan view. 図１８（ａ）は、ソルダーレジスト膜を形成した状態の説明断面図、（ｂ）は部分平面図、FIG. 18A is an explanatory sectional view of a state in which a solder resist film is formed, and FIG. 18B is a partial plan view. 図１９（ａ）は、接続導体部等に耐食めっき皮膜を形成した状態の説明断面図、（ｂ）は全体平面図である。FIG. 19A is an explanatory cross-sectional view of a state in which a corrosion-resistant plating film is formed on the connection conductor portion and the like, and FIG. 19B is an overall plan view. またさらに他の実施の形態を示す半導体装置の説明断面図である。It is an explanatory sectional view of a semiconductor device showing still another embodiment. 図２０の半導体装置のパッケージの部位の一部切り欠き斜視図である。FIG. 21 is a partially cutaway perspective view of a portion of the package of the semiconductor device of FIG. 20.

符号の説明Explanation of symbols

１０ 半導体装置用パッケージ
１２ 半導体チップ
１４ 半導体装置
１６ 基板
１７ 配線パターン
１８ 第１の外部接続部
１９ 端子部
２０ ワイヤ
２１ 窓部
２２ 接地プレーン
２３ 電源プレーン
２５ 接続導体部
２６ ボンディングパターン
２７ スルーホール導体部
２８ 第２の外部接続部
３０ ソルダーレジスト膜
３２ バンプ
３５ 封止樹脂
３６ 導体層
３７ スルーホール
３８ 耐食めっき皮膜
４２ 接地プレーンもしくは電源プレーン
DESCRIPTION OF SYMBOLS 10 Semiconductor device package 12 Semiconductor chip 14 Semiconductor device 16 Board | substrate 17 Wiring pattern 18 1st external connection part 19 Terminal part 20 Wire 21 Window part 22 Ground plane 23 Power supply plane 25 Connection conductor part 26 Bonding pattern 27 Through-hole conductor part 28 Second external connection portion 30 Solder resist film 32 Bump 35 Sealing resin 36 Conductor layer 37 Through hole 38 Corrosion-resistant plating film 42 Ground plane or power plane

Claims (12)

基板表層側に所要配線パターンと、該配線パターンを外部に接続するための第１の外部接続部とが形成され、基板の所要部位に、基板裏面側に搭載される半導体チップの端子部が臨み、該端子部と表層側の配線パターンとの間を電気的に接続するワイヤが引き出される窓部が開口された半導体装置用パッケージにおいて、
前記基板に形成された、接地プレーンおよび電源プレーンの少なくとも一方のプレーンと、
前記基板の窓部内壁面に形成され、対応する前記プレーンに電気的に接続する接続導体部と、
前記窓部の縁近傍の基板表層部に形成され、前記接続導体部に接続するボンディングパターンと、
前記基板の表層側に形成され、基板に形成されたスルーホール導体部を介して、対応する前記プレーンに電気的に接続する第２の外部接続部とを具備することを特徴とする半導体装置用パッケージ。 A required wiring pattern and a first external connection portion for connecting the wiring pattern to the outside are formed on the substrate surface layer side, and a terminal portion of a semiconductor chip mounted on the back side of the substrate faces a required portion of the substrate. In the package for a semiconductor device in which a window part from which a wire for electrically connecting the terminal part and the wiring pattern on the surface layer side is drawn is opened,
At least one of a ground plane and a power plane formed on the substrate;
A connection conductor portion formed on the inner wall surface of the window portion of the substrate and electrically connected to the corresponding plane;
A bonding pattern formed on the substrate surface layer near the edge of the window, and connected to the connection conductor;
A second external connection portion formed on a surface layer side of the substrate and electrically connected to the corresponding plane through a through-hole conductor portion formed on the substrate; package. 前記接続導体部が、前記窓部内壁面全体に形成された導体部の一部が除去されることによって所用複数の独立した接続導体部に形成されていることを特徴とする請求項１記載の半導体装置用パッケージ。   2. The semiconductor according to claim 1, wherein the connection conductor portion is formed into a plurality of independent connection conductor portions by removing a part of the conductor portion formed on the entire inner wall surface of the window portion. Equipment package. 前記窓部内壁面の部位に凹溝が形成され、前記接続導体部が、該凹溝壁面に形成されていることを特徴とする請求項１記載の半導体装置用パッケージ。   2. The package for a semiconductor device according to claim 1, wherein a groove is formed in a portion of the inner wall surface of the window, and the connection conductor is formed on the wall surface of the groove. 前記第１および第２の外部接続部にバンプが形成されていることを特徴とする請求項１〜３いずれか１項記載の半導体装置用パッケージ。   The semiconductor device package according to claim 1, wherein bumps are formed on the first and second external connection portions. 請求項１〜４いずれか１項記載の半導体装置用パッケージの基板裏面側に、半導体チップが搭載され、基板の前記窓部に臨む半導体チップの端子部のうちの所要端子部と、基板表層側に形成された前記配線パターンとの間、および前記半導体チップの端子部のうちの所要端子部と、対応する前記ボンディングパターンとの間がワイヤにより電気的に接続されていることを特徴とする半導体装置。   A semiconductor chip is mounted on the back side of the substrate of the semiconductor device package according to any one of claims 1 to 4, and a required terminal portion of the terminal portions of the semiconductor chip facing the window portion of the substrate, and a substrate surface layer side The semiconductor device is characterized in that a wiring is electrically connected to the wiring pattern, a required terminal portion of the terminal portions of the semiconductor chip, and the corresponding bonding pattern by wires. apparatus. 前記半導体チップとワイヤとが封止樹脂により封止されていることを特徴とする請求項５記載の半導体装置。   6. The semiconductor device according to claim 5, wherein the semiconductor chip and the wire are sealed with a sealing resin. 基板表層側に所要配線パターンと、該配線パターンを外部に接続するための第１の外部接続部とが形成され、基板の所要部位に、基板裏面側に搭載される半導体チップの端子部が臨み、該端子部と表層側の配線パターンとの間を電気的に接続するワイヤが引き出される窓部が開口された半導体装置用パッケージの製造方法において、
接地プレーンおよび電源プレーンの少なくとも一方のプレーンを有し、表層側に導体層を有する多層の基板を形成する工程と、
該基板の、形成すべき前記窓部の開口縁に一致する位置に、所要数の第１のスルーホールを形成し、該第１のスルーホール内壁に、対応する前記プレーンの端面を露出させる工程と、
前記基板の前記窓部となる部位以外の部位に、第２のスルーホールを形成し、該第２のスルーホール内壁に、対応する前記プレーンの端面を露出させる工程と、
前記第１および第２のスルーホール内壁にめっきにより導体部を形成し、該導体部とスルーホール内壁に露出している前記プレーンの端面とを電気的に接続する工程と、
前記基板の前記導体層をエッチング加工して、前記配線パターン、前記第１の外部接続部、前記第２のスルーホール内壁に形成された導体部に接続する第２の外部接続部、および前記第１のスルーホール内壁に形成された導体部に接続するボンディングパターンを形成するエッチング工程と、
前記基板に、前記第１のスルーホール上を開口線が通るようにして前記窓部を開口する工程とを具備することを特徴とする半導体装置用パッケージの製造方法。 A required wiring pattern and a first external connection portion for connecting the wiring pattern to the outside are formed on the substrate surface layer side, and a terminal portion of a semiconductor chip mounted on the back side of the substrate faces a required portion of the substrate. In the method for manufacturing a package for a semiconductor device in which a window part through which a wire for electrically connecting the terminal part and the wiring pattern on the surface layer side is drawn is opened,
Forming a multi-layer substrate having at least one of a ground plane and a power plane and having a conductor layer on the surface layer side;
Forming a required number of first through holes at positions corresponding to the opening edges of the windows to be formed on the substrate, and exposing end faces of the corresponding planes on the inner walls of the first through holes; When,
Forming a second through hole in a portion other than the portion to be the window portion of the substrate, and exposing an end face of the corresponding plane on the inner wall of the second through hole;
Forming a conductor portion by plating on the inner wall of the first and second through holes, and electrically connecting the conductor portion and an end surface of the plane exposed on the inner wall of the through hole;
Etching the conductor layer of the substrate to form the wiring pattern, the first external connection portion, a second external connection portion connected to a conductor portion formed on the inner wall of the second through hole, and the first An etching step of forming a bonding pattern connected to a conductor formed on the inner wall of one through hole;
And a step of opening the window portion so that an opening line passes through the first through hole in the substrate. 前記第１のスルーホール、第２のスルーホールを同一の工程により形成することを特徴とする請求項７記載の半導体装置用パッケージの製造方法。   8. The method of manufacturing a package for a semiconductor device according to claim 7, wherein the first through hole and the second through hole are formed by the same process. 前記第１および第２の外部接続部上にバンプを形成する工程を含むことを特徴とする請求項７または８記載の半導体装置用パッケージの製造方法。   9. The method for manufacturing a package for a semiconductor device according to claim 7, further comprising a step of forming bumps on the first and second external connection portions. 基板表層側に所要配線パターンと、該配線パターンを外部に接続するための第１の外部接続部とが形成され、基板の所要部位に、基板裏面側に搭載される半導体チップの端子部が臨み、該端子部と表層側の配線パターンとの間を電気的に接続するワイヤが引き出される窓部が開口された半導体装置用パッケージの製造方法において、
接地プレーンおよび電源プレーンの少なくとも一方のプレーンを有し、表層側に導体層を有する多層の基板を形成する工程と、
該基板の中央部に前記窓部を開口し、該窓部内壁に、対応する前記プレーンの端面を露出させる工程と、
前記基板の前記窓部となる部位以外の部位に、第２のスルーホールを形成し、該第２のスルーホール内壁に、対応する前記プレーンの端面を露出させる工程と、
前記窓部および第２のスルーホール内壁にめっきにより導体部を形成し、該導体部とスルーホール内壁に露出している前記プレーンの端面とを電気的に接続する工程と、
前記基板の前記導体層をエッチング加工して、前記配線パターン、前記第１の外部接続部、前記第２のスルーホール内壁に形成された導体部に接続する第２の外部接続部、および前記窓部内壁に形成された導体部に接続するボンディングパターンを形成するエッチング工程とを具備することを特徴とする半導体装置用パッケージの製造方法。 A required wiring pattern and a first external connection portion for connecting the wiring pattern to the outside are formed on the substrate surface layer side, and a terminal portion of a semiconductor chip mounted on the back side of the substrate faces a required portion of the substrate. In the method for manufacturing a package for a semiconductor device in which a window part through which a wire for electrically connecting the terminal part and the wiring pattern on the surface layer side is drawn is opened,
Forming a multi-layer substrate having at least one of a ground plane and a power plane and having a conductor layer on the surface layer side;
Opening the window at the center of the substrate and exposing the end face of the corresponding plane on the inner wall of the window;
Forming a second through hole in a portion other than the portion to be the window portion of the substrate, and exposing an end face of the corresponding plane on the inner wall of the second through hole;
Forming a conductor portion by plating on the window portion and the inner wall of the second through hole, and electrically connecting the conductor portion and an end surface of the plane exposed on the inner wall of the through hole;
Etching the conductor layer of the substrate to connect the wiring pattern, the first external connection portion, the second external connection portion connected to the conductor portion formed on the inner wall of the second through hole, and the window And an etching process for forming a bonding pattern connected to the conductor formed on the inner wall of the part. 前記窓部内壁に形成された導体部を一部除去し、所要複数の独立した導体部に分割する工程を具備することを特徴とする請求項１０記載の半導体装置用パッケージの製造方法。   The method for manufacturing a package for a semiconductor device according to claim 10, further comprising a step of removing a part of the conductor formed on the inner wall of the window and dividing it into a plurality of required independent conductors. 前記第１および第２の外部接続部上にバンプを形成する工程を含むことを特徴とする請求項１０または１１記載の半導体装置用パッケージの製造方法。
12. The method of manufacturing a package for a semiconductor device according to claim 10, further comprising a step of forming bumps on the first and second external connection portions.
JP2006035791A 2005-02-18 2006-02-13 Package for semiconductor device, method of manufacturing the same, and semiconductor device Pending JP2006261652A (en)

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