JP2006128249A - Package for housing semiconductor element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a package for housing semiconductor element that can cope with the increase of the signal transmitting speed of a conductor wiring pattern for signal while using a plated lead wire for electroplating, and to provide a method of manufacturing the package. <P>SOLUTION: The package 10 for housing semiconductor element has a plurality of conductor wiring patterns 12 which are respectively electrically disconnected from a resin base material 11 having a nearly rectangular shape, and electroplated coating films on the patterns 12. A plated wire collecting pattern 19 is connected to plated wires 18 extended from the conductor wiring patterns 12 for respectively forming plated coating films of the conductor wiring patterns 12, and short-circuits each pattern 12. The pattern 19 is provided at the central part, and the plated lead wires 20 connected to the plated wire collecting pattern 19 are extended to the outer peripheral side section. The package 10 also has a notch 21 from which the plated wire collecting pattern 19 is removed by excavation after the plated coating film is formed on each conductor wiring pattern 12 through the plated lead wires 20, plated wire collecting pattern 19, and plated wires 18. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a package for housing a semiconductor element for mounting a semiconductor element and a method for manufacturing the same, and more particularly, a package for housing a semiconductor element having a conductor wiring pattern that can cope with high-speed signal propagation of the semiconductor element and the package thereof. It relates to a manufacturing method.

  In recent years, semiconductor element storage packages made of a resin base material for mounting semiconductor elements have been developed with higher density and higher speed of semiconductor elements, mounting of semiconductor elements, lower cost, lower impedance, and equipment. From the viewpoint of downsizing the external dimensions for downsizing, for example, a BGA (Ball Grid Array) type or the like that can increase the arrangement density of the conductor wiring pattern formed on the package is often used. .

  As shown in FIG. 5, a conventional BGA type semiconductor element storage package 50 has a large number for connecting to one surface of a substantially rectangular resin base material 51 with a semiconductor element 52 and bonding wires 53 in a plan view. A conductive wiring pattern 55 made of Cu or the like having a bonding pad 54 is provided. The package 50 for housing a semiconductor element has a conductor wiring pattern 55 including a large number of external connection terminal pads 57 for connecting external connection terminals 56 made of solder balls or the like to the other surface of the resin base material 51. Yes. The bonding pad 54 and the external connection terminal pad 57 are connected via the conductor wiring pattern 55 and the through-hole conductor 58 to form an electrically conductive state. The bonding pads 54 and the external connection terminal pads 57 are formed by exposing predetermined portions of the conductor wiring pattern 55 of the solder resist film 59 formed on both surfaces of the resin base 51 including the conductor wiring pattern 55 as openings. . The bonding pad 54 and the external connection terminal pad 57 exposed from the opening of the solder resist film 59 are usually used to improve the bonding property of the bonding wire 53 and prevent the surface from being oxidized to improve the solder ball welding property. A Ni plating film and an Au plating film (not shown) are formed by a technique of electrolytic plating formed by conducting in a plating bath. Then, after the semiconductor element 52 is mounted on the semiconductor element storage package 50, the semiconductor element 52 is hermetically sealed with the sealing resin 60.

  As shown in FIG. 6, the manufacturing method of the semiconductor element storage package 50 is usually formed as an aggregate of a large number of semiconductor element storage packages 50 on a large, substantially rectangular panel-shaped resin substrate 51a. From the dummy portion 61 around each semiconductor element storage package 50 in the assembly to each semiconductor element storage package 50, a plating tie bar wire 62 and an individual semiconductor element storage from the plating tie bar wire 62. A plating lead line 63 extending to each conductor wiring pattern 55 of the package 50 is provided. The Ni plating film and the Au plating film are energized from the plating tie bar wire 62 to the respective conductor wiring patterns 55 through the plating lead wires 63, and are previously formed by covering portions that do not require plating. It is formed on the conductor wiring pattern 55 such as the bonding pad 54 exposed from the opening of the resist film 59 and the external connection terminal pad 57. Each semiconductor element storage package 50 is formed by cutting along the cutting line 64 from the assembly.

  As a package for housing a semiconductor element, there has been proposed a package in which plating lead lines are concentrated and led to one end face of a rectangular flat insulating base (for example, see Patent Document 1).

Japanese Patent Laid-Open No. 5-326748

However, the conventional semiconductor element storage package and the manufacturing method thereof as described above have the following problems.
(1) With respect to a package for housing a semiconductor element, with the recent increase in the speed of semiconductor elements, a package specification that can accommodate a conductor wiring pattern for signals is required. However, since the conventional package for housing a semiconductor element requires a plating lead wire for forming a plating film by a method of electrolytic plating in which each conductor wiring pattern is energized in a plating bath. There is a problem that propagation of high-speed signals is hindered by the electrostatic capacity generated in the plated lead lines connected to the conductor wiring pattern in the package after being made. In addition, in the semiconductor element storage package, since the conductor wiring pattern may be formed near the center of the package, it is difficult to shorten the plating lead line extending from the outer periphery in the conventional semiconductor element storage package. Yes, the electrostatic capacity generated in the plated lead wire hinders high-speed signal propagation.
(2) The plated lead wire is necessary for forming the plating film of the conductor wiring pattern by electrolytic plating. However, as a method of eliminating the plated lead wire, there is no chemical plating that does not energize the conductor wiring pattern. A method of forming a plating film by a method using electrolytic plating is conceivable. However, since the plating film by electroless plating cannot secure a sufficient film thickness, the adhesive strength when a solder ball as an external connection terminal is bonded to an external connection terminal pad, for example, a conductor wiring pattern is lowered. Or the connection strength when bonding wires are connected to the bonding pads may be reduced.
(3) In the case where the lead wires are led out to one end surface of the rectangular flat insulating base in the semiconductor element housing package, the lead wires are necessary and the plating lead wires become longer. This hinders the propagation of high-speed signals due to the capacitance generated in the plated lead lines.
SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and a package for housing a semiconductor element that can cope with a high-speed signal propagation of a conductor wiring pattern for a signal while using a plated lead wire for electrolytic plating, and its manufacture It aims to provide a method.

A package for housing a semiconductor element according to the present invention that meets the above object has a plurality of conductor wiring patterns that are electrically disconnected from each other on a substantially rectangular resin base material, and is formed on the conductor wiring pattern by electrolytic plating. In a package for housing a semiconductor element having a plating film, a plating wire connected to a plating wire extending from each of the conductor wiring patterns for forming the plating film on each of the conductor wiring patterns, and short-circuiting each conductor wiring pattern It has a collective pattern in the center and has a plated lead wire that extends to the outer peripheral side to connect with the plated wire collective pattern, and each conductor wiring pattern has a plated lead wire, a plated wire aggregate pattern, and a plated wire. After the plating film is formed, the plating wire assembly pattern has a notch portion that is drilled and removed.
Here, in the semiconductor element storage package, the plated lead wire is connected to the power supply conductor wiring pattern in the conductor wiring pattern, and the power supply conductor wiring pattern is connected to the plated wire assembly pattern via the plating wire. Is good.

The method for manufacturing a package for housing a semiconductor element according to the present invention in accordance with the above object comprises an assembly in which a plurality of individual pieces are arranged on a large, substantially rectangular panel-shaped resin base material via a dummy portion. A package for housing a semiconductor element, in which a plurality of conductor wiring patterns that are electrically disconnected from each other are provided on an individual body, and a plating film is formed by electrolytic plating via a plating tie bar wire provided on each dummy wiring portion of each conductor wiring pattern In the manufacturing method, a plating wire assembly pattern for short-circuiting each of the conductor wiring patterns in connection with the plating wires extending from the respective conductor wiring patterns of the individual pieces is provided in the center of each individual piece, Plating lead wires connected to each plating wire assembly pattern are extended to the plating tie bar wires through the outer periphery of each piece. A step of providing a plating tie bar wire, a plating lead wire of each individual piece, a plating wire assembly pattern, and a step of forming a plating film on the conductor wiring pattern of each individual piece by electrolytic plating through the plating wire; In order to cut and form the notch portions by drilling and removing the respective plated wire aggregate patterns of the individual pieces, and electrically disconnecting each of the conductor wiring patterns of the individual pieces from each other and making the individual pieces into individual pieces And cutting along the cutting line.
Here, the manufacturing method of the semiconductor element storage package is such that each plating lead wire extending to the plating tie bar wire is connected to the power supply conductor wiring pattern in each conductor wiring pattern of the individual piece. It is preferable to provide a plated wire extending from the power supply conductor wiring pattern and connected to the individual plated wire assembly pattern.

The package for housing a semiconductor element according to claim 1 or claim 2 dependent thereon is connected to a plating wire extending from each of the conductor wiring patterns for forming a plating film on each of the conductor wiring patterns, A plating wire assembly pattern for short-circuiting the conductor wiring pattern of the central portion, and a plating lead wire connected to the plating wire assembly pattern is extended to the outer peripheral side portion. After the plated wire assembly pattern and the plating film is formed via the plated wire, the plated wire assembly pattern has a notch portion that is drilled and removed, so that a plated lead wire connected to each conductor wiring pattern is required. Without plating, the plating film thickness can be optimized and plating that connects with each conductor wiring pattern The shorter can be the length may correspond to the speed of signal propagation conductor wiring patterns for signal.
In particular, in the package for housing a semiconductor element according to claim 2, the plated lead wire is connected to the power supply conductor wiring pattern in the conductor wiring pattern, and the power supply conductor wiring pattern is connected to the plating wire assembly pattern via the plating wire. Therefore, the plated lead wire is connected to the conductor wiring pattern for power supply that is not affected by the capacitance and connected to the plated wire assembly pattern, so that the plated lead wire is connected to other conductor wiring patterns. Therefore, it is possible to avoid the short circuiting with other conductor wiring patterns and to easily arrange them.

The method for manufacturing a package for housing a semiconductor element according to claim 3 or claim 4 dependent thereon is connected to a plated wire extending from each conductor wiring pattern of the individual piece to short-circuit each of the conductor wiring patterns. A plating wire assembly pattern is provided in the center of each individual piece, and a plating lead wire connected to each plating wire assembly pattern passes through the outer peripheral side of each individual piece and extends to the plating tie bar wire. And a step of forming a plating film on the conductor wiring pattern of each individual piece by electrolytic plating through the plated tie bar wire, the plated lead wire of each individual piece, the plated wire assembly pattern, and the plated wire And cutting and removing the plated wire assembly patterns of the individual pieces to form notches, and electrically connecting the conductor wiring patterns of the individual pieces to each other. In addition, there is a step of cutting along the cutting lines for separating the assembly into individual pieces, so that a plating film is formed by electroplating without using the plating lead lines connected to each conductor wiring pattern. In addition, it is possible to provide a method for manufacturing a package for housing a semiconductor element, which can cope with high-speed signal propagation of a signal conductor wiring pattern.
In particular, the method of manufacturing a package for housing a semiconductor element according to claim 4 is characterized in that each lead-out line of the individual piece extending to the plating tie-bar line is a conductor wiring for power supply in each conductor wiring pattern of the individual piece. Connected to the power supply conductor wiring pattern and connected to the power supply conductor wiring pattern that is not affected by the capacitance. It is possible to provide a method of manufacturing a package for housing a semiconductor element, in which a plated lead wire connected to a line assembly pattern can be arranged without being short-circuited with another conductor wiring pattern.

Subsequently, the best mode for carrying out the present invention will be described with reference to the accompanying drawings to provide an understanding of the present invention.
1A and 1B are explanatory views of a package for housing a semiconductor element according to an embodiment of the present invention. FIG. 2 is an explanatory view of a modification of the package for housing a semiconductor element. FIGS. 4A and 4B are partially enlarged plan views on the upper surface side for explaining a method for manufacturing the semiconductor element housing package, and FIGS. It is a partial expanded longitudinal cross-sectional view for demonstrating a method.

  A semiconductor element housing package according to an embodiment of the present invention will be described with reference to FIGS. 1 (A) and 1 (B). Here, FIG. 1A is a partially enlarged plan view of the semiconductor element storage package as viewed from above, and FIG. 1B is a bottom view of the semiconductor element storage package in a pattern form seen through the bottom surface. FIG. As shown in FIGS. 1A and 1B, a semiconductor element storage package 10 according to an embodiment of the present invention is cut into a single piece from an assembly of a plurality of single pieces. It is. The semiconductor element storage package 10 is in a disconnected state in which the substantially rectangular resin base material 11 is not electrically short-circuited with each other, and the patterns formed on both surfaces of the resin base material 11 are electrically connected to each other. It has a plurality of conductor wiring patterns 12 in a state. A package 10 for housing a semiconductor element is usually a conductive wiring pattern 12 on the upper surface side of a resin base material 11 and a plurality of bonding pads 13 for bonding wire connection for electrically connecting the semiconductor element and the package. have. Further, the semiconductor element storage package 10 has a plurality of external connection terminal joints as conductor wiring patterns 12 for connecting to a board or the like on the lower surface side of the resin base material 11 so as to be electrically connected to the outside. An external connection terminal pad 14 is provided. Further, the semiconductor element storage package 10 has a circuit wiring 15 and a resin base material 11 in order to electrically connect the bonding pads 13 and the external connection terminal pads 14 as the respective conductor wiring patterns 12. The through-hole conductor 16 is formed so as to penetrate therethrough. For this conductor wiring pattern 12, a desired portion of the conductor wiring pattern 12 exposed from the openings of the solder resist film 17 formed on both surfaces of the resin substrate 11 by using an electroplating technique in which current is supplied in a plating bath. For example, a plating film is formed on the bonding pad 13 and the external connection terminal pad 14.

  In the semiconductor element storage package 10, in order to form a plating film on each of the plurality of conductor wiring patterns 12, the plating wire 18 extending from each of the bonding pads 13 on the upper surface side of the plurality of conductor wiring patterns 12 is in the middle. The adjacent plated wires 18 are connected without being short-circuited, and a plated wire assembly pattern 19 capable of short-circuiting all of the plurality of conductor wiring patterns 12 after being connected is provided in the central portion on the upper surface side of the resin substrate 11. is doing. Furthermore, on the upper surface side of the resin base material 11, there is a plating lead wire 20 that connects one end to the plated wire assembly pattern 19 and extends the other end to the outer peripheral side of the resin base material 11. ing. Solder resist films are formed on both surfaces of the resin base material 11 by performing electrolytic plating on the plurality of conductor wiring patterns 12 through the plated lead wires 20, the plated wire assembly patterns 19, and the plated wires 18. A plating film is formed on the conductive wiring pattern 12 such as the bonding pad 13 exposed from the opening 17 and the external connection terminal pad 14. The package 10 for housing a semiconductor element has a notch 21 at the center of the resin substrate 11 by forming and removing the plated wire assembly pattern 19 together with the resin substrate 11 after the plating film is formed. is doing.

  With reference to FIG. 2, a description will be given of a semiconductor element storage package which is a modification of the semiconductor element storage package 10 according to the embodiment of the present invention. Here, FIG. 2 is a partially enlarged plan view of a semiconductor element accommodation package as a modification of the semiconductor element accommodation package 10 as viewed from above. As shown in FIG. 2, a semiconductor element storage package 10a, which is a modified example of the semiconductor element storage package 10 according to the embodiment of the present invention, includes a plurality of individual pieces as in the case of the semiconductor element storage package 10. It is cut from the assembly into individual pieces. The semiconductor element storage package 10a is in a disconnected state in which the substantially rectangular resin base material 11 is not electrically short-circuited with each other, and a pattern formed on one surface of the resin base material 11 is electrically A plurality of conductor wiring patterns 12a that are electrically conductive are provided. The semiconductor element storage package 10a is usually a plurality of bonding wires for connecting a bonding wire for electrically connecting the semiconductor element and the package to one surface side of the resin base material 11 as the conductor wiring pattern 12a. A pad 13 and a plurality of external connection terminal pads 14 for joining external connection terminals for connecting to a board or the like and being electrically connected to the outside are provided. Further, the semiconductor element storage package 10a has circuit wirings 15a as the conductor wiring patterns 12a in order to electrically connect the bonding pads 13 and the external connection terminal pads 14. For this conductor wiring pattern 12a, the desired conductor wiring pattern 12a exposed from the opening of the solder resist film 17 formed on one surface of the resin substrate 11 by using an electroplating technique in which current is supplied in a plating bath. For example, a plating film is formed on the bonding pad 13 and the external connection terminal pad 14.

  In the semiconductor element storage package 10a, in order to form a plating film on each of the plurality of conductor wiring patterns 12a, the plating wire 18 extended from each of the bonding pads 13 on one surface side of the plurality of conductor wiring patterns 12a. Are connected without short-circuiting between adjacent plated wires 18 in the middle, and have a plated wire assembly pattern 19 that can short-circuit all of the plurality of conductor wiring patterns 12a after being connected. Further, on the same surface side of the resin base material 11, there is a plated lead wire 20 that connects one end to the plated wire assembly pattern 19 and extends the other end to the outer peripheral side of the resin base material 11. is doing. Solder resist formed on the same surface of the resin base material 11 is subjected to electrolytic plating on each of the plurality of conductor wiring patterns 12a via the plated lead wires 20, the plated wire assembly patterns 19, and the plated wires 18. A plating film is formed on the conductor wiring pattern 12 a such as the bonding pad 13 exposed from the opening of the film 17 and the external connection terminal pad 14. The semiconductor element storage package 10a has a notch 21 at the center of the resin substrate 11 by forming and removing the plated wire assembly pattern 19 together with the resin substrate 11 after the plating film is formed. is doing.

  In the semiconductor element housing packages 10, 10 a, the plated lead wire 20 is connected to the power supply conductor wiring pattern in the conductor wiring patterns 12, 12 a, and the plated wire assembly pattern is connected to the power supply conductor wiring pattern via the plating wire 18. 19 may be connected. Since the power supply conductor wiring pattern is not affected by the electrostatic capacity unlike the signal conductor wiring pattern, the power supply conductor wiring pattern can be used as an extension of the plating lead line 20. The plated lead wire 20 can be avoided from being arranged between the adjacent conductor wiring patterns 12 and 12a at a narrow interval, and can be easily arranged by preventing a short circuit with the conductor wiring patterns 12 and 12a. .

Next, with reference to FIGS. 3A and 3B, a method for manufacturing the semiconductor element housing packages 10 and 10a (hereinafter, represented by the symbols used in the semiconductor element housing package 10 representatively) will be described. . 3 (A) and 3 (B) are shown in the form of the semiconductor element housing package 10 and are a partially enlarged plan view on the upper surface side and a state where the external connection terminal pads 14 on the lower surface side are also seen through. It is also illustrated in FIG.
As shown in FIG. 3 (A), each of the semiconductor element storage packages 10 is formed into a large, substantially rectangular panel-shaped resin base material 22 before the individual semiconductor element storage packages 10 are produced. A plurality of individual packages are arranged as a plurality of individual packages arranged via dummy portions 23 provided around each of them. Each piece of the assembly is provided with a plurality of conductor wiring patterns 12 that are electrically disconnected from each other, and the conductor wiring patterns 12 are provided via the plating tie bar wires 24 provided in the above-described dummy portion 23. A plating film is applied by electrolytic plating. In order to form this plating film, first, a plated wire assembly pattern for short-circuiting each of the conductor wiring patterns 12 by connecting with the plating wires 18 extending from the respective conductor wiring patterns 12 in the individual piece. 19 is provided at the center of the individual piece. Further, from the plated wire assembly pattern 19, a plated lead wire 20 connected to the plated wire aggregate pattern 19 is provided so as to extend to the plated tie bar wire 24 through the outer peripheral side portion of the individual piece. A solder resist film 17 is provided on the surface of each piece so that the bonding pads 13 and the external connection terminal pads 14 are exposed from the openings. The solder resist film 17 may also be provided on the plated wire assembly pattern 19 or the plated tie bar wire 24.

  Next, the panel-shaped resin base material 22 is provided with an electroplating jig on the electrode terminal portion of the plating tie bar wire 24 provided so as to surround the individual pieces around the dummy portions 23 around the individual pieces. The electrode terminals are connected and immersed in the plating bath. Then, the current applied from the electrode terminal is applied to the individual conductive wiring pattern 12 via the plating tie bar wire 24, the respective plated lead wire 20, the plated wire assembly pattern 19, and the plated wire 18. Is energized. The energization in this plating bath forms a plating film by electrolytic plating on a desired portion of the conductive wiring pattern 12 exposed from the opening of the solder resist film 17, for example, the bonding pad 13 or the external connection terminal pad 14. .

  Next, as shown in FIG. 3 (B), the panel-like resin base material 22 is punched and removed by using a stamping die, a router processing machine, or the like by punching out the plated wire assembly pattern 19 of each piece. And the notch part 21 is formed in the center part of each piece. Due to the notches 21, the individual conductor wiring patterns 12 are electrically disconnected from each other. Each individual piece in the assembly is cut along a cutting line 25 (FIG. 3 (A) shown in FIG. ))) And cut with a dicing saw or router machine. By cutting the assembly, the semiconductor element housing package 10 made of individual pieces is produced.

  In order to fabricate the semiconductor element storage packages 10 and 10a, the individual lead wires 20 extending to the plating tie bar wires 24 are used as power sources in the respective conductive wiring patterns 12 of the individual pieces. It is preferable to connect to a power supply conductor wiring pattern. Further, in order to manufacture the semiconductor element housing packages 10 and 10a, it is preferable that the plated wire 18 is extended from the power supply conductor wiring pattern and connected to the individual plated wire assembly pattern 19.

Here, with reference to FIGS. 4A to 4D, the semiconductor element storage package 10, 10a according to the embodiment of the present invention (hereinafter, representatively described in the form of the semiconductor element storage package 10). A method for forming the conductor wiring pattern 12 on the panel-shaped resin base material 22 for producing the above will be described.
As shown in FIG. 4A, the panel-shaped resin base material 22 has, for example, high heat resistance such as BT resin (resin containing bismaleimide triazine as a main component) or epoxy resin, dielectric characteristics, insulating characteristics, and processing. Resin excellent in the property is used, and Cu foil 26 is stuck on both surfaces of the panel-shaped resin base material 22. A through-hole 27 for forming the through-hole conductor 16 (see FIG. 4B) is formed in the panel-shaped resin base material 22 having the Cu foil 26 attached to both surfaces thereof.

  Next, as shown in FIG. 4B, the surface of the Cu foil 26 of the panel-shaped resin base material 22 and the wall surface of the through hole 27 are subjected to electroless Cu plating and electrolytic Cu plating to form the Cu foil 26. A Cu plating film 28 is formed on the surface, and a through-hole conductor 16 made of the Cu plating film 28 is formed on the wall surface of the through hole 27. The method of directly plating the resin surface with electroless Cu plating can be performed chemically in a strong alkali bath using formalin as a reducing agent after applying a catalyst such as palladium to the resin surface. In addition, in the electrolytic Cu plating, for example, the surface of the electroless Cu plating film is energized in a Cu plating bath such as copper sulfate or pyrophosphoric acid to form the electrolytic Cu plating film.

  Next, as shown in FIG. 4C, a photosensitive dry film is spread on both sides of the panel-like resin base material 22 on which the Cu plating film 28 is formed, and exposed by contacting a pattern mask. Then, an etching resist film having an opening opposite to the desired pattern is formed by a photolithography method to be developed. Further, the Cu plating film 28 exposed from the opening of the etching resist film is etched using, for example, an etching solution such as a ferric chloride solution or a cupric chloride solution. The foil 26 is removed. And on the upper surface side of the panel-shaped resin base material 22 which peeled and removed the dry film, for example, the bonding pad 13 (refer FIG.4 (D)) in the conductor wiring pattern 12 and the circuit wiring 15 (FIG.4) are shown. (See (D)). Further, on the lower surface side of the panel-shaped resin base material 22, for example, the circuit wiring 15 in the conductor wiring pattern 12 connected through the through-hole conductor 16 connected to the circuit wiring 15 on the upper surface side (FIG. 4D). And external connection terminal pads 14 (see FIG. 4D) are formed. Furthermore, on the upper surface side of the panel-shaped resin base material 22, a plated wire 18 (not shown) for forming a plating film by electrolytic plating on the conductor wiring pattern 12, a plated wire assembly pattern 19 (not shown), and A plated lead wire 20 (not shown) is provided.

  Next, as shown in FIG. 4D, both sides of the panel-like resin base material 22 are used to expose the necessary portions of the conductor wiring pattern 12 from the opening and simultaneously fill the inside of the through-hole conductor 16. Then, a solder resist film 17 is formed by screen printing or photolithography. Necessary portions of the conductor wiring pattern 12 exposed from the opening of the solder resist film 17 include a bonding pad 13 on the upper surface side of the panel-like resin base material 22 and an external connection terminal pad 14 on the lower surface side. The panel-shaped resin base material 22 is immersed in, for example, a Ni plating bath such as a watt bath or a sulfamic acid bath, and the plated lead wire 20, the plated wire assembly pattern 19, and the plated wire 18 through the plated tie bar wire 24. An Ni plating film (not shown) is applied on the bonding pads 13 exposed from the openings of the solder resist film 17 and the external connection terminal pads 14 by electroplating. Further, the panel-shaped resin base material 22 is immersed in a plating bath such as an Au plating bath or an Au alloy plating bath, and the plated lead wire 24, the plated wire assembly pattern 19 and the plated wire 18 through the plated tie bar wire 24 are used. An Au plating film (not shown) is applied to the surface of the Ni plating film on the bonding pad 13 and the external connection terminal pad 14 exposed from the opening of the solder resist film 17 by electroplating with energization. The Ni plating film may be a Ni alloy plating film containing Co or the like. The plated wire assembly pattern 19 that short-circuits all the conductor wiring patterns 12 is punched and removed using a punching press die, a router processing machine, or the like to form a notch 21. Due to the notches 21, the conductor wiring patterns 12 are electrically disconnected from each other.

  Here, although not shown, an example of a mounting form in the case where a semiconductor element is mounted on a semiconductor element storage package will be described. The semiconductor element storage package has a cut-out portion joined with a heat sink made of a metal plate having high thermal conductivity on either side of the cut-out portion so as to block either side of the cut-out portion. There is a configuration in which the element is mounted on the heat sink so as to be housed in the notch. Further, the semiconductor element is mounted on the cutout portion of the package for housing the semiconductor element in a bridge shape around one of the cutout portions so as to block either one of the cutout portions. There is a form. In any case, the semiconductor element is hermetically sealed with a sealing resin or the like after the bonding pad and the semiconductor element are electrically connected with a bonding wire.

  In the present invention, a semiconductor element storage package on which a signal speed-up semiconductor element is mounted can speed up signal propagation of a signal conductor wiring pattern. It can be applied to mobile phones and personal computers.

(A), (B) is explanatory drawing of the package for semiconductor element accommodation which concerns on one embodiment of this invention, respectively. It is explanatory drawing of the modification of the same semiconductor element storage package. (A), (B) is the partial enlarged plan view of the upper surface side for demonstrating the manufacturing method of the package for the said semiconductor element accommodation, respectively. (A)-(D) are the partial expansion longitudinal cross-sectional views for demonstrating the manufacturing method of the package for the said semiconductor element accommodation, respectively. It is explanatory drawing of the conventional package for semiconductor element accommodation. It is explanatory drawing of the manufacturing method of the same semiconductor element storage package.

Explanation of symbols

  10, 10a: Semiconductor element storage package, 11: Resin base material, 12, 12a: Conductor wiring pattern, 13: Bonding pad, 14: External connection terminal pad, 15, 15a: Circuit wiring, 16: Through-hole conductor, 17 : Solder resist film, 18: Plating wire, 19: Plating wire assembly pattern, 20: Plating lead wire, 21: Notch portion, 22: Panel-shaped resin substrate, 23: Dummy portion, 24: Plating tie bar wire, 25: Cutting line, 26: Cu foil, 27: Through hole, 28: Cu plating film

Claims (4)

In a semiconductor element storage package having a plurality of conductor wiring patterns that are electrically disconnected from each other on a substantially rectangular resin base material, and having a plating film formed by electrolytic plating on the conductor wiring pattern,
A plating wire assembly pattern that is connected to a plating wire extending from each of the conductor wiring patterns for forming the plating film on each of the conductor wiring patterns and that short-circuits each of the conductor wiring patterns is provided in the central portion. And a plating lead wire connected to the plating wire assembly pattern is extended to the outer peripheral side portion, and the plating lead wire, the plating wire assembly pattern, and the plating wire are connected to each of the conductor wiring patterns. A package for housing a semiconductor element, comprising: a notch portion in which the plated wire assembly pattern is formed by being drilled and removed after the plating film is formed.   2. The package for housing a semiconductor element according to claim 1, wherein the plating lead wire is connected to a power supply conductor wiring pattern in the conductor wiring pattern, and the plating wire assembly is connected to the power supply conductor wiring pattern via the plating wire. A package for housing a semiconductor element, wherein the package is connected to a pattern. A plurality of conductor wiring patterns, each of which consists of an assembly in which a plurality of pieces are arranged on a large, substantially rectangular panel-shaped resin substrate via dummy portions, and each of the pieces is electrically disconnected from each other. In the method of manufacturing a package for housing a semiconductor element, in which a plating film is formed by electrolytic plating via a plating tie bar wire provided in the dummy part in each of the conductor wiring patterns,
Provided in the central part of each of the individual pieces is a plating wire assembly pattern for short-circuiting each of the conductor wiring patterns by connecting with a plating wire extending from each of the conductor wiring patterns of the individual pieces, A step of providing a lead-out line connected to the plating wire assembly pattern and extending to the plating tie-bar line through the outer peripheral side of each piece, and
The plating film is applied to the conductor wiring pattern of each piece by the electrolytic plating through the plating tie bar wire, the plating lead line of each piece, the plating line assembly pattern, and the plating line. Forming, and
Drilling and removing each of the plated wire aggregate patterns of the individual pieces to form a notch, electrically disconnecting the conductor wiring patterns of the individual pieces from each other, and from the aggregate A method of manufacturing a package for housing a semiconductor element, comprising a step of cutting along a cutting line for making a single piece.   4. The method of manufacturing a package for housing a semiconductor device according to claim 3, wherein each of the plated lead wires of the individual piece extending to the plated tie bar wire is a power source in each of the conductor wiring patterns of the individual piece. A method of manufacturing a package for housing a semiconductor element, comprising: connecting to a conductor wiring pattern for power supply; and providing the plated wire extending from the power supply conductor wiring pattern and connected to the plated wire assembly pattern of the individual pieces .

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