JP2006261382A - Multilayer wiring board and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board improved in wiring density, and also to provide a method of manufacturing a multilayer wiring board in which a short circuit is removed even if the short circuit is produced between a first inner wiring layer and a second inner wiring layer. <P>SOLUTION: An interposer 3 is equipped with: a multilayer board 31 provided with a hole 31g which penetrates through insulating boards 31a to 31c; an electrode pad 36 on which a plating film 36a is formed; an inner wiring 40a which is arranged between the insulating boards 31a and 31b through which the hole 31g has penetrated, kept in contact with the side of the hole 31g, equipped with an end which is corresponding to the hole 31g in shape, and electrically connected to the electrode pad 36; and an inner wiring 40b that is arranged between the insulating boards 31b and 31c through which the hole 31g has penetrated, kept in contact with the side of the hole 31g, equipped with an end which is corresponding to the hole 31g in shape, electrically separated from the inner wiring layer 40a, and electrically connected to an electrode pad 36 different from the electrode pad 36 to which the inner wiring layer 40a has been connected. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multilayer wiring board and a method for manufacturing the same.

  Conventionally, a semiconductor device in which a semiconductor chip is mounted on an interposer and the semiconductor chip and the interposer are electrically connected by a bonding wire is known.

  The bonding wire is connected to the electrode pad of the interposer, but the surface of the electrode pad may be plated in order to improve the bonding property of the electrode pad to the bonding wire and to prevent oxidation of the electrode pad.

  This plating is performed by connecting a wiring electrically connected to the electrode pad to a wiring for electrolytic plating (hereinafter referred to as “plating wire”) and supplying an electric field to the plating wire. Here, when the electrode pad is plated, it is sufficient that an electric field can be supplied to the electrode pad, so that a plurality of wirings are connected to one plating wire and the wirings are electrically short-circuited. The plating is done. Thereby, the number of plating wires can be reduced, and the formation area of a plating wire can be reduced.

  However, when plating is performed in a state in which the wirings are electrically short-circuited in this way, in order for the wirings to function as signal wirings during the operation of the semiconductor chip, the short-circuited wirings after the plating are used. Must be electrically separated.

Currently, since the wiring is electrically short-circuited on the surface layer of the interposer, the short-circuited portion of the wiring is cut by etching using the opening of the solder resist formed on the surface layer of the interposer. In addition, the wiring is electrically short-circuited by connecting a plurality of wirings to the plated wire on the surface layer of the interposer, and the electrode pads are plated in that state, and then plated using chemical polishing or mechanical polishing. A technique for removing lines and electrically separating wirings is disclosed (see Patent Document 1).
JP 2002-216283 A

  By the way, due to the increase in wiring density, it may not be possible to secure all plating wire formation areas on the surface layer of the interposer, and plating wires are formed on the inner layer of the interposer and a plurality of wirings are formed on the plating wire formed on the inner layer. It is desired that the electrode pads be plated by connecting them and electrically short-circuiting the wires. However, when the wirings are electrically short-circuited in the inner layer of the interposer, it is difficult to cut the short-circuit portion of the wiring existing in the inner layer by the above method.

  The present invention has been made to solve the above problems. That is, even when the multilayer wiring board capable of improving the wiring density and the short-circuit portion between the first inner-layer wiring and the second inner-layer wiring are formed between the insulating substrates, the short-circuit portion is removed. It is an object of the present invention to provide a method for manufacturing a multilayer wiring board capable of satisfying the requirements.

  According to one aspect of the present invention, a plurality of insulating substrates are stacked, a multilayer substrate having at least one or more holes penetrating the insulating substrate, and formed on the multilayer substrate, and at least partially plated A plurality of electrode pads, and disposed between the insulating substrate through which the hole penetrates and the insulating substrate, having an end portion in contact with a side surface of the hole and corresponding to the hole The first inner layer wiring electrically connected to the electrode pad and the insulating substrate through which the hole passes are disposed between the insulating substrate and the side surface of the hole and correspond to the hole And is electrically connected to the electrode pad different from the electrode pad that is electrically isolated from the first inner layer wiring and electrically connected to the first inner layer wiring. And having a second inner layer wiring Multilayer wiring board according to symptoms is provided.

  According to another aspect of the present invention, a multilayer substrate formed by laminating a plurality of insulating substrates, a plurality of electrode pads formed on the multilayer substrate, and disposed between the insulating substrate and the insulating substrate. A first inner layer wiring electrically connected to the electrode pad, and disposed between the insulating substrate and the insulating substrate, and connected to the first inner layer wiring and electrically connected to the first inner layer wiring. A second inner layer wire electrically connected to the electrode pad different from the electrode pad to which the first inner layer wire is electrically connected, and the first and second inner layer wires. An electric field is supplied to the electroplating wiring of a multilayer wiring board that is electrically connected to the electroplating wiring, and the surface of the electrode pad is plated via the first and second inner layer wirings. And applying at least one or more of the insulating substrates Forming a hole, removing a short circuit portion between the first inner layer wiring and the second inner layer wiring, and electrically separating the first inner layer wiring and the second inner layer wiring. A method for manufacturing a multilayer wiring board is provided.

  According to the multilayer wiring board according to one aspect of the present invention, the wiring density can be improved. According to the manufacture of the multilayer wiring board according to another aspect of the present invention, even when the short-circuit portion between the first inner-layer wiring and the second inner-layer wiring is formed between the insulating substrates, the short-circuit portion is removed. Can do.

(First embodiment)
Hereinafter, a first embodiment will be described with reference to the drawings. FIG. 1 is a schematic vertical sectional view of a semiconductor device according to the present embodiment, and FIG. 2 is a schematic plan view of the interposer with the solder resist according to the present embodiment omitted.

  As shown in FIG. 1 and FIG. 2, the semiconductor device 1 has a BGA (Ball Grid Array) structure or an LGA (Land Grid Array) structure. In this embodiment, a semiconductor device having a PFBGA (Plastic Fine Pitch Ball Grid Array) structure is described. The semiconductor device 1 includes a semiconductor chip 2 such as a Si chip. The semiconductor chip 2 is mounted on an interposer 3 (multilayer wiring board) via an adhesive 4, and the semiconductor chip 2 is covered with a mold resin 5.

  The interposer 3 has a multilayer wiring structure. In this embodiment, an interposer having a four-layer wiring structure will be described. The interposer 3 includes a multilayer substrate 31 formed by laminating a plurality of insulating substrates 31a to 31c in the present embodiment. The insulating substrates 31a to 31c are made of, for example, a glass epoxy substrate or a ceramic substrate, and are laminated and adhered to each other.

  The multilayer substrate 31 has holes 31d to 31h penetrating at least one or more insulating substrates 31a to 31c. In the present embodiment, holes 31 d to 31 h penetrating all the insulating substrates 31 a to 31 c are formed in the multilayer substrate 31. The holes 31d to 31h are formed in a columnar shape.

  A plurality of surface layer wirings 32 and 33, a plurality of plating wires 34 and 35, and a plurality of electrode pads 36 and 37 are formed on the front surface of the insulating substrate 31a and the back surface of the insulating substrate 31c. The surface layer wirings 32 are electrically connected to different electrode pads 36, respectively. The electrode pads 36 are electrically connected to the electrode pads 2a of the semiconductor chip 2 via bonding wires 6 made of a metal such as Au, and solder balls 7 are formed on the electrode pads 37, respectively. On the surfaces of the electrode pads 36 and 37, plating films 36a and 37a are formed.

  The surface layer wirings 32 and 33 have one end portions in contact with the holes 31d, 31e, and 31f, respectively, and the end portions are formed in shapes corresponding to the holes 31d, 31e, and 31f, and the surface layer wirings 32a to 32d, 32e to 32h, 33a-33d. In the present embodiment, since the cross-sectional shapes of the holes 31d to 31f are circular, the end portions of the surface wirings 32a to 32d, 32e to 32h, and 33a to 33d are arcuate. The surface layer wires 32a to 32d, the surface layer wires 32e to 32h, and the surface layer wires 33a to 33d, the surface layer wires 32a to 32d, the surface layer wires 32e to 32h, and the surface layer wires 33a to 33d are electrically isolated from each other. Yes.

  The plating wires 34 and 35 are used when the plating films 36 a and 37 a are formed on the surfaces of the electrode pads 36 and 37. One end portions of the plated wires 34 and 35 are in contact with the side surfaces of the holes 31d, 31e, and 31f, respectively, and are formed in shapes corresponding to the holes 31d, 31e, and 31f. That is, the end portions of the plated wires 34 and 35 are arcuate like the end portions of the surface wiring 32a and the like. The other ends of the plated wires 34 and 35 are routed to the outer peripheral edge of the insulating substrates 31a and 31c.

  Solder resists 38 and 39 are formed on the front surface of the insulating substrate 31a and the back surface of the insulating substrate 31c so as to cover the surface layer wirings 32 and 33, respectively. Openings are formed in the solder resists 38 and 39, and the electrode pads 36 and 37 are exposed from these openings.

  Between the insulating substrate 31a and the insulating substrate 31b and between the insulating substrate 31b and the insulating substrate 31c, a plurality of inner layer wirings 40 and 41 and a plurality of plating wires 42 and 43 are formed. The inner layer wirings 40 and 41 are electrically connected to different electrode pads 36 and 37 via the conductive via 44 and the surface layer wirings 32 other than the surface layer wirings 32a to 32d, 32e to 32h, and 33a to 33d.

  The inner layer wirings 40, 41 have a plurality of inner layer wirings 40a to 40d (first inner layer wirings, first inner wirings, one end of which is in contact with the holes 31g, 31h and the end is formed in a shape corresponding to the holes 31g, 31h. 2 inner layer wirings) and a plurality of inner layer wirings 41a to 41d (first inner layer wirings, second inner layer wirings). The end portions of the inner layer wirings 40a to 40d and 41a to 41d are arcuate like the end portions of the surface layer wiring 32a and the like. The inner layer wirings 40a to 40d and the inner layer wirings 41a to 41d, the inner layer wirings 40a to 40d, and the inner layer wirings 41a to 41d are electrically isolated from each other.

  The plating lines 42 and 43 are used when the plating films 36a and 37a are formed on the surfaces of the electrode pads 36 and 37, respectively. One end portions of the plating wires 42 and 43 are in contact with the side surfaces of the holes 31g and 31h, respectively, and are formed in shapes corresponding to the holes 31g and 31h. That is, the end portions of the plated wires 42 and 43 have an arc shape like the end portions of the surface wiring 32a and the like. The other ends of the plated wires 42 and 43 are routed to the outer peripheral edges of the insulating substrates 31b and 31c.

  Such an interposer 3 can be manufactured as follows. FIG. 3 is a diagram schematically showing the manufacturing process of the interposer according to the present embodiment.

  First, an insulating substrate 31a having a surface layer wiring 32, a plating wire 34, and an electrode pad 36 formed on the surface, an insulating substrate 31b having an inner layer wiring 40 and a plating wire 42 formed on the surface, and an inner layer wiring 41 and plating on the surface. An insulating substrate 31c in which the line 43 is formed and the surface layer wiring 33 and the electrode pad 37 are formed on the back surface is laminated in this order.

  Here, as shown in FIG. 3, on the surface of the insulating substrate 31a, the surface layer wirings 32a to 32d are electrically short-circuited by the short-circuit portion 32i, and the plating wire 34 is connected to the short-circuit portion 32i. . The surface layer wirings 32e to 32h are electrically short-circuited by a short-circuit portion 32j, and a plating wire 34 is connected to the short-circuit portion 32j.

  On the surface of the insulating substrate 31b, the inner layer wirings 40a to 40d are electrically short-circuited by the short-circuit portion 40e, and the plating wire 42 is connected to the short-circuit portion 40e. In the present embodiment, the four inner layer wirings 40a to 40d are electrically short-circuited, but it is sufficient that at least two inner layer wirings 40a and 40b are electrically short-circuited.

  On the surface of the insulating substrate 31c, the inner layer wirings 41a to 41d are electrically short-circuited by the short circuit part 41e, and the plating wire 43 is connected to the short circuit part 41e. In the present embodiment, the four inner layer wirings 41a to 41d are electrically short-circuited, but it is sufficient that at least two inner layer wirings 41a and 41b are electrically short-circuited. Further, on the back surface of the insulating substrate 31c, the surface layer wirings 33a to 33d are electrically short-circuited by the short-circuit portion 33e, and the plating wire 43 is connected to the short-circuit portion 33e. The surface layer wirings 32a to 32d, the short circuit portion 32i, the plating wire 34, and the like are integrally formed.

  Next, solder resists 38 and 39 having openings are formed on the front surface of the insulating substrate 31a and the back surface of the insulating substrate 31c so that the electrode pads 36 and 37 are exposed. Thereafter, an electric field is supplied to the plating wire 34 and the like, and the surfaces of the electrode pads 36 and 37 are plated via the surface layer wirings 32 and 33 and the inner layer wirings 40 and 41. Thereby, the plating films 36a and 37a are formed.

  After plating the surfaces of the electrode pads 36 and 37, the insulating substrates 31 a to 31 c are respectively penetrated at positions where the short-circuit portions 32 i and the like exist by a drilling mechanism (not shown) such as a drill or a laser. Holes 31d to 31h are formed from the insulating substrate 31a side. Thereby, the short circuit portion 32i and the like are removed, and the surface layer wirings 32a to 32d and the inner layer wirings 40a to 40d are electrically separated from each other, and the interposer 3 shown in FIG. 2 is completed. In addition, you may remove the plating wires 34 and 35 which exist in the surface layer of the interposer 3 after formation of the holes 31d-31f.

  In the present embodiment, a hole 31g that penetrates the insulating substrates 31a to 31c is formed by a drilling mechanism after plating, the short-circuit portions 40e and 41e are removed, and the inner layer wirings 40a to 40d and the inner layer wirings 41a to 41e are connected. Since they can be electrically separated from each other, even when the short-circuit portions 40e and 41e are formed in the inner layer of the interposer 3, it can be dealt with.

  In the present embodiment, when the surfaces of the electrode pads 36 and 37 are plated, the inner-layer wirings 40a to 40d are electrically short-circuited, so that the number of plating wires 42 and the like can be reduced. Thereby, since the formation area of the plating wire 42 etc. can be reduced, more inner layer wiring 40 grade | etc., Can be formed, and wiring density can be improved.

  Since the plated wire is exposed on the side surface of the semiconductor device 1, it is easily contaminated. Here, if the plated wire or the like is contaminated, the metal constituting the plated wire or the like may move due to electromigration due to the voltage applied during the operation of the semiconductor chip, and the wiring may be short-circuited. On the other hand, in the present embodiment, the number of the plated wires 42 and the like can be reduced by electrically short-circuiting the inner layer wires 40a to 40d or the inner layer wires 41a to 40d. And the like can be widened, and short-circuiting of wiring and the like can be further suppressed.

  In the present embodiment, the short-circuit portions such as the short-circuit portion 32i do not overlap vertically, but once the surface layer wirings 32a to 32d and the like are electrically short-circuited so that the short-circuit portions 32i overlap vertically, once Short-circuit part 32i etc. can be removed by hole formation.

(Second Embodiment)
Hereinafter, a second embodiment will be described with reference to the drawings. In the present embodiment, the first inner layer wiring and the second inner layer wiring arranged between the insulating substrates different from the first inner layer wiring are electrically connected by conductive vias, and the conductive vias are removed after plating. An example in which the first inner layer wiring and the second inner layer wiring are electrically separated will be described. Note that the same contents as those in the first embodiment may be omitted. FIG. 4 is a schematic vertical sectional view of the semiconductor device according to the present embodiment, and FIG. 5 is a schematic plan view of the interposer with the solder resist according to the present embodiment omitted.

  As shown in FIGS. 4 and 5, the side surface of the hole 31g is in contact with the end portions of the inner layer wirings 41a to 41d (second inner layer wiring) in addition to the inner layer wirings 40a to 40d (first inner layer wiring). ing. End portions of the inner layer inner lines 41a to 41d are formed in a shape corresponding to the hole 31g. The inner layer wirings 40a to 40d and the inner layer wirings 41a to 41d are electrically separated from each other.

  Such an interposer 3 can be manufactured as follows. FIG. 6 is a diagram schematically showing the manufacturing process of the interposer according to the present embodiment.

  First, an insulating substrate 31a having a surface layer wiring 32, a plating wire 34, and an electrode pad 36 formed on the surface, an insulating substrate 31b having an inner layer wiring 40 and a plating wire 42 formed on the surface, and an inner layer wiring 41 and plating on the surface. An insulating substrate 31c in which the line 43 is formed and the surface layer wiring 33 and the electrode pad 37 are formed on the back surface is laminated in this order.

  Here, as shown in FIG. 6, the short-circuit portion 40 e of the inner-layer wirings 40 a to 40 d and the short-circuit portion 41 e of the inner-layer wirings 41 a to 41 d overlap each other vertically, and the inner-layer wirings 40 a to 40 d and the inner-layer wirings 41 a to 41 d Are electrically connected through a conductive via 44a. That is, the inner layer wirings 40a to 40d and the inner layer wirings 41a to 41d are electrically short-circuited with each other. In the present embodiment, the four inner layer wirings 40a to 40d and the four inner layer wirings 41a to 41d are electrically short-circuited through the conductive via 44a. However, at least one inner layer wiring 40a and at least one inner layer wiring 40a are electrically short-circuited. It is sufficient that one inner layer wiring 41a is electrically short-circuited.

  Next, solder resists 38 and 39 are formed, and then an electric field is supplied to the plating wires 34 and the like, and the surfaces of the electrode pads 36 and 37 are plated through the surface layer wirings 32 and 33 and the inner layer wirings 40 and 41. .

  After plating the surfaces of the electrode pads 36 and 37, holes are formed from the insulating substrate 31 a side so as to penetrate the insulating substrates 31 a to 31 c at positions where the short-circuit portions 32 c and the like exist by a drilling mechanism (not shown). 31d to 31g are formed. Thereby, the short-circuit portions 40e, 41e and the like and the conductive via 44a are removed, and the inner layer wirings 40a to 40d and the inner layer wirings 41a to 41d, the inner layer wirings 40a to 40d, the inner layer wirings 41a to 41d, and the like are electrically connected to each other. The interposer 3 shown in FIG. 5 is completed.

  In the present embodiment, when the surfaces of the electrode pads 36 and 37 are plated, the inner layer wirings 40a to 40d disposed between the insulating substrates 31a and 31b and the inner layer wiring 41a disposed between the insulating substrates 31b and 31c. Since .about.41d are electrically short-circuited by the conductive via 44a, the number of plated wires 42, 43, etc. can be further reduced.

  In the present embodiment, since the short-circuit portion 40e of the inner-layer wirings 40a to 40d and the short-circuit portion 41e of the inner-layer wirings 41a to 41d overlap vertically, the short-circuit portions 40e and 41e can be removed by forming holes once. In addition, you may form the short circuit part 32i etc. in the position which overlaps with the short circuit part 40e up and down.

  The present invention is not limited to the description of the above embodiment, and the structure, material, arrangement of each member, and the like can be appropriately changed without departing from the gist of the present invention. For example, in the first and second embodiments, the surface wirings 32a to 32d, the surface wirings 32e to 32h, and the surface wirings 33a to 33d are electrically short-circuited. Good. In this case, it is not necessary to form the holes 31d, 31e, 31f.

  In the first and second embodiments, the hole 31g is formed from the insulating substrate 31a side so as to penetrate the insulating substrates 31a to 31c. However, in the first embodiment, the hole 31g is formed on the insulating substrate 31a. In the second embodiment, the hole 31g only needs to penetrate the insulating substrates 31a and 31b. When the hole 31g is formed from the insulating substrate 31c side, the hole 31g only needs to penetrate the insulating substrates 31b and 31c in the first and second embodiments.

  In the first embodiment, the hole 31h is formed from the insulating substrate 31a side so as to penetrate the insulating substrates 31a to 31, but the hole 31h may penetrate the insulating substrates 31a and 31b. In addition, when forming the hole 31h from the insulating substrate 31c side, the hole 31h should just penetrate the insulating substrate 31c.

  In the first and second embodiments, the interposer 3 has been described. However, it can be applied to any multilayer wiring board.

1 is a schematic vertical sectional view of a semiconductor device according to a first embodiment. It is a typical top view of an interposer in the state where a soldering resist concerning a 1st embodiment was omitted. It is the figure which showed typically the manufacturing process of the interposer which concerns on 1st Embodiment. It is a typical vertical sectional view of a semiconductor device concerning a 2nd embodiment. It is a typical top view of an interposer in the state where a solder resist concerning a 2nd embodiment was omitted. It is the figure which showed typically the manufacturing process of the interposer which concerns on 3rd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Semiconductor chip, 3 ... Interposer, 31 ... Multilayer substrate, 31a-31c ... Insulating substrate, 32a-32h, 33a-33d ... Surface layer wiring, 32i, 32j, 33e, 40e, 41e ... Short-circuit part, 34, 35, 42, 43 ... plated wire, 36, 37 ... electrode pad, 40a-40d, 41a-41d ... inner layer wiring.

Claims (5)

A multilayer substrate comprising a plurality of insulating substrates laminated, and having a hole penetrating at least one of the insulating substrates;
A plurality of electrode pads formed on the multilayer substrate and plated at least partially;
The hole is disposed between the insulating substrate and the insulating substrate through which the hole penetrates, has an end portion in a shape corresponding to the hole and in contact with a side surface of the hole, and is electrically connected to the electrode pad. A first inner layer wiring;
The hole is disposed between the insulating substrate and the insulating substrate through which the hole penetrates, has an end portion that contacts the side surface of the hole and has a shape corresponding to the hole, and is electrically connected to the first inner layer wiring. And a second inner layer wiring electrically connected to the electrode pad different from the electrode pad to which the first inner layer wiring is electrically connected. .   2. The multilayer wiring board according to claim 1, wherein the first inner layer wiring is disposed between the insulating substrates that is the same as the insulating substrate in which the second inner layer wiring is disposed.   2. The multilayer wiring board according to claim 1, wherein the first inner layer wiring is arranged between the insulating substrates different from the insulating substrate on which the second inner layer wiring is arranged.   The multilayer wiring board according to claim 1, wherein the hole penetrates the multilayer substrate. A multilayer substrate formed by laminating a plurality of insulating substrates, a plurality of electrode pads formed on the multilayer substrate, and disposed between the insulating substrate and the insulating substrate and electrically connected to the electrode pads. The first inner layer wiring is disposed between the insulating substrate and the insulating substrate, connected to the first inner layer wiring and electrically short-circuited with the first inner layer wiring, and the first inner layer wiring. A second inner layer wiring electrically connected to the electrode pad different from the electrode pad to which the wiring is electrically connected; and an electrolytic plating electrically connected to the first and second inner layer wirings. Supplying an electric field to the electrolytic plating wiring of the multilayer wiring board including the wiring, and plating the surface of the electrode pad via the first and second inner layer wirings;
Forming at least one or more holes penetrating the insulating substrate, removing a short-circuit portion between the first inner layer wiring and the second inner layer wiring, and forming the first inner layer wiring and the second inner layer wiring; And a step of electrically separating the wiring board.

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