JP5493660B2 - Functional element built-in substrate, manufacturing method thereof, and electronic device - Google Patents

Functional element built-in substrate, manufacturing method thereof, and electronic device Download PDF

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JP5493660B2
JP5493660B2 JP2009227371A JP2009227371A JP5493660B2 JP 5493660 B2 JP5493660 B2 JP 5493660B2 JP 2009227371 A JP2009227371 A JP 2009227371A JP 2009227371 A JP2009227371 A JP 2009227371A JP 5493660 B2 JP5493660 B2 JP 5493660B2
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functional element
substrate
heat dissipation
heat
wiring layer
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JP2011077305A (en
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嘉樹 中島
新太郎 山道
克 菊池
健太郎 森
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NEC Corp
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NEC Corp
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Description

本発明は、機能素子内蔵基板及びその製造方法、並びに電子機器に関し、更に詳しくは一個以上の機能素子を内蔵する機能素子内蔵基板及びその製造方法、並びに機能素子内蔵基板を有する電子機器に関する。   The present invention relates to a functional element-embedded substrate, a manufacturing method thereof, and an electronic device, and more particularly to a functional element-embedded substrate that includes one or more functional elements, a manufacturing method thereof, and an electronic device having the functional element-embedded substrate.

機能素子内蔵基板は、電子機器の小型化・薄型化にとって重要な技術になっているが、機能素子より発生する熱が大きな問題となっている。そのため、以下のような技術が開示されている。   The functional element-embedded substrate is an important technology for downsizing and thinning electronic devices, but heat generated from the functional element is a big problem. Therefore, the following techniques are disclosed.

特許文献１に記載の機能素子内蔵基板では、機能素子裏面直下に放熱用の配線パターンを形成することで放熱性を高める構造が開示されている。特許文献２および３に記載の機能素子内蔵基板では、機能素子の下部に放熱材となる金属板が設ける技術が開示されている。特許文献４では、機能素子の側面の金属補強材を放熱材とし、放熱効果を一定以上維持するとともに設計自由度を確保している。特許文献５では、外部に露出する放熱面を増加させるため、放熱材を外部に突出させる構造を開示している。特許文献６では、放熱効果を高めるため、機能素子回路面に直接接続する放熱ビアを設ける構造としている。特許文献７では、放熱効果を高めるため、機能素子回路面の反対側に放熱ビアを設ける構造としている。特許文献８では、機能素子を実装した基板の機能素子とは別の部分に放熱配線と放熱ビアを通じてヒートシンクを設け、基板の配線及び設計自由度を確保する構造を開示している。   In the functional element built-in substrate described in Patent Document 1, a structure is disclosed in which heat dissipation is improved by forming a heat dissipation wiring pattern immediately below the back surface of the functional element. In the functional element built-in substrates described in Patent Documents 2 and 3, a technique is disclosed in which a metal plate serving as a heat dissipation material is provided below the functional element. In Patent Document 4, the metal reinforcing material on the side surface of the functional element is used as a heat dissipating material, and the heat dissipating effect is maintained at a certain level and design freedom is ensured. In patent document 5, in order to increase the heat radiation surface exposed outside, the structure which makes a heat radiating material protrude outside is disclosed. In Patent Document 6, in order to enhance the heat dissipation effect, a heat dissipation via directly connected to the functional element circuit surface is provided. In Patent Document 7, in order to enhance the heat dissipation effect, a heat dissipation via is provided on the side opposite to the functional element circuit surface. Patent Document 8 discloses a structure in which a heat sink is provided through a heat radiating wiring and a heat radiating via in a portion different from the functional element of the substrate on which the functional element is mounted, thereby ensuring the wiring of the substrate and the degree of design freedom.

特開２００４−３３５６４１号公報Japanese Patent Laid-Open No. 2004-335641 特開２００４−２８８７１１号公報JP 2004-288711 A 特開２００２−１８５１４５号公報JP 2002-185145 A 特開２００８−２６３２２０号公報JP 2008-263220 A 特開２００７−１１５８３７号公報JP 2007-115837 A 特開２００６−３３９４２１号公報JP 2006-339421 A ＷＯ２００６／０４３３８８号公報WO2006 / 043388 特開平１１−３３０７０８号公報Japanese Patent Laid-Open No. 11-330708

特許文献１に開示の技術は、配線設計自由度が減少すると同時に、配線のみで放熱を行うので放熱量が制限される。特許文献２、３に開示の技術は、機能素子の上側または下側に厚みのある金属板が存在するため、その部分に配線が設けられず、またその分厚みが増す。特許文献４に開示の技術は、機能素子が薄化した場合に外部に露出する放熱面積が減少する。特許文献５に開示の技術は、放熱材を放熱の目的のみで用い、たとえば補強材等を兼ねる構造としていない。特許文献６に開示の技術は、機能素子回路面側の配線が制限される。また、放熱ビアは回路面側最外層の金属層に接続されているが、該金属層を形成するプロセスにはコストがかかる。また該機能素子内蔵基板の上段に基板または機能素子等を実装する場合、放熱効果が低下する。特許文献７に開示の技術は、機能素子回路面の反対側の配線が制限される。特許文献８では、ヒートシンクを設けなければならないため、コストが増加すると共に、基板表面の実装面積が減少する。   In the technique disclosed in Patent Document 1, the degree of freedom in wiring design is reduced, and at the same time, heat is radiated only by wiring, so the amount of heat radiated is limited. In the techniques disclosed in Patent Documents 2 and 3, since a thick metal plate exists on the upper side or the lower side of the functional element, no wiring is provided in that portion, and the thickness increases accordingly. The technique disclosed in Patent Document 4 reduces the heat radiation area exposed to the outside when the functional element is thinned. The technique disclosed in Patent Document 5 uses a heat dissipation material only for the purpose of heat dissipation, and does not have a structure that also serves as a reinforcing material, for example. In the technique disclosed in Patent Document 6, wiring on the functional element circuit surface side is limited. Moreover, although the thermal radiation via is connected to the outermost metal layer on the circuit surface side, the process for forming the metal layer is expensive. Moreover, when a board | substrate or a functional element etc. are mounted in the upper stage of this functional element built-in board | substrate, the heat dissipation effect falls. In the technique disclosed in Patent Document 7, wiring on the opposite side of the functional element circuit surface is limited. In Patent Document 8, since a heat sink must be provided, the cost increases and the mounting area of the substrate surface decreases.

上記従来技術の機能素子内蔵基板の問題点は以下のように整理される。即ち、第１の問題点は、機能素子内蔵基板の放熱を配線によって行う場合、設計自由度が減少することと放熱効果が十分に確保できない点である。また、第２の問題点は、機能素子の放熱を機能素子の上側または下側の金属板によって行う場合、設計自由度が減少することと基板の薄化ができない点である。第３の問題点は、機能素子の側面に金属補強材を設け、該金属補強材を放熱材として用いる場合、機能素子の薄化に伴って外部に露出する放熱材面積が減少し、放熱効果が減少する点である。また第４の問題点は、外部に露出する放熱面を増加させるため、放熱材を外部に突出させる構造とした場合、放熱材を放熱の目的のみで用い、たとえば補強材等を兼ねる構造としていないため、プロセスおよびコストが増加する点である。また第５の問題点は、放熱のためにヒートシンクを別に取り付ける場合、ヒートシンクの部品調達コスト及び実装コストがかかる点である。   The problems of the above-described substrate with a built-in functional element can be summarized as follows. That is, the first problem is that when the heat radiation of the functional element built-in substrate is performed by wiring, the degree of freedom in design is reduced and the heat radiation effect cannot be sufficiently ensured. The second problem is that when the heat radiation of the functional element is performed by the upper or lower metal plate of the functional element, the degree of design freedom is reduced and the substrate cannot be thinned. The third problem is that when a metal reinforcing material is provided on the side surface of the functional element and the metal reinforcing material is used as a heat radiating material, the area of the heat radiating material exposed to the outside decreases with the thinning of the functional element. This is the point that decreases. The fourth problem is that, in order to increase the heat-dissipating surface exposed to the outside, when the heat-dissipating material protrudes to the outside, the heat-dissipating material is used only for the purpose of heat-dissipation and does not have a structure that also serves as a reinforcing material, for example Therefore, the process and cost increase. The fifth problem is that, when a heat sink is separately attached for heat dissipation, the parts procurement cost and mounting cost of the heat sink are required.

本発明は、以上のような問題点を鑑みてなされたものであり、その目的は、機能素子内蔵基板において、薄化と設計自由度を維持しつつ、放熱効果を十分に確保できる構造およびその製造方法を提供することである。   The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a structure capable of sufficiently ensuring a heat dissipation effect while maintaining thinness and design freedom in a functional element built-in substrate, and its It is to provide a manufacturing method.

本発明の第１の視点に係る機能素子内蔵基板は、絶縁層と、該絶縁層に埋設される１以上の機能素子と、該絶縁層内部の該機能素子の横方向周囲に配された放熱材と、機能素子の回路面側に配設され、機能素子の回路面に設けられた電極端子を通じて該機能素子と接続されている第１配線層と、機能素子内蔵基板の機能素子回路面側の反対側に配設されている第２配線層と、放熱材及び絶縁層を貫通し、第１配線層と第２配線層とを接続する層間ビアと、放熱材と第１配線層とを接続する放熱ビアと、を含む機能素子内蔵基板が提供される。放熱材が該機能素子内蔵基板の側面部に露出するとともに、少なくとも一部がさらに基板面に直交する方向、つまり側面部の高さ方向（上下方向）に亘って延在して形成されている（以下、このように形成された部分を延在部という）。延在部の側面に、凹凸構造が含まれている。 A functional element-embedded substrate according to a first aspect of the present invention includes an insulating layer, one or more functional elements embedded in the insulating layer, and heat dissipation disposed around the functional element in the lateral direction inside the insulating layer. Material, a first wiring layer disposed on the circuit surface side of the functional element and connected to the functional element through an electrode terminal provided on the circuit surface of the functional element, and the functional element circuit surface side of the functional element built-in substrate A second wiring layer disposed on the opposite side, an interlayer via that penetrates the heat dissipation material and the insulating layer and connects the first wiring layer and the second wiring layer, and a heat dissipation material and the first wiring layer. A functional element-embedded substrate including a heat dissipation via to be connected is provided. The thermal material discharge is exposed on the side surface of the functional element embedded board, are formed to extend over the direction at least partially further perpendicular to the substrate surface, i.e. the side portion height direction (vertical direction) ( Hereinafter, the portion formed in this way is referred to as an extending portion). An uneven structure is included on the side surface of the extending portion .

本発明の第２の視点に係る半導体装置は、上記機能素子内蔵基板の前記放熱材の前記側面延在部に接続端子が設置され、かつ信号端子同士も接続された、機能素子内蔵基板を複数含むことを特徴とする。   A semiconductor device according to a second aspect of the present invention includes a plurality of functional element-embedded substrates in which connection terminals are installed in the side surface extending portion of the heat dissipation material of the functional element-embedded substrate and signal terminals are also connected to each other. It is characterized by including.

本発明の第３の視点に係る電子機器は、上記機能素子内蔵基板又は半導体装置を含むことを特徴とする。   An electronic apparatus according to a third aspect of the present invention includes the functional element-embedded substrate or the semiconductor device.

本発明の第４の視点に係る機能素子内蔵基板の製造方法は、開口部に機能素子を配した放熱材の両面側に絶縁層を配する工程と、該絶縁層の周辺部の少なくとも一部を除去して放熱材用ビアホールを形成する工程と、
機能素子の回路面に設けられた電極端子を通じて該機能素子と接続される第１配線層と、機能素子内蔵基板の機能素子回路面側の反対側に配設される第２配線層とを接続するための、放熱材及び絶縁層を貫通する層間ビア用ビアホールを形成する工程と、第１配線層と放熱材とを接続するための放熱ビア用ビアホールを形成する工程と、放熱材用ビアホールに、さらに放熱部を形成することにより、機能素子内蔵基板外周部の放熱材延在部を形成する工程と、層間ビア用ビアホールに層間ビアを形成する工程と、放熱ビア用ビアホールに放熱ビアを形成する工程と、第１配線層及び第２配線層を形成する工程と、放熱材延在部に凹凸構造が含まれるようにダイシングを行う工程と、を含む。 According to a fourth aspect of the present invention, there is provided a method of manufacturing a functional element-embedded substrate, the step of disposing an insulating layer on both sides of a heat dissipating material in which a functional element is disposed in an opening, and at least a part of a peripheral portion of the insulating layer Removing the heat dissipation material via hole and
Connects the first wiring layer connected to the functional element through the electrode terminal provided on the circuit surface of the functional element and the second wiring layer disposed on the opposite side of the functional element circuit surface side of the functional element built-in substrate. A step of forming a via hole for an interlayer via penetrating the heat dissipation material and the insulating layer, a step of forming a via hole for a heat dissipation via for connecting the first wiring layer and the heat dissipation material, and a via hole for the heat dissipation material by further forming the heat radiating portion, and forming a heat dissipating material extending portion of the functional element embedded board peripheral portion, and forming an interlayer vias in the via hole for interlayer via, the thermal vias in the via hole for heat radiation vias formed step and step and a step of performing dicing to include uneven structure on the heat radiating member extending portion, the including of forming the first wiring layer and the second wiring layer.

本発明の機能素子内蔵基板によって、側面の広い範囲に亘って放熱材が設置される為、機能素子内蔵層の薄化を含む機能素子内蔵基板の薄化を実現しつつ、機能素子内蔵基板の放熱効果を十分に維持することができる。また、放熱材を機能素子の側面に配設することで、機能素子の設計自由度を維持することができる。   With the functional element built-in substrate of the present invention, the heat dissipating material is installed over a wide range of side surfaces, so that the functional element built-in substrate including the thinning of the functional element built-in layer can be thinned, The heat dissipation effect can be sufficiently maintained. Moreover, the design freedom of the functional element can be maintained by disposing the heat radiating material on the side surface of the functional element.

また、放熱材を補強材と兼ねる構造とした場合は、プロセスのコストの低減も実現することができると共に、反りの低減、基板の剛性の向上、基板の平坦性の向上等の効果が期待できる。また、ヒートシンクを別に設ける際に必要な部品調達コストや実装するコストを省くことができる。   In addition, when the heat dissipation material is also used as a reinforcing material, the cost of the process can be reduced, and effects such as reduction of warpage, improvement of the rigidity of the board, and improvement of the flatness of the board can be expected. . In addition, it is possible to save parts procurement cost and mounting cost required when a heat sink is separately provided.

本発明の第１の実施例に係る機能素子内蔵基板の断面図である。It is sectional drawing of the functional element built-in board | substrate which concerns on 1st Example of this invention. 本発明の第１の実施例に係る機能素子内蔵基板の機能素子内蔵層の平面図である。It is a top view of the functional element incorporation layer of the functional element incorporation substrate concerning the 1st example of the present invention. 本発明の第１の実施例に係る機能素子内蔵基板の機能素子回路面側配線層の平面図である。It is a top view of the functional element circuit surface side wiring layer of the functional element built-in substrate according to the first embodiment of the present invention. 本発明の第２の実施例に係る機能素子内蔵基板の断面図である。It is sectional drawing of the functional element built-in board | substrate which concerns on the 2nd Example of this invention. 本発明の第２の実施例に係る機能素子内蔵基板の機能素子内蔵層の平面図である。It is a top view of the functional element incorporation layer of the functional element incorporation substrate concerning the 2nd example of the present invention. 本発明の第２の実施例に係る機能素子内蔵基板の機能素子回路面側配線層の平面図である。It is a top view of the functional element circuit side wiring layer of the functional element built-in substrate according to the second embodiment of the present invention. 本発明の第３の実施例に係る機能素子内蔵基板の断面図である。It is sectional drawing of the functional element built-in board | substrate which concerns on the 3rd Example of this invention. 本発明の第３の実施例に係る機能素子内蔵基板の機能素子内蔵層の平面図である。It is a top view of the functional element incorporation layer of the functional element incorporation substrate concerning the 3rd example of the present invention. 本発明の第３の実施例に係る機能素子内蔵基板の機能素子回路面側配線層の平面図である。It is a top view of the functional element circuit surface side wiring layer of the functional element built-in substrate based on 3rd Example of this invention. 本発明の第４の実施例に係る機能素子内蔵基板の断面図である。It is sectional drawing of the functional element built-in board | substrate which concerns on the 4th Example of this invention. 本発明の第４の実施例に係る機能素子内蔵基板の機能素子内蔵層の平面図である。It is a top view of the functional element incorporation layer of the functional element incorporation substrate concerning the 4th example of the present invention. 本発明の第４の実施例に係る機能素子内蔵基板の機能素子回路面側配線層の平面図である。It is a top view of the functional element circuit surface side wiring layer of the functional element built-in substrate according to the fourth embodiment of the present invention. 本発明の第５の実施例に係る機能素子内蔵基板の断面図である。It is sectional drawing of the functional element built-in board | substrate which concerns on the 5th Example of this invention. 本発明の第５の実施例に係る機能素子内蔵基板の機能素子内蔵層の平面図である。It is a top view of the functional element incorporation layer of the functional element incorporation substrate concerning the 5th example of the present invention. 本発明の第５の実施例に係る機能素子内蔵基板の機能素子回路面側配線層の平面図である。It is a top view of the functional element circuit surface side wiring layer of the functional element built-in substrate based on 5th Example of this invention. 本発明の第６の実施例に係る機能素子内蔵基板の断面図である。It is sectional drawing of the functional element built-in board | substrate which concerns on the 6th Example of this invention. 本発明の第７の実施例に係る機能素子内蔵基板の断面図である。It is sectional drawing of the functional element built-in board | substrate which concerns on the 7th Example of this invention. 本発明の第６の実施例に係る機能素子内蔵基板の実装例の断面図である。It is sectional drawing of the example of mounting of the functional element built-in board | substrate based on the 6th Example of this invention. 本発明の第７の実施例に係る機能素子内蔵基板の実装例の断面図である。It is sectional drawing of the example of mounting of the functional element built-in board | substrate concerning the 7th Example of this invention. 本発明の第５の実施例に係る機能素子内蔵基板５００の第１の製造方法の製造段階を示す断面図である。It is sectional drawing which shows the manufacture stage of the 1st manufacturing method of the functional element built-in board | substrate 500 which concerns on the 5th Example of this invention. 図２０に示す製造段階（ａ）の平面図である。It is a top view of the manufacturing stage (a) shown in FIG. 図２０から続く製造段階を示す断面図である。FIG. 21 is a cross-sectional view showing a manufacturing step continued from FIG. 20. 図２２（ｇ）に示す製造段階の平面図である。FIG. 23 is a plan view of the manufacturing stage shown in FIG. 図２２（ｇ）に示す製造段階の変形例の平面図である。It is a top view of the modification of the manufacturing stage shown in FIG.22 (g). 図２２（ｇ）に示す製造段階の他の変形例の平面図である。FIG. 23 is a plan view of another modification of the manufacturing stage shown in FIG. 図２２から続く製造段階を示す断面図である。FIG. 23 is a cross-sectional view showing a manufacturing step continued from FIG. 22. 図２６から続く製造段階を示す断面図である。FIG. 27 is a cross-sectional view showing a manufacturing step continued from FIG. 26. 図２７（ｎ）に示す製造段階の平面図である。FIG. 28 is a plan view of the manufacturing stage shown in FIG. 図２４に示す変形例の場合の製造段階（ｎ）の平面図である。FIG. 25 is a plan view of a manufacturing stage (n) in the case of the modification shown in FIG. 24. 図２５に示す他の変形例の場合の製造段階（ｎ）の平面図である。FIG. 26 is a plan view of a manufacturing stage (n) in the case of another modification shown in FIG. 25. 図２７（ｎ）から続くダイシング工程後の断面図である。FIG. 28 is a cross-sectional view after a dicing process continued from FIG. 図２８のようにダイシングした場合の平面図である。It is a top view at the time of dicing like FIG. 図３０のようにダイシングした場合の平面図である。It is a top view at the time of dicing like FIG. 本発明の第５の実施例に係る機能素子内蔵基板５００を第１の製造例によって製造した場合の、より詳細な断面図である。FIG. 10 is a more detailed cross-sectional view when a functional element-embedded substrate 500 according to a fifth embodiment of the present invention is manufactured according to the first manufacturing example.

本発明に係る機能素子内蔵基板において、放熱材は、絶縁層内部での厚さが機能素子の厚さと同じであることが好ましい。   In the functional element-embedded substrate according to the present invention, it is preferable that the heat dissipation material has the same thickness inside the insulating layer as the functional element.

前記放熱材は、前記基板面に直交する方向の延在部の少なくとも一部の長さが、該基板の配線層を含む厚さと同じであることが好ましい。   In the heat dissipation material, it is preferable that the length of at least a part of the extending portion in the direction orthogonal to the substrate surface is the same as the thickness including the wiring layer of the substrate.

前記放熱材が、金属、樹脂材料、セラミック材料及びカーボンナノチューブ材料のうちの少なくとも１つかならなることが好ましい。   It is preferable that the heat dissipation material is at least one of a metal, a resin material, a ceramic material, and a carbon nanotube material.

前記放熱材と前記機能素子が、配線及び放熱ビアのうちの少なくとも１つによって接続されていることが好ましい。   It is preferable that the heat dissipation material and the functional element are connected by at least one of a wiring and a heat dissipation via.

前記配線及び放熱ビアのうちの少なくとも１つが、前記機能素子のグランドを兼ねることが好ましい。   It is preferable that at least one of the wiring and the heat dissipation via also serves as a ground for the functional element.

前記第１及び第２配線層に加え、さらに一層以上の配線層が配設されていることが好ましい。
In addition to the first and second wiring layers, one or more wiring layers are preferably provided.

前記放熱材が前記機能素子内蔵基板の側面部に延在している部分と、前記側面部に露出しているのみである部分の比率が、１対１〜１対２の割合になっていることが好ましい。   The ratio of the portion where the heat dissipation material extends to the side surface portion of the functional element built-in substrate and the portion exposed only to the side surface portion is a ratio of 1: 1 to 1: 2. It is preferable.

本発明に係る機能素子内蔵基板の製造方法において、前記放熱材延在部の形成にビアホール形成プロセス及びめっきプロセスを用いることが好ましい。   In the method for manufacturing a functional element-embedded substrate according to the present invention, it is preferable to use a via hole forming process and a plating process for forming the heat radiating material extending portion.

また、前記機能素子内蔵基板が２つ以上面取りされているワークサイズによって製造されることが好ましい。   Moreover, it is preferable that the functional element-embedded substrate is manufactured with a work size in which two or more chamfers are chamfered.

以下に、添付図面を参照し、本発明の実施例を更に詳しく説明する。   Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

（実施例１）
図１乃至図３は、それぞれ本発明の第１の実施例に係る機能素子内蔵基板１００の縦断面図、機能素子内蔵層の水平断面図（図１のＡ−Ａ断面）、上面配線層の平面図である。機能素子内蔵基板１００は、回路面２側に電極端子４を有する機能素子１が絶縁層３に埋設されている。絶縁層３の回路面側と回路面の反対側には、それぞれ配線層６と配線層７が形成されており、配線層６は電極端子４と接続されている。また絶縁層３の機能素子１の側方には機能素子内蔵基板全体に亘って放熱材５が配設され、かつ放熱材５は機能素子内蔵基板１００の側面でさらに基板面に直行する方向（側面部の上下方向）全体に亘って延在部４０として広がっている。 Example 1
1 to 3 are respectively a longitudinal sectional view of a functional element built-in substrate 100 according to a first embodiment of the present invention, a horizontal sectional view of a functional element built-in layer (cross section AA in FIG. 1), and an upper wiring layer. It is a top view. In the functional element built-in substrate 100, the functional element 1 having the electrode terminal 4 on the circuit surface 2 side is embedded in the insulating layer 3. A wiring layer 6 and a wiring layer 7 are formed on the circuit surface side and the opposite side of the circuit surface of the insulating layer 3, respectively, and the wiring layer 6 is connected to the electrode terminal 4. Further, a heat radiating material 5 is disposed on the side of the functional element 1 in the insulating layer 3 over the entire functional element built-in substrate, and the heat radiating material 5 is further in a direction perpendicular to the substrate surface on the side surface of the functional element built-in substrate 100 ( It extends as an extended portion 40 over the entire side portion in the vertical direction).

絶縁層３には、エポキシ、ポリイミド、液晶ポリマーなどをベースとしたものが好適であるが、それらに限定されない。電極端子４は、金属または導電性ペースト等が好適であるが、それらに限定されない。放熱材５は、銅、ＳＵＳ、コバール合金等の金属材料、或いはセラミック材料、または高熱伝導性樹脂等が好適であるが、これらに限定されない。配線層６及び７には、めっき法、印刷法による銅、ニッケル、金、銀、無鉛はんだなどの一種類以上の金属が好適であるが、それらに限定されない。   The insulating layer 3 is preferably based on epoxy, polyimide, liquid crystal polymer, or the like, but is not limited thereto. The electrode terminal 4 is preferably a metal or a conductive paste, but is not limited thereto. The heat dissipating material 5 is preferably a metal material such as copper, SUS, or Kovar alloy, or a ceramic material, or a high thermal conductive resin, but is not limited thereto. The wiring layers 6 and 7 are preferably made of one or more kinds of metals such as copper, nickel, gold, silver, lead-free solder by plating or printing, but are not limited thereto.

また、図１、図３に示されている配線層６乃至７の配線パターンは、あくまで模式的な一例であり、本発明の趣旨に沿う形で別のパターンを任意に形成することが可能である。   Further, the wiring patterns of the wiring layers 6 to 7 shown in FIGS. 1 and 3 are merely schematic examples, and other patterns can be arbitrarily formed in accordance with the spirit of the present invention. is there.

また、放熱材５は、機能素子内蔵基板１００の側面の必ずしも全周にわたって延在部４０を有する必要はなく、その一部に延在部４０を有しない部分があってもよい。例えば、基板１００と同じ高さの延在部４０を有する部分と、延在部４０を有さずに基板１００の側面部に放熱材５が露出しているのみである部分の比率が１対１から１対２の範囲であれば、十分な放熱効果を奏する。またその延在部４０の高さ方向の長さも、図１では基板１００の高さと同じとしており、またそれが放熱効果の点で好ましいが、必ずしも同じである必要はない。   Further, the heat dissipation material 5 does not necessarily have the extending portion 40 over the entire circumference of the side surface of the functional element-embedded substrate 100, and there may be a portion that does not have the extending portion 40. For example, the ratio of the portion having the extended portion 40 having the same height as the substrate 100 and the portion in which the heat radiating material 5 is not exposed on the side surface portion of the substrate 100 without the extended portion 40 is one pair. If it is the range of 1 to 1: 2, sufficient heat dissipation effect is produced. Further, the length of the extending portion 40 in the height direction is the same as the height of the substrate 100 in FIG. 1, and this is preferable in terms of the heat dissipation effect, but is not necessarily the same.

さらに、放熱材５の絶縁層３内部での厚さは、図１では機能素子１と同じとしており、またそれが好ましいが、必ずしも同じである必要はない。これらは適宜設計条件に応じて設定できるものであり、以下の実施例においても同様である。   Further, the thickness of the heat dissipating material 5 inside the insulating layer 3 is the same as that of the functional element 1 in FIG. 1 and is preferable, but it is not necessarily the same. These can be appropriately set according to design conditions, and the same applies to the following embodiments.

（実施例２）
図４乃至図６は、本発明の第２の実施例に係る機能素子内蔵基板２００の、縦断面図、機能素子内蔵層の水平断面図（図４（ａ）のＣ−Ｃ断面）、上部配線層６の平面図である。機能素子内蔵基板２００は、機能素子内蔵基板１００の放熱材５において更に露出面積を増加させるよう、上部から見て端部が凹凸の構造となっていることを特徴とする。その他の構造は機能素子内蔵基板１００と同じである。実施例２は、放熱材５の露出面積を増加させることで、より高い放熱効果を狙ったものである。尚、図４の（ａ）は、放熱材５が凸である部分の断面図（図５におけるＡ−Ａ断面図）、図４（ｂ）は、放熱材５が凹である部分の断面図（図５におけるＢ−Ｂ断面図）である。 (Example 2)
4 to 6 are a vertical sectional view, a horizontal sectional view of a functional element built-in layer (CC cross section in FIG. 4A), an upper part of the functional element built-in substrate 200 according to the second embodiment of the present invention. 3 is a plan view of a wiring layer 6. FIG. The functional element-embedded substrate 200 is characterized in that the end portion has an uneven structure when viewed from above so as to further increase the exposed area of the heat dissipation material 5 of the functional element-embedded substrate 100. Other structures are the same as those of the functional element built-in substrate 100. Example 2 aims at a higher heat dissipation effect by increasing the exposed area of the heat dissipation material 5. 4A is a cross-sectional view of a portion where the heat dissipating material 5 is convex (AA cross-sectional view in FIG. 5), and FIG. 4B is a cross-sectional view of a portion where the heat dissipating material 5 is concave. It is BB sectional drawing in FIG.

また図５に示されている放熱材５の端部の凹凸パターン、図４または図６に示されている配線層６乃至７の配線パターンは、あくまで模式的な一例であり、本発明の趣旨に沿う形で別のパターンを自由に形成することが可能である。   Further, the uneven pattern at the end of the heat dissipation material 5 shown in FIG. 5 and the wiring patterns of the wiring layers 6 to 7 shown in FIG. 4 or FIG. 6 are merely schematic examples, and are the gist of the present invention. It is possible to freely form another pattern along the line.

（実施例３）
図７乃至図９は、それぞれ本発明の第３の実施例に係る機能素子内蔵基板３００の、縦断面図、機能素子内蔵層の水平断面図（図７のＡ−Ａ断面）、上面配線層の平面図である。機能素子内蔵基板３００は、機能素子内蔵基板１００の構造に加え、絶縁層３及び放熱材５を貫通し、配線層６と配線層７を接続する層間ビア８が設けられていることを特徴とする。配線層６と配線層７が互いに接続されていることで、設計自由度が向上している。 (Example 3)
7 to 9 are a longitudinal sectional view, a horizontal sectional view of a functional element built-in layer (cross section AA in FIG. 7), and a top wiring layer, respectively, of the functional element built-in substrate 300 according to the third embodiment of the present invention. FIG. In addition to the structure of the functional element-embedded substrate 100, the functional element-embedded substrate 300 includes an interlayer via 8 that penetrates the insulating layer 3 and the heat dissipation material 5 and connects the wiring layer 6 and the wiring layer 7. To do. Since the wiring layer 6 and the wiring layer 7 are connected to each other, the degree of freedom in design is improved.

層間ビア８は、レーザー、ドリル等によってビアホールを設け、めっき法、印刷法による銅、ニッケル、金、銀、無鉛はんだなどの一種類以上の金属をフィルドまたはコンフォーマルビアの形状に形成することにより作製する方法が好適に用いられるが、これに限定されない。   The interlayer via 8 is formed by providing a via hole with a laser, a drill, or the like, and forming one or more kinds of metals such as copper, nickel, gold, silver, lead-free solder by a plating method or a printing method into a filled or conformal via shape. A manufacturing method is preferably used, but is not limited thereto.

また図７乃至８に示されている層間ビア８の数及び位置、図７または図９に示されている配線層６乃至７の配線パターンは、あくまで模式的な一例であり、電極端子４と層間ビア８を接続する配線が存在することを除いては、本発明の趣旨に沿う形で別のパターンを任意に形成することが可能である。   Further, the number and positions of the interlayer vias 8 shown in FIGS. 7 to 8 and the wiring patterns of the wiring layers 6 to 7 shown in FIG. 7 or FIG. 9 are merely schematic examples, and the electrode terminals 4 and Except for the presence of wiring connecting the interlayer vias 8, it is possible to arbitrarily form another pattern in accordance with the spirit of the present invention.

（実施例４）
図１０乃至図１２は、それぞれ本発明の第４の実施例に係る機能素子内蔵基板４００の、縦断面図、機能素子内蔵層の水平断面図（図１０のＡ−Ａ断面）、上面配線層の平面図である。機能素子内蔵基板４００は、機能素子内蔵基板１００の構造に加え、回路面２側の配線層６と放熱材５を接続させる放熱ビア９を設けていることを特徴とする。配線層６と放熱材５が接続されていることで、放熱効果がより高くなっている。 (Example 4)
10 to 12 are a longitudinal sectional view, a horizontal sectional view of a functional element built-in layer (cross section AA in FIG. 10), and a top wiring layer, respectively, of the functional element built-in substrate 400 according to the fourth embodiment of the present invention. FIG. The functional element built-in substrate 400 is characterized in that, in addition to the structure of the functional element built-in substrate 100, a heat radiation via 9 for connecting the wiring layer 6 on the circuit surface 2 side and the heat radiation material 5 is provided. Since the wiring layer 6 and the heat dissipation material 5 are connected, the heat dissipation effect is higher.

また図１０乃至１１に示されている放熱ビア９の位置及び数、図１０または図１２に示されている配線層６乃至７の配線パターンは、あくまで模式的な一例であり、電極端子４と放熱ビア９を接続する配線が存在することを除いては、本発明の趣旨に沿う形で別のパターンを任意に形成することが可能である。   Further, the positions and number of the heat radiation vias 9 shown in FIGS. 10 to 11 and the wiring patterns of the wiring layers 6 to 7 shown in FIG. 10 or 12 are merely schematic examples, and the electrode terminals 4 and Except for the presence of the wiring connecting the heat radiating vias 9, it is possible to arbitrarily form another pattern in accordance with the spirit of the present invention.

（実施例５）
機能素子内蔵基板２００乃至４００の特徴である、放熱材５端部の凹凸パターン、層間ビア８、放熱ビア９はひとつの構造に組み合わせることが可能であって、図１３乃至図１５は、これら全ての要素を組み合わせた本発明の第５の実施例に係る機能素子内蔵基板５００の、縦断面図、機能素子内蔵層の水平断面図（図１３のＣ−Ｃ断面）、上面配線層の平面図をそれぞれ示している。機能素子内蔵基板５００では、機能素子内蔵基板２００乃至４００の特徴を備えていることにより、放熱効果と配線設計自由度が向上している。尚、図１３（ａ）は、放熱材５が凸である部分の断面図（図１４のＡ−Ａ断面）、図１３（ｂ）は、放熱材５が凹である部分の断面図（図１４のＢ−Ｂ断面）である。 (Example 5)
The concave / convex pattern at the end of the heat dissipating material 5, the interlayer via 8, and the heat dissipating via 9, which are the features of the functional element built-in substrates 200 to 400, can be combined into one structure. FIG. 13 to FIG. FIG. 13 is a longitudinal sectional view, a horizontal sectional view of a functional element built-in layer (CC cross section in FIG. 13), and a plan view of an upper wiring layer. Respectively. Since the functional element-embedded substrate 500 has the features of the functional element-embedded substrates 200 to 400, the heat dissipation effect and the wiring design freedom are improved. 13A is a cross-sectional view of the portion where the heat dissipating material 5 is convex (cross section AA in FIG. 14), and FIG. 13B is a cross-sectional view of the portion where the heat dissipating material 5 is concave (FIG. 13). 14 is a BB cross section).

また図１３乃至１４に示されている層間ビア８の位置及び数、放熱ビア９の位置及び数、図１３または図１５に示されている上部配線層６乃至７の配線パターンは、あくまで模式的な一例であり、電極端子４と層間ビア８を接続する配線及び電極端子４と放熱ビア９を接続する配線が存在することを除いては、本発明の趣旨に沿う形で別のパターンを任意に形成することが可能である。   Further, the position and number of the interlayer vias 8 shown in FIGS. 13 to 14, the position and number of the heat dissipation vias 9, and the wiring patterns of the upper wiring layers 6 to 7 shown in FIG. 13 or FIG. In this example, a different pattern can be arbitrarily formed in accordance with the spirit of the present invention except that there is a wiring connecting the electrode terminal 4 and the interlayer via 8 and a wiring connecting the electrode terminal 4 and the heat dissipation via 9. Can be formed.

尚、機能素子内蔵基板２００乃至４００で述べられた特徴は機能素子内蔵基板５００のように全てを一度に組み合わせる必要はなく、たとえば放熱ビアと層間ビアを組み合わせただけでも、機能素子内蔵基板３００乃至４００において述べられた効果を同時に得られる。   The features described in the functional element built-in substrates 200 to 400 do not need to be combined all at once as in the functional element built-in substrate 500. For example, the functional element built-in substrates 300 to 400 can be combined only by combining heat dissipation vias and interlayer vias. The effects described in 400 can be obtained simultaneously.

（実施例６）
図１６は、本発明の第６の実施例に係る機能素子内蔵基板６００の断面図である。機能素子内蔵基板６００は、機能素子内蔵基板５００に加え、配線層６側に絶縁層１０を介して配線層１４を、配線層７側に絶縁層１１を介して配線層１５を配置し、更に両面にソルダーレジスト層１６乃至１７を配置していることを特徴とする。配線層６と配線層１４は層間ビア１２で接続され、配線層７と配線層１５は層間ビア１３で接続されている。層数が増えたことで配線自由度が向上しており、またソルダーレジスト層により外部に接続する端子部分以外を被覆することで最外配線層の配線間の導通等の不具合を抑制する効果が得られる。 (Example 6)
FIG. 16 is a cross-sectional view of a functional element-embedded substrate 600 according to the sixth embodiment of the present invention. In addition to the functional element built-in substrate 500, the functional element built-in substrate 600 has a wiring layer 14 disposed on the wiring layer 6 side through the insulating layer 10, and a wiring layer 15 disposed on the wiring layer 7 side through the insulating layer 11. Solder resist layers 16 to 17 are arranged on both sides. The wiring layer 6 and the wiring layer 14 are connected by an interlayer via 12, and the wiring layer 7 and the wiring layer 15 are connected by an interlayer via 13. Wiring flexibility is improved by increasing the number of layers, and by covering the areas other than the terminal portion connected to the outside with a solder resist layer, there is an effect of suppressing problems such as conduction between wirings of the outermost wiring layer. can get.

（実施例７）
図１７は、本発明の第７の実施例に係る機能素子内蔵基板７００の断面図である。機能素子内蔵基板７００は、機能素子内蔵基板６００を複数積み重ねた構造で、接続端子１８により各々の機能素子内蔵基板６００の配線を接続すると共に、接続端子１９により各々の放熱材５を接続している。機能素子内蔵基板６００の各々の放熱材５を接続することで、放熱効果を効率的に向上させることができる。 (Example 7)
FIG. 17 is a cross-sectional view of a functional element-embedded substrate 700 according to the seventh embodiment of the present invention. The functional element-embedded substrate 700 has a structure in which a plurality of functional element-embedded substrates 600 are stacked, and the wiring of each functional element-embedded substrate 600 is connected by the connection terminals 18 and each heat dissipation material 5 is connected by the connection terminals 19. Yes. By connecting the heat dissipating members 5 of the functional element built-in substrate 600, the heat dissipating effect can be improved efficiently.

尚、機能素子内蔵基板６００乃至７００においては、そのコアに機能素子内蔵基板５００を用いているが、コアとして、機能素子内蔵基板１００乃至４００を用いてもよい。   In the functional element built-in substrates 600 to 700, the functional element built-in substrate 500 is used as the core, but the functional element built-in substrates 100 to 400 may be used as the core.

（実施例８）
図１８乃至図１９は、機能素子内蔵基板６００乃至７００をマザーボード２２へ実装した場合の第８の実施例の断面図である。本実施例において、機能素子内蔵基板６００及び７００はマザーボードに接続端子２０によって配線が接続されると共に、接続端子２１により放熱材５もマザーボードに接続されている。マザーボードに放熱材が接続されることで、放熱効果が向上している。また機能素子内蔵基板６００乃至７００の各々の放熱ビア９にグランド配線を接続し、かつマザーボードのグランド配線（図示せず）に接続端子２１を接続すれば、グランド配線を別途設ける必要がなくなり、配線設計自由度が向上する。またグランド配線を別途設けている場合でも、グランドの電圧が更に安定することにより、信号品質の向上に寄与する。 (Example 8)
18 to 19 are cross-sectional views of the eighth embodiment when the functional element built-in substrates 600 to 700 are mounted on the mother board 22. In the present embodiment, the functional element built-in substrates 600 and 700 are connected to the mother board by the connection terminals 20, and the heat dissipation material 5 is also connected to the mother board by the connection terminals 21. The heat dissipation effect is improved by connecting the heat dissipation material to the motherboard. Further, if a ground wiring is connected to each heat radiation via 9 of each of the functional element built-in substrates 600 to 700 and a connection terminal 21 is connected to a ground wiring (not shown) of the mother board, there is no need to separately provide a ground wiring. Design freedom is improved. Even when ground wiring is separately provided, the ground voltage is further stabilized, which contributes to improvement in signal quality.

図２０〜図３３は、本発明の第５実施例に係る機能素子内蔵基板５００の第一の製造方法例について、各製造段階（ａ）〜（ｎ）の縦断面図、及び、特に平面図を示す必要のある製造段階における平面図である。   20 to 33 are vertical cross-sectional views of manufacturing steps (a) to (n) and particularly plan views of the first manufacturing method example of the functional element-embedded substrate 500 according to the fifth embodiment of the present invention. It is a top view in the manufacturing stage which needs to show.

図２０（ａ）の断面図（図２１のＡ−Ａ断面）に示すように、まず、層間ビア用開口部２３および機能素子用開口部２４を設けた放熱材５を用意する。層間ビア用開口部２３、機能素子用開口部２４の形成方法は、放熱材５が金属材料の場合はエッチング法が、それ以外の場合はプレス法が好適に使用されるがこれに限定されない。一方図２１に開口部２３、２４を設けた状態の放熱材５の平面図を示す。尚放熱材５が樹脂材である場合は、開口部２３、２４を設ける前に硬化させるプロセスが好適であるが、これに限定されない。   As shown in the cross-sectional view of FIG. 20A (cross-section AA in FIG. 21), first, the heat dissipating material 5 provided with the interlayer via opening 23 and the functional element opening 24 is prepared. The method for forming the interlayer via opening 23 and the functional element opening 24 is not limited to this, although the etching method is suitably used when the heat dissipating material 5 is a metal material, and the pressing method is used otherwise. On the other hand, FIG. 21 shows a plan view of the heat dissipating material 5 in a state where the openings 23 and 24 are provided. When the heat dissipating material 5 is a resin material, a process of curing before providing the openings 23 and 24 is suitable, but the present invention is not limited to this.

図２０（ａ）、図２１における開口部２３乃至２４の位置、数、径の大きさは、模式的な一例であって、本発明の趣旨に沿う範囲で任意に定められる。また、本製造例は機能素子内蔵基板５００を製造する方法を示しているため開口部２３乃至２４の双方が必要とされるが、機能素子内蔵基板１００乃至２００または４００を製造する場合は、層間ビア用開口部２３は必要とされない。   The positions, numbers, and diameters of the openings 23 to 24 in FIG. 20A and FIG. 21 are schematic examples, and are arbitrarily determined within the scope of the present invention. Further, since this manufacturing example shows a method of manufacturing the functional element-embedded substrate 500, both the openings 23 to 24 are required. However, when the functional element-embedded substrate 100 to 200 or 400 is manufactured, an interlayer is used. The via opening 23 is not required.

続く工程において、図２０（ｂ）に示すように、補強材５の一方の主面から、基材２６上にシート状に形成された未硬化絶縁材２５を、放熱材５側に向けて供給する。未硬化絶縁材２５の供給の方法は、ラミネート法が好適に使用されるがこれに限定されない。未硬化絶縁材２５には、エポキシ、ポリイミド、液晶ポリマーなどをベースとしたものが好適であるが、それらに限定されない。基材２６は、ポリエチレンテレフタラート系の樹脂またはＣｕ等の金属箔が好適に使用されるがこれに限定されない。   In the subsequent process, as shown in FIG. 20B, the uncured insulating material 25 formed in a sheet shape on the base material 26 is supplied toward the heat radiating material 5 from one main surface of the reinforcing material 5. To do. As a method for supplying the uncured insulating material 25, a laminating method is preferably used, but not limited thereto. The uncured insulating material 25 is preferably based on epoxy, polyimide, liquid crystal polymer or the like, but is not limited thereto. As the base material 26, polyethylene terephthalate resin or metal foil such as Cu is preferably used, but is not limited thereto.

その後、図２０（ｃ）に示すように、機能素子１を、未硬化絶縁材２５が供給された面とは反対の側から搭載する。機能素子１には予め、回路面２上に、円柱状、もしくは一層以上の配線から成る電極端子４が設けられるが、そのほかに金のスタッドバンプも使用することが可能であり、電極端子４の形状はこれらに限定されない。電極端子４の材質も、銅、金、ニッケル等から成るがこれらに限定されない。尚、機能素子１の搭載に際して、予め放熱材５の機能素子１を搭載する側にアライメントマークを設けておけば精度よく搭載することができるが、本発明を実施する上で放熱材５にアライメントマークを設けることは必須ではない。   Thereafter, as shown in FIG. 20C, the functional element 1 is mounted from the side opposite to the surface supplied with the uncured insulating material 25. The functional element 1 is previously provided with an electrode terminal 4 made of a cylindrical shape or one or more wirings on the circuit surface 2, but a gold stud bump can also be used. The shape is not limited to these. The material of the electrode terminal 4 is also made of copper, gold, nickel or the like, but is not limited thereto. When the functional element 1 is mounted, it can be mounted with high precision if an alignment mark is provided on the side of the heat radiating material 5 on which the functional element 1 is mounted in advance. It is not essential to provide a mark.

続いて、機能素子１を搭載した側の放熱材５の他方の主面に基材２８上にシート状に形成された未硬化絶縁材２７を、放熱材５及び機能素子１側に向けて供給する。この際、未硬化絶縁材２７により機能素子１と開口部２４の間隙、及び開口部２３は充填される。未硬化絶縁材２７の供給の方法は、ラミネート法が好適に使用されるがこれに限定されない。未硬化絶縁材２７には、エポキシ、ポリイミド、液晶ポリマーなどをベースとしたものが好適であるが、それらに限定されない。また未硬化絶縁材２７には、未硬化絶縁材２５と同種の樹脂を用いることが、二つの未硬化絶縁材の熱膨張係数・弾性率等の物理的な諸定数の差による残留応力等を回避する上で好適であるが、これに限定されない。基材２８は、ポリエチレンテレフタラート系の樹脂フィルムまたはＣｕ等の金属箔が好適に使用されるがこれに限定されない。本工程において、未硬化絶縁材２５及び未硬化絶縁材２７に同種の材料を使用していた場合は、２つの未硬化樹脂絶縁材は一体化する。   Subsequently, an uncured insulating material 27 formed in a sheet shape on the base 28 on the other main surface of the heat dissipation material 5 on the side where the functional element 1 is mounted is supplied toward the heat dissipation material 5 and the functional element 1 side. To do. At this time, the gap between the functional element 1 and the opening 24 and the opening 23 are filled with the uncured insulating material 27. As a method for supplying the uncured insulating material 27, a laminating method is preferably used, but not limited thereto. The uncured insulating material 27 is preferably based on epoxy, polyimide, liquid crystal polymer, or the like, but is not limited thereto. The uncured insulating material 27 is made of the same resin as that of the uncured insulating material 25, so that residual stress due to differences in physical constants such as thermal expansion coefficient and elastic modulus of the two uncured insulating materials can be reduced. Although it is suitable in avoiding, it is not limited to this. As the base material 28, a polyethylene terephthalate-based resin film or a metal foil such as Cu is preferably used, but is not limited thereto. In this step, when the same kind of material is used for the uncured insulating material 25 and the uncured insulating material 27, the two uncured resin insulating materials are integrated.

続く工程において、図２２（ｅ）に示すように、未硬化絶縁材２５及び未硬化絶縁材２７を一括して硬化し、絶縁層３とした後、基材２６および２８を除去する。未硬化絶縁材２５と未硬化絶縁材２７が別種の材料の場合でも、以後該２つの絶縁材を区別せず、絶縁層３とする。除去の方法は、基材２６または２８が樹脂の場合には直接剥離等、金属箔の場合にはエッチング等の方法が好適に使用されるがこれらに限定されない。   In the subsequent process, as shown in FIG. 22E, the uncured insulating material 25 and the uncured insulating material 27 are collectively cured to form the insulating layer 3, and then the base materials 26 and 28 are removed. Even when the uncured insulating material 25 and the uncured insulating material 27 are different types of materials, the two insulating materials are not distinguished from each other and are referred to as the insulating layer 3. The removal method is preferably, for example, direct peeling or the like when the substrate 26 or 28 is a resin, or etching or the like when the substrate 26 is a metal foil, but is not limited thereto.

その後、図２２（ｆ）に示すように、研削装置やバフ研磨装置等を使用して、絶縁層３の、機能素子１の回路面２側の主面を研磨し、電極端子４を露出させる。   After that, as shown in FIG. 22 (f), the main surface of the insulating layer 3 on the circuit surface 2 side of the functional element 1 is polished by using a grinding device, a buffing device, or the like to expose the electrode terminals 4. .

その後、図２２（ｇ）に断面図を、図２３に平面図を示すように、層間ビア用ビアホール２９、放熱ビア用ビアホール３０、放熱材用ビアホール３１を形成する。なお、図２３の平面図においては、わかりやすくするため、絶縁層３を示す斜線模様を省略している（以下平面図において同様）。ビアホール形成方法は、ビアホール２９、３０に関しては径の小さいビアホールも形成可能であることからレーザーが好適に使用されるがこれに限定されない。ビアホール３１に関してはレーザーまたはドリルが好適に使用されるがこれらに限定されない。   Then, as shown in a sectional view in FIG. 22G and a plan view in FIG. 23, an interlayer via via hole 29, a heat radiating via hole 30, and a heat radiating material via hole 31 are formed. In the plan view of FIG. 23, for the sake of clarity, the hatched pattern indicating the insulating layer 3 is omitted (the same applies to the plan view below). As for the via hole formation method, the via holes 29 and 30 can be formed with small diameter via holes, but a laser is preferably used, but is not limited thereto. For the via hole 31, a laser or a drill is preferably used, but is not limited thereto.

図２３の平面図において、パッケージの角となる部分の放熱材用ビアホール３１をやや大きくすれば、パッケージダイシングの際のダイシングラインの起点及び終点の位置調整等のマージンを設けることが容易になり、好適である。また、放熱材用ビアホール３１の直径は、一般の基板のダイシングの精度より十分に大きく、また放熱材用ビアホール３１の形成コストが十分に低減できる条件を満たすことが望ましく、１００μｍ〜２００μｍの間が好適であるが、これに限定されない。   In the plan view of FIG. 23, if the heat-dissipating material via hole 31 at the corner of the package is made slightly larger, it becomes easy to provide margins for adjusting the position of the starting and end points of the dicing line during package dicing, Is preferred. Moreover, it is desirable that the diameter of the heat radiating material via hole 31 is sufficiently larger than the dicing accuracy of a general substrate, and that it satisfies the condition that the cost of forming the heat radiating material via hole 31 can be sufficiently reduced. Although it is suitable, it is not limited to this.

また、本製造例は機能素子内蔵基板５００を製造する方法を示しているため層間ビア用ビアホール２９乃至放熱ビア用ビアホール３０の双方が必要とされるが、機能素子内蔵基板１００乃至２００または４００を製造する場合は、層間ビア用ビアホール２９は必要とされない。また機能素子内蔵基板１００乃至３００を製造する場合は、放熱ビア用ビアホール３０は必要とされない。   Further, since this manufacturing example shows a method of manufacturing the functional element built-in substrate 500, both the interlayer via via hole 29 to the heat radiating via hole 30 are required, but the functional element built-in substrate 100 to 200 or 400 is used. In the case of manufacturing, the via hole 29 for interlayer via is not required. Further, when the functional element built-in substrates 100 to 300 are manufactured, the heat radiating via hole 30 is not required.

図２２、図２３における放熱材用ビアホール３１の位置、数、径の大きさは、模式的な一例であって、本発明の趣旨に沿う範囲で任意に定められる。例えば、技術的またはコスト的な制約から放熱材用ビアホール３１の径を大きくできない場合には、図２４のように、ジグザグに放熱材用ビアホール３１を設ければ、後に凹凸形状を設けるときにも比較的小さなビアホール径で対応できる。また、技術的またはコスト的な制約から、図２５のように、パッケージの外周部全てに放熱材用ビアホール３１を形成できない場合でも、本発明の趣旨はある程度達成できる。図２５において、放熱材用ビアホール３１の間隔は、放熱効率の著しく低下する限界を考慮すれば、放熱材用ビアホール３１の直径の１乃至２倍が好適であるが、これに限定されない。   The positions, the number, and the diameter of the heat radiating material via holes 31 in FIGS. 22 and 23 are schematic examples, and are arbitrarily determined within the scope of the present invention. For example, if the diameter of the heat dissipation material via hole 31 cannot be increased due to technical or cost restrictions, if the heat dissipation material via hole 31 is provided in a zigzag manner as shown in FIG. It can be handled with a relatively small via hole diameter. Further, even if the heat radiating material via hole 31 cannot be formed in the entire outer periphery of the package as shown in FIG. 25 due to technical or cost restrictions, the gist of the present invention can be achieved to some extent. In FIG. 25, the distance between the heat radiating material via holes 31 is preferably 1 to 2 times the diameter of the heat radiating material via holes 31 in consideration of the limit that the heat radiating efficiency is remarkably lowered, but is not limited thereto.

続いて露出した電極端子４の表面部分の研磨くずである樹脂残渣及び各ビアホール２９、３０、３１内に存在するビアホール形成時の樹脂残渣などを取り除く為、希硫酸洗浄またはデスミア処理を行うが、樹脂残渣等の除去の方法はこれに限定されない。   Subsequently, in order to remove the resin residue which is polishing scraps of the exposed surface portion of the electrode terminal 4 and the resin residue at the time of forming the via hole in each of the via holes 29, 30 and 31, a dilute sulfuric acid cleaning or desmear treatment is performed. The method for removing resin residues and the like is not limited to this.

続いて、図２２（ｈ）に示すように、銅、ニッケルなどの無電解めっき又は、チタン、タングステン、クロム、白金、金、銅、ニッケル、銀、スズ、鉛からなる一つ以上元素による一層以上の導電層をスパッタ処理により形成し、続くめっき工程のためのめっきシード層３２とする。（めっき）シード層３２の形成の方法は、無電解、スパッタ処理に限定されない。   Subsequently, as shown in FIG. 22 (h), electroless plating such as copper or nickel, or one or more layers made of titanium, tungsten, chromium, platinum, gold, copper, nickel, silver, tin, or lead. The above conductive layer is formed by sputtering, and is used as a plating seed layer 32 for the subsequent plating process. (Plating) The method of forming the seed layer 32 is not limited to electroless and sputtering.

続く工程において、図２６（ｉ）のようにめっきレジスト層（図示せず）を形成して、該レジストパターンをマスクとして電解めっきにより、配線層６、層間ビアの回路面側部分３３、放熱材の回路面側拡張部分３４を形成する。層間ビアの回路面側部分３３は、フィルドビア形状またはコンフォーマルビア形状を任意に選択できる。しかし放熱材の回路面側拡張部分３４は、本発明の趣旨から、フィルドビア形状とすることが好ましい。   In the subsequent process, a plating resist layer (not shown) is formed as shown in FIG. 26 (i), and the wiring layer 6, the circuit surface side portion 33 of the interlayer via, and the heat dissipation material are electroplated using the resist pattern as a mask. The circuit surface side extended portion 34 is formed. For the circuit surface side portion 33 of the interlayer via, a filled via shape or a conformal via shape can be arbitrarily selected. However, it is preferable that the circuit surface side extended portion 34 of the heat dissipation material has a filled via shape for the purpose of the present invention.

その後図２６（ｊ）のようにめっきレジストを取り除き配線層以外のめっきシード層をエッチングする。尚、該めっき法より形成される部分は、銅、ニッケル、金、銀などの一種類以上の金属が好適であるが、それらに限定されない。また、配線層６、層間ビアの回路面側部分３３、放熱材の回路面側拡張部分３４の形成方法も、上記に述べた方法に限定されず、たとえば印刷法等を用いても良い。めっき法を用いない場合、必ずしもシード層３２は必要とされない。   Thereafter, as shown in FIG. 26J, the plating resist is removed and the plating seed layer other than the wiring layer is etched. In addition, although one or more types of metals, such as copper, nickel, gold | metal | money, silver, are suitable for the part formed by this plating method, it is not limited to them. Also, the method of forming the wiring layer 6, the circuit surface side portion 33 of the interlayer via, and the circuit surface side extended portion 34 of the heat radiation material is not limited to the method described above, and for example, a printing method or the like may be used. When the plating method is not used, the seed layer 32 is not necessarily required.

その後、図２６（ｋ）に示すように、回路面の反対側においてもシード層３５を形成し、さらに図２７（ｌ）及び図２７（ｍ）に示すように、シード層３５を用いためっき工程によって、導体配線層７、層間ビアの回路面反対側部分３６、放熱材の回路面反対側拡張部分３７を形成する。尚、該めっき法より形成される部分は、銅、ニッケル、金、銀などの一種類以上の金属が好適であるが、それらに限定されない。また、配線層６、層間ビアの回路面反対側部分３６、放熱材の回路面反対側拡張部分３７の形成方法も、上記に述べた方法に限定されず、たとえば印刷法等を用いても良い。めっき法を用いない場合、必ずしもシード層３５は必要とされない。層間ビアの回路面反対側部分３６は、フィルドビア形状またはコンフォーマルビア形状を任意に選択できる。しかし放熱材の回路面反対側拡張部分３７は、本発明の趣旨から、フィルドビア形状とすることが好ましい。   Thereafter, as shown in FIG. 26 (k), a seed layer 35 is also formed on the opposite side of the circuit surface. Further, as shown in FIGS. 27 (l) and 27 (m), plating using the seed layer 35 is performed. According to the process, the conductor wiring layer 7, the inter-layer via circuit surface opposite side portion 36, and the heat dissipation material circuit surface opposite side extended portion 37 are formed. In addition, although one or more types of metals, such as copper, nickel, gold | metal | money, silver, are suitable for the part formed by this plating method, it is not limited to them. Further, the method of forming the wiring layer 6, the inter-layer via circuit surface opposite side portion 36, and the heat radiation material opposite side circuit surface extended portion 37 is not limited to the method described above, and for example, a printing method or the like may be used. . When the plating method is not used, the seed layer 35 is not necessarily required. The inter-layer via circuit surface opposite side portion 36 can arbitrarily select a filled via shape or a conformal via shape. However, it is preferable that the extended portion 37 on the opposite side of the circuit surface of the heat dissipation material has a filled via shape for the purpose of the invention.

本工程以降、放熱材５、放熱材の回路面側拡張部分３４、放熱材の回路面反対側拡張部分３７及びそれらの間に存在するシード層３２、３５の一部は一体として扱い、区別せず放熱材５とする。また、層間ビアの回路面側の部分３３、層間ビアの回路面反対側の部分３６及びそれらの間に存在するシード層３２、３５の一部も一体として扱い、区別せず層間ビア８とする。配線層６と配線層６の部分に存在するシード層３２の一部、配線層７と配線層７の部分に存在するシード層３５の一部も、同様に区別せず一体として扱い、それぞれ配線層６、配線層７とする。放熱ビア９と、放熱ビア９の部分に存在するシード層３２の一部も、区別せず一体として扱い、放熱ビア９とする。   After this step, the heat dissipating material 5, the circuit surface side extended portion 34 of the heat dissipating material, the expansion portion 37 opposite to the circuit surface of the heat dissipating material, and part of the seed layers 32, 35 existing between them are treated as a single unit and distinguished. The heat dissipating material 5 is used. Further, a part 33 on the circuit surface side of the interlayer via, a part 36 on the opposite side of the circuit surface of the interlayer via, and a part of the seed layers 32 and 35 existing between them are treated as one body, and are referred to as the interlayer via 8 without distinction. . Similarly, the wiring layer 6 and part of the seed layer 32 existing in the wiring layer 6 part and the part of the seed layer 35 existing in the wiring layer 7 and part of the wiring layer 7 are also treated as one piece without distinction, respectively. Layer 6 and wiring layer 7 are used. The heat radiating via 9 and a part of the seed layer 32 existing in the portion of the heat radiating via 9 are also handled as one body without being distinguished from each other, and are referred to as the heat radiating via 9.

また、本製造例は機能素子内蔵基板５００を製造する方法を示しているため、図２２（ｇ）、（ｈ）、図２６（ｉ）〜（ｋ）、図２７（ｌ）、（ｍ）の工程において、層間ビアの部分３３、３６、シード層３２、３５の一部を経て層間ビア８を形成することが必要とされるが、機能素子内蔵基板１００乃至２００または４００を製造する場合、これらは必要とされない。同様に、同じ工程において、放熱ビア９及びシード層３２の一部を経て放熱ビア９を形成することが必要とされるが、機能素子内蔵基板１００乃至３００を製造する場合、これらは必要とされない。   Further, since this manufacturing example shows a method of manufacturing the functional element-embedded substrate 500, FIGS. 22 (g), (h), FIGS. 26 (i) to (k), FIGS. 27 (l), (m). In this process, it is necessary to form the interlayer via 8 through the interlayer via portions 33 and 36 and part of the seed layers 32 and 35. When manufacturing the functional element embedded substrate 100 to 200 or 400, These are not needed. Similarly, in the same process, it is necessary to form the heat dissipation via 9 through the heat dissipation via 9 and part of the seed layer 32, but these are not required when the functional element built-in substrates 100 to 300 are manufactured. .

続いて、図２７（ｎ）に断面図、図２８にその平面図で示すように、ダイシングライン３８に沿ってダイシングを行い、図３１（断面図）及び図３２（平面図）に示すように個片化する。尚、本製造例は機能素子内蔵基板５００を製造する方法を示しているため、図２８の平面図においてダイシングライン３８は凹凸の形状をしているが、機能素子内蔵基板１００または３００乃至４００を製造する場合は、該凹凸形状は必要とされない。   Subsequently, as shown in a sectional view in FIG. 27 (n) and a plan view in FIG. 28, dicing is performed along a dicing line 38, as shown in FIG. 31 (sectional view) and FIG. 32 (plan view). Divide into pieces. Since the present manufacturing example shows a method for manufacturing the functional element built-in substrate 500, the dicing line 38 has an uneven shape in the plan view of FIG. 28, but the functional element built-in substrate 100 or 300 to 400 is formed. In the case of manufacturing, the uneven shape is not required.

また、図２９に平面図で示すように、図２４においてビアホール３１をジグザグに設けていた場合には、該ジグザグ形状に沿って凹凸形状にダイシングライン３８を設定することもできる。ダイシングライン３８は凹凸形状ではなくジグザグ形状でもよい。あるいは、本特許の趣旨に沿った上記以外の別の形状でもよい。更に、機能素子内蔵基板５００ではなく、機能素子内蔵基板１００、または３００乃至４００を製造する場合には、ダイシングライン３８を直線としてもよい。図２５においてビアホール３１を互いに離して形成した場合には、図３０に示すように、特にこの方法が好適である。   29, when the via hole 31 is provided in a zigzag shape in FIG. 24, the dicing line 38 can also be set in an uneven shape along the zigzag shape. The dicing line 38 may have a zigzag shape instead of an uneven shape. Alternatively, other shapes other than those described above may be used in accordance with the spirit of this patent. Furthermore, when the functional element built-in substrate 100 or 300 to 400 is manufactured instead of the functional element built-in substrate 500, the dicing line 38 may be a straight line. 25, when the via holes 31 are formed apart from each other, this method is particularly suitable as shown in FIG.

更に、本製造例は機能素子内蔵基板５００を製造する方法を示しているため、図２７（ｍ）の工程の後、図２７（ｎ）、図３１（図３２）に示すようにパッケージダイシングを行うが、機能素子内蔵基板６００を製造する場合には、図２７（ｎ）、図３１（図３２）の工程を行わず、図２７（ｍ）の工程の後、図２２（ｇ）、（ｈ）、図２６（ｉ）〜（ｋ）、図２７（ｌ）、（ｍ）に示す工程と同様にして絶縁層１０乃至１１、層間ビア１２乃至１３、配線層１４乃至１５を形成すると共に放熱材５を拡張し、更にソルダーレジスト層１６乃至１７を形成して、その後図２７（ｎ）、図３１（図３２）と同様にしてダイシングを行う。   Furthermore, since this manufacturing example shows a method for manufacturing the functional element-embedded substrate 500, package dicing is performed as shown in FIGS. 27 (n) and 31 (FIG. 32) after the step of FIG. 27 (m). However, when the functional element-embedded substrate 600 is manufactured, the steps of FIG. 27 (n) and FIG. 31 (FIG. 32) are not performed, and after the step of FIG. 27 (m), FIG. h), insulating layers 10 to 11, interlayer vias 12 to 13, and wiring layers 14 to 15 are formed in the same manner as in the steps shown in FIGS. 26 (i) to (k), 27 (l), and (m). The heat dissipating material 5 is expanded, solder resist layers 16 to 17 are further formed, and then dicing is performed in the same manner as in FIGS. 27 (n) and 31 (FIG. 32).

尚、図３１において、ダイシングライン３８によって切断されたことにより形成された放熱材５の側面の実線は、放熱材５が凸である部分の断面を、破線は、放熱材５が凹である部分の断面を示す。このとき、図３２に平面図を示すように、凹凸のダイシングライン３８で切断したことにより、切り離された機能素子内蔵基板の放熱材５の端部も凹凸となる。また、図３３に示すように、図３０のようにダイシングライン３８を直線とした場合には、切り離された内蔵基板の端部も直線となる。   In FIG. 31, the solid line on the side surface of the heat dissipating material 5 formed by being cut by the dicing line 38 indicates the cross section of the portion where the heat dissipating material 5 is convex, and the broken line indicates the portion where the heat dissipating material 5 is concave. The cross section of is shown. At this time, as shown in a plan view in FIG. 32, the end of the heat radiating material 5 of the functional element-embedded substrate that has been cut off becomes uneven by cutting along the uneven dicing line 38. As shown in FIG. 33, when the dicing line 38 is a straight line as shown in FIG. 30, the end portion of the separated built-in substrate is also a straight line.

図３４は、本発明の第５実施例に係る機能素子内蔵基板５００について、図２０〜３３に示す第一の製造方法例に基づき製造した場合の、より詳細な断面図である。放熱材５の拡張部分及び層間ビア８、放熱ビア９の断面は、めっき法により製造した場合にはテーパー形状となっている。尚、図３４（ａ）は、放熱材５が凸である部分の断面図、図３４（ｂ）は、放熱材５が凹である部分の断面図である。   FIG. 34 is a more detailed cross-sectional view of the functional element-embedded substrate 500 according to the fifth embodiment of the present invention when manufactured based on the first manufacturing method example shown in FIGS. The expanded portion of the heat dissipating material 5 and the cross sections of the interlayer via 8 and the heat dissipating via 9 are tapered when manufactured by plating. 34A is a cross-sectional view of a portion where the heat dissipating material 5 is convex, and FIG. 34B is a cross-sectional view of a portion where the heat dissipating material 5 is concave.

以上、本発明を上記実施形態に即して説明したが、本発明は上記実施形態の構成にのみ制限されるものでなく、本発明の範囲内で当業者であればなし得るであろう各種変形、修正を含むことは勿論である。   The present invention has been described with reference to the above embodiment, but the present invention is not limited only to the configuration of the above embodiment, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, including modifications.

１ 機能素子
２ 回路面
３ 絶縁層
４ 電極端子
５ 放熱材
６ （上部）配線層
７ 配線層
８ 層間ビア
９ 放熱ビア
１０ 絶縁層
１１ 絶縁層
１２ 層間ビア
１３ 層間ビア
１４ 配線層
１５ 配線層
１６ ソルダーレジスト層
１７ ソルダーレジスト層
１８ 接続端子
１９ 接続端子
２０ 接続端子
２１ 接続端子
２２ マザーボード
２３ 層間ビア用開口部
２４ 機能素子用開口部
２５ 未硬化絶縁材
２６ 基材
２７ 未硬化絶縁材
２８ 基材
２９ 層間ビア用ビアホール
３０ 放熱ビア用ビアホール
３１ 放熱材用ビアホール
３２ （めっき）シード層
３３ 層間ビアの回路面側の部分
３４ 放熱材の回路面側拡張部分
３５ （めっき）シード層
３６ 層間ビアの回路面反対側の部分
３７ 放熱材の回路面反対側拡張部分
３８ ダイシングライン
４０ 延在部
１００〜７００ 機能素子内蔵基板 DESCRIPTION OF SYMBOLS 1 Functional element 2 Circuit surface 3 Insulating layer 4 Electrode terminal 5 Heat dissipation material 6 (Upper) Wiring layer 7 Wiring layer 8 Interlayer via 9 Thermal radiation via 10 Insulating layer 11 Insulating layer 12 Interlayer via 13 Interlayer via 14 Wiring layer 15 Wiring layer 16 Solder Resist layer 17 Solder resist layer 18 Connection terminal 19 Connection terminal 20 Connection terminal 21 Connection terminal 22 Motherboard
23 Interlayer Via Opening 24 Functional Element Opening 25 Uncured Insulating Material 26 Base Material 27 Uncured Insulating Material 28 Base Material 29 Interlayer Via Via Hole 30 Heat Dissipation Via Hole 31 Heat Dissipation Via Hole 32 (Plating) Seed Layer 33 Interlayer via circuit surface side portion 34 Heat dissipation material circuit surface side expansion portion 35 (plating) seed layer 36 Interlayer via circuit surface opposite side portion 37 Heat dissipation material circuit surface opposite side expansion portion 38 Dicing line 40 Extension portion 100-700 functional element built-in substrate

Claims (13)

絶縁層と、
該絶縁層に埋設される１以上の機能素子と、
該絶縁層内部の該機能素子の横方向周囲に配された放熱材と、
前記機能素子の回路面側に配設され、前記機能素子の回路面に設けられた電極端子を通じて該機能素子と接続されている第１配線層と、
前記機能素子内蔵基板の前記機能素子回路面側の反対側に配設されている第２配線層と、
前記放熱材及び前記絶縁層を貫通し、前記第１配線層と前記第２配線層とを接続する層間ビアと、
前記放熱材と前記第１配線層とを接続する放熱ビアと、を含み、
前記放熱材が該機能素子内蔵基板の側面部に露出するとともに、少なくとも一部がさらに基板面に直交する方向に亘って延在して形成された延在部を有し、
前記延在部の側面に、凹凸構造が含まれていることを特徴とする、機能素子内蔵基板。 An insulating layer;
One or more functional elements embedded in the insulating layer ;
A heat dissipating material disposed around the lateral direction of the functional element inside the insulating layer;
A first wiring layer disposed on the circuit surface side of the functional element and connected to the functional element through an electrode terminal provided on the circuit surface of the functional element;
A second wiring layer disposed on the side opposite to the functional element circuit surface side of the functional element built-in substrate;
An interlayer via that penetrates the heat dissipation material and the insulating layer and connects the first wiring layer and the second wiring layer;
Look including a heat radiation vias connecting the first wiring layer and the heat radiating member,
The heat radiating material is exposed to the side surface portion of the functional element built-in substrate, and at least a portion further extends in a direction orthogonal to the substrate surface ,
A functional element-embedded substrate characterized in that a concavo-convex structure is included on a side surface of the extending portion . 前記放熱材は、前記絶縁層内部での厚さが前記機能素子の厚さと同じであることを特徴とする、請求項１に記載の機能素子内蔵基板。   2. The functional element-embedded substrate according to claim 1, wherein a thickness of the heat dissipating material inside the insulating layer is the same as a thickness of the functional element. 前記放熱材は、前記基板面に直交する方向の延在部の少なくとも一部の長さが、該基板の配線層を含む厚さと同じであることを特徴とする、請求項１又は２に記載の機能素子内蔵基板。   The length of at least a part of the extending portion in the direction orthogonal to the substrate surface of the heat dissipation material is the same as the thickness including the wiring layer of the substrate. Functional element built-in substrate. 前記放熱材が、金属、樹脂材料、セラミック材料及びカーボンナノチューブ材料のうちの少なくとも１つかならなることを特徴とする、請求項１〜３のいずれか一に記載の機能素子内蔵基板。 The heat dissipating material is a metal, at least 1, characterized by comprising if several, functional elements embedded board according to any one of claims 1 to 3 of the resin material, a ceramic material and a carbon nanotube material. 前記放熱材と前記機能素子が、配線及び放熱ビアのうちの少なくとも１つによって接続されていることを特徴とする、請求項１〜４のいずれか一に記載の機能素子内蔵基板。 At least the one is connected, characterized in that is, functional element embedded board according to any one of claims 1-4 of the heat radiating member and said functional element, wiring and thermal vias. 前記配線及び放熱ビアのうちの少なくとも１つが、前記機能素子のグランドを兼ねることを特徴とする、請求項５に記載の機能素子内蔵基板。   6. The functional element built-in substrate according to claim 5, wherein at least one of the wiring and the heat dissipation via also serves as a ground of the functional element. 前記第１及び第２配線層に加え、さらに一層以上の配線層が配設されていることを特徴とする、請求項１〜６のいずれか一に記載の機能素子内蔵基板。 The addition to the first and second wiring layers, characterized in that it is arranged that one more or more wiring layers, functional device-embedded board according to any one of claims 1-6. 前記放熱材が前記機能素子内蔵基板の側面部に延在している部分と、前記側面部に露出しているのみである部分の比率が、１対１〜１対２の割合になっていることを特徴とする、請求項１〜７のいずれか一に記載の機能素子内蔵基板。 The ratio of the portion where the heat dissipation material extends to the side surface portion of the functional element built-in substrate and the portion exposed only to the side surface portion is a ratio of 1: 1 to 1: 2. characterized in that the functional element-embedded board according to any one of claims 1-7. 前記放熱材の前記側面延在部に接続端子が設置され、かつ信号端子同士も接続された、請求項１〜８のいずれか一に記載の機能素子内蔵基板を複数含むことを特徴とする、半導体装置。 It includes a plurality of functional element-embedded substrates according to any one of claims 1 to 8 , wherein a connection terminal is installed in the side surface extending portion of the heat dissipation material, and signal terminals are also connected to each other. Semiconductor device. 請求項１〜９のいずれか一に記載の機能素子内蔵基板又は半導体装置を含むことを特徴とする、電子機器。 Characterized in that it comprises a functional element embedded board or a semiconductor device according to any one of claims 1 to 9, the electronic device. 開口部に機能素子を配した放熱材の両面側に絶縁層を配する工程と、
該絶縁層の周辺部の少なくとも一部を除去して放熱材用ビアホールを形成する工程と、
前記機能素子の回路面に設けられた電極端子を通じて該機能素子と接続される第１配線層と、前記機能素子内蔵基板の前記機能素子回路面側の反対側に配設される第２配線層とを接続するための、前記放熱材及び前記絶縁層を貫通する層間ビア用ビアホールを形成する工程と、
前記第１配線層と前記放熱材とを接続するための放熱ビア用ビアホールを形成する工程と、
前記放熱材用ビアホールに、さらに放熱部を形成することにより、機能素子内蔵基板外周部の放熱材延在部を形成する工程と、
前記層間ビア用ビアホールに層間ビアを形成する工程と、
前記放熱ビア用ビアホールに放熱ビアを形成する工程と、
前記第１配線層及び第２配線層を形成する工程と、
前記放熱材延在部に凹凸構造が含まれるようにダイシングを行う工程と、
を含むことを特徴とする、機能素子内蔵基板の製造方法。 A step of disposing an insulating layer on both sides of the heat dissipating material in which the functional element is disposed in the opening;
Removing at least a portion of the periphery of the insulating layer to form a heat radiating material via hole;
A first wiring layer connected to the functional element through an electrode terminal provided on the circuit surface of the functional element, and a second wiring layer disposed on the opposite side of the functional element circuit surface side of the functional element built-in substrate Forming a via hole for an interlayer via penetrating the heat radiating material and the insulating layer,
Forming a via hole for heat dissipation via for connecting the first wiring layer and the heat dissipation material;
Forming a heat radiating material extending portion on the outer peripheral portion of the functional element built-in substrate by forming a heat radiating portion in the heat radiating material via hole ; and
Forming an interlayer via in the interlayer via via hole;
Forming a heat dissipation via in the heat dissipation via hole;
Forming the first wiring layer and the second wiring layer;
Dicing so that the heat dissipation material extending portion includes an uneven structure;
The manufacturing method of the board | substrate with a built-in functional element characterized by including these. 前記放熱材延在部の形成にビアホール形成プロセス及びめっきプロセスを用いることを特徴とする、請求項１１に記載の製造方法。 The manufacturing method according to claim 11 , wherein a via hole forming process and a plating process are used for forming the heat radiating material extending portion. 前記機能素子内蔵基板が２つ以上面取りされているワークサイズによって製造されることを特徴とする、請求項１１又は１２に記載の製造方法。 Characterized in that it is produced by the work size the functional element embedded board is more than one chamfering method according to claim 11 or 12.
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