JP2006252360A - Digital circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital circuit capable of performing positive data transfer when not needing high-speed transfer. <P>SOLUTION: A system clock S1 is divided to generate a frequency dividing clock S2 with a sufficiently late transfer timing signal, and transfer data a-e are transferred synchronously with the frequency dividing clock S2. Positive data transfer can thereby be performed by operating based on a slow clock as to a signal requesting accurate data transfer and operation without requesting high-speed transfer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital circuit, and more particularly to a digital circuit that performs data transfer in a clock synchronous manner.

  Conventionally, many digital ICs employ a clock synchronization system for operations inside the digital IC and data transfer between the ICs, and perform various processing signal operations according to the timing.

In a digital circuit typified by such a digital IC, as described in Patent Document 1, variable amount delay means for varying transfer timing of an output signal when data is transferred to an external circuit by synchronous transfer, and A bidirectional buffer for inputting the output signal and the signal from the external circuit, and an input signal sampling means for sampling the input signal from the bidirectional buffer, while transferring the output signal delayed by the variable amount delay means to the external circuit; And a delay amount setting means for controlling the delay amount of the variable amount delay means based on the sampling result of the input signal sampling means.
JP 2002-123485 A

Further, as described in Patent Document 2, a feedback type phase compensator that receives an internal clock signal and a feedback signal and generates a clock signal in which the clock signal and the feedback signal are synchronized, and the feedback A first output circuit for receiving a clock signal formed by the phase compensator, a first external terminal connected to the output terminal of the first output circuit, and a clock signal for the second external terminal. And an input circuit for forming the feedback signal for the feedback type phase compensator.
JP 2002-318638 A

  By the way, even when a synchronous transfer operation is performed, there is a signal that does not require high-speed transfer, and if such a signal is transferred using a clock that operates at high speed, data transfer is performed. There is a problem that it becomes impossible to carry out reliably.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a digital circuit capable of performing reliable data when high-speed transfer is not required.

  In order to solve the above problems, a digital circuit according to the present invention divides a system clock to generate a sufficiently slow transfer timing signal, and at least one of a plurality of data signals and control signals in synchronization with the transfer timing signal. It is configured to perform either transfer.

  Here, it is preferable that the transfer timing signal can be set by delaying the output timing of the signal to be transferred in units of the system clock cycle. In this case, it is preferable that an independent delay time can be set for each of a plurality of signals transferred simultaneously.

  It is preferable to generate a plurality of transfer timing signals having different periods. In this case, it is preferable that the output timing of a signal to be transferred for each of a plurality of transfer timing signals can be set with a delay.

  According to the digital circuit of the present invention, the system clock is divided to generate a sufficiently slow transfer timing signal, and at least one of a plurality of data signals and control signals is transferred in synchronization with the transfer timing signal. With the configuration, a signal that requires accurate data transfer and operation is operated based on a slow clock, so that a sufficient margin can be ensured and reliable data transfer can be performed.

Embodiments of the present invention will be described below with reference to the accompanying drawings. First, a first embodiment of the present invention will be described with reference to FIG.
In the first embodiment, the system clock S changing in synchronization with the high-speed timing signal shown in FIG. 1A is divided, and a sufficiently slow transfer timing signal as shown in FIG. The divided clock SA is generated, and the transfer data a to e are simultaneously transferred in synchronization with the divided clock SA, as shown in FIGS. The transfer data a to e are at least one of a data signal and a control signal transferred between a plurality of circuit blocks in the same semiconductor, and a data signal and a control signal for a peripheral device.

  As described above, when transmitting / receiving at least one of a data signal and a control signal between a plurality of circuit blocks in the same semiconductor and / or a peripheral device, the system clock is divided and transferred sufficiently slowly. By generating a timing signal (divided clock) and transferring at least one of a plurality of data signals and control signals in synchronization with the transfer timing signal, high-speed transfer is not required, but rather accurate Signals that require data transfer and operation can be operated on the basis of a slow clock (transfer timing signal), so that a sufficient margin can be secured and reliable data transfer can be performed.

Next, a second embodiment of the present invention will be described with reference to FIG.
In the second embodiment, by delaying the timing for outputting the transfer data in synchronization with the frequency-divided clock SA, the timing of the internal operation of the IC shown in FIG. 10C and the transfer data shown in FIG. The output operation timing (change timing) is shifted.

  That is, as described above, if a lot of data and control signals are synchronized with the slow clock (divided clock S2), signals are transmitted and received simultaneously for the data and information prepared in that period. As a result, as shown in FIG. 3 (h), the change in power consumption becomes large at the slow clock cycle, which may cause adverse effects such as noise on the internal and peripheral circuits of the IC. There is a risk that highly reliable data transfer cannot be performed.

  Therefore, by shifting the output timing of the transfer data, the internal operation timing and the changing timing are shifted, and the change in power consumption can be dispersed and kept small, and reliable data transfer under stable operation Will be able to do.

Next, a third embodiment of the present invention will be described with reference to FIG.
In the third embodiment, the delay time can be set independently for each signal (each transfer data) at the timing when the transfer data is output in synchronization with the divided clock SA.

  For example, the output timing of the transfer data a is a delay time 0 with respect to the divided clock SA, the transfer data b is a delay time b with respect to the divided clock S2, and the transfer data c is with respect to the divided clock S2. At the delay time c, the transfer data d is set to the delay time d with respect to the divided clock S2, the transfer data e is set to the delay time e with respect to the divided clock S2, and the transfer data is output after the delay time elapses. I am doing so.

  In other words, the transfer timing (transfer data output timing) is changed for each transfer data with respect to the slow transfer timing signal (divided clock) of each signal in units of the high-speed system clock used as the internal timing of the IC. By making it possible to set each signal individually, the change timing of each signal (transfer data) can be varied. As a result, as shown in FIG. 5, changes in power consumption due to changes in signals are smoothed, and the generation of noise that adversely affects data, internal circuits, or IC peripheral circuits is minimized. Can do.

Next, a fourth embodiment of the present invention will be described with reference to FIG.
In the fourth embodiment, a plurality of frequency-divided clocks (transfer timing signals) SA, SB, and SC having different timings are generated from the system clock S as shown in (b), (e), and (g) of FIG. The transfer data a and b are transferred by the divided clock SA, the transfer data c is transferred by the divided clock SB, and the transfer data d and e are transferred by the divided clock SC.

  That is, various functions are integrated in a circuit that divides the original system clock to generate a transfer timing signal that is a slow clock and operates using the generated transfer timing signal (divided clock) as a timing reference. Since the required clock (transfer timing signal) cycle differs depending on the function and performance of each IC, generating a transfer timing signal with a cycle according to each operation generates a timing at which the signal changes. Can be further reduced, and the generation of noise can be suppressed.

Next, a fifth embodiment of the present invention will be described with reference to FIG.
In the fifth embodiment, similarly to the fourth embodiment, the divided clock SA, which is a plurality of transfer timing signals having different timings from the system clock S as shown in FIGS. , SB, SC are generated, the divided clock SA is used for transferring the transfer data a and b, the divided clock SB is used for transferring the transfer data c, and the divided clock SC is used for transferring the transfer data d and e. Similar to the third embodiment, the output timing for outputting the transfer data in synchronization with the divided clock (transfer timing signal) can be delayed independently for each transfer timing signal.

  In other words, in the digital circuit that operates in synchronization with the generated clock, each generating a clock having a necessary period according to the function and performance, for each generated clock, By setting the delay in units of system clocks, the timing of signal changes is dispersed, and the generation of noise that adversely affects the digital IC and peripheral circuits can be suppressed.

It is explanatory drawing with which it uses for description of 1st Embodiment of this invention. It is explanatory drawing with which it uses for description of 2nd Embodiment of this invention. It is explanatory drawing with which it uses for operation | movement description of the same embodiment. It is explanatory drawing with which it uses for description of 3rd Embodiment of this invention. It is explanatory drawing with which it uses for operation | movement description of the same embodiment. It is explanatory drawing with which it uses for description of 4th Embodiment of this invention. It is explanatory drawing with which it uses for description of 5th Embodiment of this invention.

Claims (5)

  In a digital circuit in which a system clock changes in synchronization with a high-speed timing signal, the system clock is divided to generate a sufficiently slow transfer timing signal, and a plurality of data signals and control signals are synchronized with the transfer timing signal. A digital circuit that performs at least one of the transfer operations.   2. The digital circuit according to claim 1, wherein the transfer timing signal can be set by delaying an output timing of the signal to be transferred in units of a cycle of the system clock.   3. The digital circuit according to claim 2, wherein an independent delay time can be set for each of a plurality of signals transferred simultaneously.   2. The digital circuit according to claim 1, wherein a plurality of transfer timing signals having different periods are generated. 5. The digital circuit according to claim 4, wherein an output timing of a signal to be transferred for each of the plurality of transfer timing signals can be set with a delay.

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