JP2005321856A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for making it unnecessary to strictly adjust a delay between different clock signals, and for facilitating synchronization between the different clock signals. <P>SOLUTION: A combination circuit 21 receives output signals of flip flop circuits 11a to 11d, and outputs an interface signal IF_A to a high speed circuit region 10A. A selector 30e selects an interface signal IF_A while an enable control signal ENa is in an H level period, and selects the output feedback signal of a flop flop circuit 11e when the enable control signal ENa is in an L level period. The enable control signal ENa is changed after a high speed signal CLKF is changed, and delayed only in a fixed time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that operates in synchronization with a clock signal.

  In a semiconductor integrated circuit, a method of synchronizing with a clock signal is often used in order to accurately operate a large-scale and complicated circuit. This type of semiconductor integrated circuit generally includes a plurality of logic circuits, a plurality of flip-flop circuits (data holding circuits) for synchronizing them with a clock signal, and a clock generation circuit for generating a clock signal on a semiconductor chip. It is configured by forming. The clock signal output from the clock generation circuit is supplied to flip-flop circuits formed at various locations on the semiconductor chip, and operates the entire semiconductor integrated circuit in synchronization.

  In recent years, semiconductor integrated circuits are required to operate at a higher clock frequency in order to improve the operation speed. On the other hand, in the conventional semiconductor integrated circuit, the entire circuit is operated in synchronization with one clock signal. Therefore, clock skew becomes a problem when the logic scale and chip area of a semiconductor integrated circuit are increased.

  The clock skew is a delay difference between clock signals generated when the clock signal reaches each flip-flop circuit, and tends to increase as the logic scale and chip area of the semiconductor integrated circuit increase. Recent semiconductor integrated circuits tend to have a large logic scale and chip area.

  In the synchronous circuit design as described above, it is important to accurately match the data fetch timings of all synchronized flip-flop circuits (data holding circuits). One technique for accurately adjusting the data fetch timing of the flip-flop circuit is to insert a delay element so that the clock delay from the starting point of the clock signal to each flip-flop circuit is the same.

  In a large-scale system represented by a microcomputer, a system LSI (Large Scale Integrated circuit), etc., the internal modules that make up the system have their respective optimum frequencies depending on the purpose of use and the required processing speed. Often requires a clock signal. For this reason, a dedicated module for generating a plurality of types of clock signals is required in the system.

  Here, paying attention to each module alone, each module alone can basically be controlled by only one type of clock signal among a plurality of types of clock signals. However, when paying attention to the entire system in which a plurality of modules are mixed, there are many cases where it is necessary to transfer data between the modules. Furthermore, the data between the modules is often a system based on the assumption that the data is synchronized.

  A conventional semiconductor integrated circuit (electronic circuit device) uses a single synchronization detection means to detect a synchronization point signal at a synchronization position between a plurality of clocks and use it to obtain data between modules constituting the system. It becomes possible to easily adjust the delivery timing (see, for example, Patent Document 1).

In addition, other conventional semiconductor integrated circuits have a plurality of logical blocks each operating in synchronization with a unique clock signal on the same semiconductor chip, and data transfer between the logical blocks is an asynchronous transfer system. As a result, the range in which the operation synchronized with the clock signal is required can be closed in each logical block (see, for example, Patent Document 2).
JP 2000-353027 A JP 2002-368727 A

  Since the conventional semiconductor integrated circuit that operates in synchronization with the clock signal is configured as described above, it is necessary to adjust the clock skew by inserting a delay element in the clock line in order to achieve synchronization. In particular, if there are two or more types of clock signals, the amount of delay adjustment increases, and the circuit scale increases due to the insertion of delay elements. As a result, there was a problem that the cost was increased. Further, if the circuit design is repeatedly changed by inserting a delay element, there is a problem that it takes a design time until a desired delay amount is obtained.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit that eliminates the need for strictly adjusting delay between different clock signals and facilitates synchronization between different clock signals.

  A semiconductor integrated circuit according to the present invention includes a combinational circuit and a first flip-flop circuit that outputs an input signal to the combinational circuit in synchronization with the first clock signal, and outputs a first interface signal from the combinational circuit. A circuit region, and a second circuit region that operates in synchronization with a second clock signal having a frequency different from that of the first clock signal and receives an interface signal. The second circuit region includes a second clock signal. And the output signal of the second flip-flop circuit is selected and output to the second flip-flop circuit when the first flip-flop circuit outputs the input signal to the combinational circuit. And a selection circuit that selects an interface signal and outputs it to the second flip-flop circuit at a timing different from the timing. No.

  According to the present invention, it is not necessary to strictly adjust the delay between different clock signals, and synchronization between different clock signals can be facilitated.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a schematic configuration diagram showing a schematic configuration of a semiconductor integrated circuit 1A according to the first embodiment of the present invention.

  Referring to FIG. 1, a semiconductor integrated circuit 1A according to the first embodiment includes a low-speed circuit region 20A that operates in synchronization with the rising edge of the low-speed clock signal CLKS, and a high-speed circuit that operates in synchronization with the rising edge of the high-speed clock signal CLKF. A region 10A and an enable signal generation circuit 29A are provided.

  The low speed circuit area 20 </ b> A includes flip-flop circuits (also referred to as FFs) 11 a to 11 d and a combinational circuit 21. All of the flip-flop circuits 11 a to 11 d operate in synchronization with the rising edge of the low-speed clock signal CLKS, temporarily hold the output signal from the combinational circuit 21, and then output it to the combinational circuit 21. The combinational circuit 21 receives the output signals of the flip-flop circuits 11a to 11d and outputs the interface signal IF_A to the high-speed circuit area 10A. The combinational circuit 21 is configured by combining logic elements such as NAND gates and inverters, for example.

  The high-speed circuit area 10A includes flip-flop circuits 11e to 11h, a combinational circuit 22, and a selector (selection circuit) 30e. All of the flip-flop circuits 11e to 11h operate in synchronization with the rising edge of the high-speed clock signal CLKF. The flip-flop circuit 11e temporarily holds the output signal from the selector 30e, and then outputs it to the combinational circuit 22. Each of the flip-flop circuits 11 f to 11 h temporarily holds the output signal from the combinational circuit 22 and then outputs it to the combinational circuit 22. The combinational circuit 22 is configured by combining logic elements such as NAND gates and inverters, for example.

  The enable signal generation circuit 29A outputs an enable control signal ENa to the selector 30e. The selector 30e selects either the output signal of the flip-flop circuit 11e or the interface signal IF_A according to the enable control signal ENa, and outputs it to the flip-flop circuit 11e. Specifically, the selector 30e selects the interface signal IF_A when the enable control signal ENa is at the H level (logic high), and the output of the flip-flop circuit 11e when the enable control signal ENa is at the L level (logic low). Select a signal.

  FIG. 2 is a circuit diagram showing an enable signal generation circuit 29 which is an example of a specific circuit configuration of the enable signal generation circuit 29A.

  Referring to FIG. 2, enable signal generating circuit 29 includes a 3-bit counter 291 and a NAND circuit 294. The 3-bit counter 291 includes a 3-bit flip-flop circuit 292 and an incrementer 293. Note that the circuit configuration of the enable signal generation circuit 29 can also be applied to the enable signal generation circuits of other embodiments.

  The 3-bit flip-flop circuit 292 receives the high-speed clock signal CLKF and outputs a 3-bit output signal EG. The 3-bit flip-flop circuit 292 is reset according to the reset signal RST. The incrementer 293 increments the output of the 3-bit flip-flop circuit 292 and then feeds it back to the input of the 3-bit flip-flop circuit 292. NAND circuit 294 receives 0-bit signal EG0, 1-bit signal EG1, and 2-bit signal EG2 of 3-bit output signal EG, and outputs enable control signal ENa.

  FIG. 3 is a timing chart showing a circuit operation of the enable signal generation circuit 29 which is an example of a specific circuit configuration of the enable signal generation circuit 29A.

  Referring to FIG. 3, the output bit of 3-bit output signal EG changes between “0” and “7” in response to the rising edge of high-speed clock signal CLKF. For example, when all of the 0-bit signal EG0, the 1-bit signal EG1, and the 2-bit signal EG2 are “0”, the 3-bit output signal EG is “0”. When the 0-bit signal EG0 and the 1-bit signal EG1 are “1” and the 2-bit signal EG2 is “0”, the 3-bit output signal EG is “3”.

  When all of the 0-bit signal EG0, the 1-bit signal EG1, and the 2-bit signal EG2 are “1”, the 3-bit output signal EG is “7”. At this time, the output of the enable control signal ENa is inverted from the H level to the L level. As shown in FIG. 3, the enable control signal ENa changes after a predetermined time delay from the change of the high-speed clock signal CLKF.

  FIG. 4 is a timing chart showing the circuit operation of the semiconductor integrated circuit 1A according to the first embodiment of the present invention.

  Referring to FIG. 4, low-speed clock signal CLKS rises at times t2, t5, t8, and t11, and falls at times t3, t6, t9, and t12. The rising speed of the high-speed clock signal CLKF is synchronized with the low-speed clock signal CLKS, and the number of rising times per unit time is eight times that of the low-speed clock signal CLKS. The interface signal IF_A changes in response to the rising edge of the low-speed clock signal CLKS.

  Here, consider a case where the flip-flop circuit 11e of FIG. 1 samples the interface signal IF_A at times t2, t5, t8, and t11 when the rising edges of the low-speed clock signal CLKS and the high-speed clock signal CLKF are synchronized. In this case, there is a possibility that the flip-flop circuit 11e samples a value during the change of the interface signal IF_A because the hold margin has no margin. In particular, when the clock skew between the low-speed clock signal CLKS and the high-speed clock signal CLKF is large, the possibility of erroneous sampling increases.

  Therefore, in the first embodiment, the enable control signal ENa changes after a delay of a predetermined time after the high-speed clock signal CLKF changes. As a result, the enable control signal ENa becomes L level at times t2, t5, t8, and t11 when the rising edges of the low-speed clock signal CLKS and the high-speed clock signal CLKF are synchronized, and the selector 30e in FIG. 1 outputs the output signal of the flip-flop circuit 11e. Select.

  Therefore, the flip-flop circuit 11e reloops its output signal at times t2, t5, t8, and t11. As a result, the flip-flop circuit 11e does not sample the interface signal IF_A at times t2, t5, t8, and t11.

  The interface signal IF_A that is not selected by the selector 30e at the times t2, t5, t8, and t11 is selected by the selector 30e at the times t3, t6, t9, and t12 that are the next rising times of the high-speed clock signal CLKF, and the flip-flop circuit. 11e. Therefore, the flip-flop circuit 11e can receive the interface signal IF_A at a timing with a sufficient hold margin.

  In the first embodiment, the enable control signal ENa has been described as having a waveform as shown in FIG. 4 for convenience of explaining the contents of the invention. However, this is only an example, and the enable control signal ENa is at the L level at the time when the rising edges of the low-speed clock signal CLKS and the high-speed clock signal CLKF are synchronized, that is, the selector 30e selects the output signal of the flip-flop circuit 11e. If you do. Hereinafter, another example of the waveform of the enable control signal ENa is shown.

  FIG. 5 is a timing diagram showing waveforms of enable signals ENA1 to ENA6, which are other examples of waveforms of the enable control signal ENa.

  In FIG. 5A, the enable control signal ENa1 rises after a delay of a fixed time from time t1 when the rising edges of the low-speed clock signal CLKS and the high-speed clock signal CLKF are synchronized, and from time t2 one unit time after time t1. It falls after being delayed for a certain time. In FIG. 5B, the enable control signal ENa2 rises after a certain time delay from the time t1, and falls after a certain time delay from the time t3 two unit time after the time t1. In FIG. 5C, the enable control signal ENa3 rises after a certain time delay from time t1, and falls after a certain time delay from time t4, which is three unit times after time t1.

  In FIG. 5D, the enable control signal ENa4 rises after a certain time delay from the time t1, and falls after a certain time delay from the time t5 four unit time after the time t1. In FIG. 5 (e), the enable control signal ENa5 rises after a certain time delay from time t1, and falls after a certain time delay from time t6, which is five unit times after time t1. In FIG. 5F, the enable control signal ENa6 rises after a certain time delay from time t1, and falls after a certain time delay from time t7, which is six unit times after time t1.

  As described above, according to the first embodiment, the rising edge of the low-speed clock signal CLKS is obtained by re-looping the output signal of the flip-flop circuit 11e at the time when the rising edges of the low-speed clock signal CLKS and the high-speed clock signal CLKF are synchronized. At the time, that is, when the flip-flop circuit 11a outputs the input signal to the combinational circuit 21, the flip-flop circuit 11e does not capture the interface signal IF_A. For this reason, the interface signal IF_A can be transferred between different clocks at a timing with a margin in the hold margin.

[Embodiment 2]
FIG. 6 is a schematic configuration diagram showing a schematic configuration of a semiconductor integrated circuit 1B according to the second embodiment of the present invention.

  Referring to FIG. 6, semiconductor integrated circuit 1B according to the second embodiment includes a high-speed circuit region 10B that operates in synchronization with the rising edge of high-speed clock signal CLKF, and a low-speed circuit that operates in synchronization with the rising edge of low-speed clock signal CLKS. A region 20B and an enable signal generation circuit 29B are provided.

  The high-speed circuit area 10B includes flip-flop circuits 11a to 11d, a combinational circuit 21, and a selector 30a. Each of the flip-flop circuits 11a to 11d operates in synchronization with the rising edge of the high-speed clock signal CLKF. The flip-flop circuit 11a temporarily holds the output signal from the selector 30a, and then outputs it to the low-speed circuit area 20B as the interface signal IF_B. Each of the flip-flop circuits 11 b to 11 d temporarily holds the output signal from the combinational circuit 21 and then outputs it to the combinational circuit 21.

  The enable signal generation circuit 29B outputs an enable control signal ENb to the selector 30a. The selector 30a selects either the output signal of the flip-flop circuit 11a or the signal SBK output from the combinational circuit 21 according to the enable control signal ENb, and outputs it to the flip-flop circuit 11a. Specifically, the selector 30a selects the signal SBK output from the combinational circuit 21 when the enable control signal ENb is at the H level, and outputs the output signal of the flip-flop circuit 11a when the enable control signal ENb is at the L level. select.

  The low speed circuit area 20B includes flip-flop circuits 11e to 11h and a combinational circuit 22. Each of the flip-flop circuits 11e to 11h operates in synchronization with the rising edge of the low-speed clock signal CLKS. The flip-flop circuit 11e temporarily holds the interface signal IF_B from the high-speed circuit area 10B, and then outputs it to the combinational circuit 22. Each of the flip-flop circuits 11 f to 11 h temporarily holds the output signal from the combinational circuit 22 and then outputs it to the combinational circuit 22.

  FIG. 7 is a timing chart showing a circuit operation of the semiconductor integrated circuit 1B according to the second embodiment of the present invention.

  Referring to FIG. 7, low-speed clock signal CLKS rises at times t2, t5, t8, and t11 and falls at times t3, t6, t9, and t12. The rising speed of the high-speed clock signal CLKF is synchronized with the low-speed clock signal CLKS, and the number of rising times per unit time is eight times that of the low-speed clock signal CLKS. When the signal SBK changes at times t2, t5, t8, and t11, the interface signal IF_B changes at times t3, t6, t9, and t12.

  Here, at the times t2, t5, t8, and t11 when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized, the flip-flop circuit 11a in FIG. 6 directly samples the signal SBK without passing through the selector 30a. Think. In this case, there is a possibility that the flip-flop circuit 11e samples a value during the change of the interface signal IF_B because the hold margin has no margin. In particular, when the clock skew between the high-speed clock signal CLKF and the low-speed clock signal CLKS is large, the possibility of erroneous sampling increases.

  Therefore, in the second embodiment, the enable control signal ENb changes after a delay of a fixed time after the high-speed clock signal CLKF changes. As a result, the enable control signal ENb becomes L level at times t2, t5, t8, and t11 when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized, and the selector 30a in FIG. 6 displays the output signal of the flip-flop circuit 11a. Select.

  Therefore, the flip-flop circuit 11a reloops its output signal at times t2, t5, t8, and t11, and the interface signal IF_B does not change. As a result, the flip-flop circuit 11e can sample the interface signal IF_B with a sufficient hold margin at times t2, t5, t8, and t11.

  The signal SBK that is not selected by the selector 30a at times t2, t5, t8, t11 is selected by the selector 30a at times t3, t6, t9, t12, which are the next rising times of the high-speed clock signal CLKF, and the flip-flop circuit 11a. Is output as an interface signal IF_B. The interface signal IF_B is sampled by the flip-flop circuit 11e at the next rising edge of the low-speed clock signal CLKS.

  In the second embodiment, the enable control signal ENb has been described as having a waveform as shown in FIG. 7 for the convenience of explaining the contents of the invention. However, this is only an example, and the enable control signal ENb is at the L level at the time when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized, that is, the selector 30a selects the output signal of the flip-flop circuit 11a. If you do. Other waveform examples of the enable control signal ENa shown in FIG. 5 can also be applied to the enable control signal ENb.

  As described above, according to the second embodiment, the rising edge of the low-speed clock signal CLKS is obtained by re-looping the output signal of the flip-flop circuit 11a at the time when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized. At the time, that is, when the flip-flop circuit 11e outputs the input signal to the combinational circuit 22, the flip-flop circuit 11a does not change the interface signal IF_B. For this reason, the interface signal IF_B can be transferred between different clocks at a timing with a margin in the hold margin.

[Embodiment 3]
FIG. 8 is a schematic configuration diagram showing a schematic configuration of a semiconductor integrated circuit 1C according to the third embodiment of the present invention.

  Referring to FIG. 8, semiconductor integrated circuit 1C according to the third embodiment includes a high-speed circuit region 10C that operates in synchronization with the rising edge of high-speed clock signal CLKF, and a low-speed circuit that operates in synchronization with the rising edge of low-speed clock signal CLKS. A region 20C and an enable signal generation circuit 29C are provided.

  The high-speed circuit region 10C includes flip-flop circuits 11a to 11d, a combinational circuit 21, and selectors 30a to 30d. Each of the flip-flop circuits 11a to 11d operates in synchronization with the rising edge of the high-speed clock signal CLKF, temporarily holds the output signals from the selectors 30a to 30d, and outputs them to the combinational circuit 21. The combinational circuit 21 receives the output signals of the flip-flop circuits 11a to 11d and outputs the interface signal IF_C to the low-speed circuit area 20C.

  The enable signal generation circuit 29C outputs an enable control signal ENa to the selector 30a, and outputs an enable control signal ENb to the selectors 30b to 30d. The selector 30a selects one of the output signal of the flip-flop circuit 11a and the interface signal IF_Ca output from the low-speed circuit area 20C according to the enable control signal ENa, and outputs it to the flip-flop circuit 11a.

  The selector 30b selects either the output signal of the flip-flop circuit 11b or the signal SBKb output from the combinational circuit 21 according to the enable control signal ENb, and outputs it to the flip-flop circuit 11b. The selector 30c selects either the output signal of the flip-flop circuit 11c or the signal SBKc output from the combinational circuit 21 according to the enable control signal ENb, and outputs it to the flip-flop circuit 11c. The selector 30d selects either the output signal of the flip-flop circuit 11d or the signal SBKd output from the combinational circuit 21 according to the enable control signal ENb, and outputs it to the flip-flop circuit 11d.

  Specifically, the selector 30a selects the interface signal IF_Ca when the enable control signal ENa is at the H level, and selects the output signal of the flip-flop circuit 11a when the enable control signal ENa is at the L level.

  The selectors 30b to 30d respectively select signals SBKb to SBKd output from the combinational circuit 21 while the enable control signal ENb is at the H level, and flip-flop circuits 11b to 11d when the enable control signal ENb is at the L level. Output signals are selected respectively. Note that the enable control signal ENa and the enable control signal ENb may be the same signal.

  The low-speed circuit region 20C includes flip-flop circuits 11e to 11h and a combinational circuit 22. Each of the flip-flop circuits 11e to 11h operates in synchronization with the rising edge of the low-speed clock signal CLKS. The flip-flop circuit 11e temporarily holds the interface signal IF_C from the high-speed circuit area 10C, and then outputs it to the combinational circuit 22. Each of the flip-flop circuits 11 f to 11 h temporarily holds the output signal from the combinational circuit 22 and then outputs it to the combinational circuit 22.

  In the third embodiment, as in the first embodiment, the enable control signal ENa changes after a delay of a predetermined time after the high-speed clock signal CLKF changes. Thereby, the selector 30a selects the output signal of the flip-flop circuit 11a at the time when the rising edges of the low-speed clock signal CLKS and the high-speed clock signal CLKF are synchronized.

  Thus, according to the third embodiment, the rising time of the low-speed clock signal CLKS is obtained by re-looping the output signal of the flip-flop circuit 11a at the time when the rising edges of the low-speed clock signal CLKS and the high-speed clock signal CLKF are synchronized. That is, at the timing when the flip-flop circuit 11e outputs the input signal to the combinational circuit 22, the flip-flop circuit 11a does not capture the interface signal IF_Ca. For this reason, the interface signal IF_Ca can be transferred between different clocks at a timing with a margin in the hold margin.

  Further, in the third embodiment, as in the second embodiment, the enable control signal ENb changes after a delay of a predetermined time after the high-speed clock signal CLKF changes. Thereby, the selectors 30b to 30d respectively select the output signals of the flip-flop circuits 11b to 11d at the time when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized.

  As a result, the flip-flop circuits 11b to 11d re-loop their output signals at the time when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized, and the interface signal IF_C remains unchanged. As a result, the flip-flop circuit 11e can sample the interface signal IF_C with a sufficient hold margin at the time when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized.

  The signals SBKb to SBKd that are not selected by the selectors 30b to 30d at the time when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized are selected by the selectors 30b to 30d at the next rising time of the high-speed clock signal CLKF. Output from the flip-flop circuits 11b to 11d as the interface signal IF_C through the combinational circuit 21. The interface signal IF_C is sampled by the flip-flop circuit 11e at the next rising edge of the low-speed clock signal CLKS.

  As described above, according to the third embodiment, the output signals of the flip-flop circuits 11b to 11d are re-looped at the time when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized. At the rising time, that is, at the timing when the flip-flop circuit 11e outputs the input signal to the combinational circuit 22, the flip-flop circuits 11b to 11d do not change the interface signal IF_C. For this reason, the interface signal IF_C can be transferred between different clocks at a timing with a margin in the hold margin.

[Embodiment 4]
FIG. 9 is a schematic configuration diagram showing a schematic configuration of a semiconductor integrated circuit 1D according to the fourth embodiment of the present invention.

  Referring to FIG. 9, semiconductor integrated circuit 1D of the fourth embodiment includes a high-speed circuit region 10D that operates in synchronization with the rising edge of high-speed clock signal CLKF, and a low-speed circuit that operates in synchronization with the rising edge of low-speed clock signal CLKS. A region 20D and an enable signal generation circuit 29D are provided.

  The high-speed circuit area 10D includes flip-flop circuits 11a to 11d, 11p to 11s, combinational circuits 21a to 21c, and selectors 30a to 30d. All of the flip-flop circuits 11a to 11d and 11p to 11s operate in synchronization with the rising edge of the high-speed clock signal CLKF.

  The flip-flop circuits 11a and 11b temporarily hold the output signals from the selectors 30a and 30b, respectively, and then output them to the combinational circuit 21a. The flip-flop circuits 11c and 11d temporarily hold the output signals from the selectors 30c and 30d, respectively, and then output them to the combinational circuit 21b. The flip-flop circuits 11p and 11q temporarily hold the output signals from the combinational circuit 21a, respectively, and then output them to the combinational circuit 21c. The flip-flop circuits 11r and 11s temporarily hold the output signals from the combinational circuit 21c, respectively, and then output them to the combinational circuit 21c.

  The combinational circuit 21a receives the output signals of the flip-flop circuits 11a and 11b and outputs signals to the flip-flop circuits 11p and 11q, respectively. The combinational circuit 21b receives the output signals of the flip-flop circuits 11c and 11d and outputs interface signals IF_D1 and IF_D2 to the low-speed circuit area 20D. The combinational circuit 21c receives the output signals of the flip-flop circuits 11p to 11s and outputs the signals SBKc and SBKd to the selectors 30c and 30d, respectively.

  The enable signal generation circuit 29D outputs an enable control signal ENa to the selectors 30a and 30b, and outputs an enable control signal ENb to the selectors 30c and 30d.

  The selector 30a selects one of the output signal of the flip-flop circuit 11a and the interface signal IF_Da output from the low-speed circuit region 20D according to the enable control signal ENa, and outputs it to the flip-flop circuit 11a. The selector 30b selects one of the output signal of the flip-flop circuit 11b and the interface signal IF_Db output from the low-speed circuit region 20D according to the enable control signal ENa, and outputs it to the flip-flop circuit 11b.

  The selector 30c selects either the output signal of the flip-flop circuit 11c or the signal SBKc output from the combinational circuit 21c according to the enable control signal ENb, and outputs it to the flip-flop circuit 11c. The selector 30d selects either the output signal of the flip-flop circuit 11d or the signal SBKd output from the combinational circuit 21d according to the enable control signal ENb, and outputs it to the flip-flop circuit 11d.

  Specifically, the selectors 30a and 30b respectively select the interface signals IF_Da and IF_Db when the enable control signal ENa is at the H level, and the output signals of the flip-flop circuits 11a and 11b when the enable control signal ENa is at the L level. Select each.

  The selectors 30c and 30d select the signals SBKc and SBKd output from the combinational circuit 21c while the enable control signal ENb is at the H level, respectively, and the flip-flop circuits 11c and 11d when the enable control signal ENb is at the L level. Output signals are selected respectively. Note that the enable control signal ENa and the enable control signal ENb may be the same signal.

  The low-speed circuit region 20D includes flip-flop circuits 11e to 11h and a combinational circuit 22. Each of the flip-flop circuits 11e to 11h operates in synchronization with the rising edge of the low-speed clock signal CLKS. The flip-flop circuits 11e and 11f temporarily hold the interface signals IF_D1 and IF_D2 from the high-speed circuit region 10B, respectively, and then output them to the combinational circuit 22. The flip-flop circuits 11 g and 11 h temporarily hold the output signal from the combinational circuit 22 and then output it to the combinational circuit 22. The combinational circuit 22 receives the output signals of the flip-flop circuits 11e to 11h and outputs interface signals IF_Da and IF_Db to the selectors 30a and 30b in the high-speed circuit region 10D, respectively.

  In the fourth embodiment, as in the first embodiment, the enable control signal ENa changes after a delay of a fixed time after the high-speed clock signal CLKF changes. Thus, the selectors 30a and 30b select the output signals of the flip-flop circuits 11a and 11b, respectively, at the time when the rising edges of the low-speed clock signal CLKS and the high-speed clock signal CLKF are synchronized.

  As described above, according to the fourth embodiment, the output signals of the flip-flop circuits 11a and 11b are re-looped at the time when the rising edges of the low-speed clock signal CLKS and the high-speed clock signal CLKF are synchronized. At the rising time, that is, when the flip-flop circuits 11e and 11f output the input signal to the combinational circuit 22, the flip-flop circuits 11a and 11b do not capture the interface signals IF_Da and IF_Db. For this reason, the interface signals IF_Da and IF_Db can be transferred between different clocks at a timing with a sufficient hold margin.

  Further, in the fourth embodiment, as in the second embodiment, the enable control signal ENb changes after a delay of a predetermined time after the high-speed clock signal CLKF changes. Thereby, the selectors 30c and 30d respectively select the output signals of the flip-flop circuits 11c and 11d at the time when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized.

  As a result, the flip-flop circuits 11c and 11d re-loop their output signals at the time when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized, and the interface signals IF_D1 and IF_D2 are changing. Absent. As a result, the flip-flop circuits 11e and 11f can sample the interface signals IF_D1 and IF_D2 with a sufficient hold margin at the time when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized.

  The signals SBKc and SBKd that are not selected by the selectors 30c and 30d at the time when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized are selected by the selectors 30c and 30d at the next rising time of the high-speed clock signal CLKF. The flip-flop circuits 11c and 11d output the interface signals IF_D1 and IF_D2 through the combinational circuit 21b. The interface signals IF_D1 and IF_D2 are sampled by the flip-flop circuits 11e and 11f at the next rising edge of the low-speed clock signal CLKS.

  As described above, according to the fourth embodiment, the output signals of the flip-flop circuits 11c and 11d are re-looped at the time when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized. The flip-flop circuits 11c and 11d do not change the interface signals IF_D1 and IF_D2 at the rising time, that is, the timing when the flip-flop circuits 11e and 11f output the input signal to the combinational circuit 22. For this reason, the interface signals IF_D1 and IF_D2 can be transferred between different clocks at a timing with a margin in the hold margin.

[Embodiment 5]
FIG. 10 is a schematic configuration diagram showing a schematic configuration of a semiconductor integrated circuit 1E according to the fifth embodiment of the present invention.

  Referring to FIG. 10, semiconductor integrated circuit 1E according to the fifth embodiment includes a low-speed circuit region 20E that operates in synchronization with the rising edge of low-speed clock signal CLKS, and a high-speed circuit that operates in synchronization with the rising edge of high-speed clock signal CLKF. Region 10E.

  The semiconductor integrated circuit 1E according to the fifth embodiment is different from the semiconductor integrated circuit according to the first embodiment in that the enable signal generating circuit 29A is removed and the low-speed clock signal CLKS via the delay element 40 is used as the enable control signal EN. Different from 1A. The delay with respect to the low-speed clock signal CLKS can be given, for example, by increasing the wiring length. At this time, the delay element 40 need not be used. Therefore, the semiconductor integrated circuit 1E can reduce the circuit area as compared with the semiconductor integrated circuit 1A of the first embodiment.

  FIG. 11 is a timing chart showing a circuit operation of semiconductor integrated circuit 1E according to the fifth embodiment of the present invention.

  Referring to FIG. 11, low-speed clock signal CLKS falls at times t1, t3, t5, and t7, and rises at times t2, t4, t6, and t8. The rising speed of the high-speed clock signal CLKF is synchronized with the low-speed clock signal CLKS, and the number of rising times per unit time is eight times that of the low-speed clock signal CLKS. The interface signal IF_E changes in response to the rising edge of the low-speed clock signal CLKS.

  In the fifth embodiment, the selector 30e in FIG. 10 selects the output signal of the flip-flop circuit 11e at times t2, t4, t6, and t8 at which the rising edges of the low-speed clock signal CLKS and the high-speed clock signal CLKF are synchronized. Yes. As described above, in the fifth embodiment, since a signal obtained by delaying the low-speed clock signal CLKS is used as the enable control signal EN, the time t2, when the rising edges of the low-speed clock signal CLKS and the high-speed clock signal CLKF are synchronized. At t4, t6, and t8, the enable control signal EN is always at the L level.

  As a result, the flip-flop circuit 11e of FIG. 10 re-loops its own output signal at times t2, t4, t6, and t8. As a result, the flip-flop circuit 11e does not sample the interface signal IF_E at times t2, t4, t6, and t8.

  The interface signal IF_E that is not selected by the selector 30e of FIG. 10 at the times t2, t4, t6, and t8 is selected by the selector 30e of FIG. 10 at the next rising time of the high-speed clock signal CLKF, and is output to the flip-flop circuit 11e. The Therefore, the flip-flop circuit 11e can receive the interface signal IF_E at a timing with a sufficient hold margin.

  As described above, according to the fifth embodiment, by removing the enable signal generating circuit 29A and using a signal obtained by delaying the low-speed clock signal CLKS as the enable control signal EN, in addition to the effects of the first embodiment. Thus, the circuit area of the semiconductor integrated circuit 1E can be reduced.

[Embodiment 6]
FIG. 12 is a schematic configuration diagram showing a schematic configuration of a semiconductor integrated circuit 1F according to the sixth embodiment of the present invention.

  Referring to FIG. 12, semiconductor integrated circuit 1F according to the sixth embodiment includes a high-speed circuit region 10F that operates in synchronization with the rising edge of high-speed clock signal CLKF, and a low-speed circuit that operates in synchronization with the rising edge of low-speed clock signal CLKS. And a region 20F.

  The semiconductor integrated circuit 1F of the sixth embodiment is different from the semiconductor integrated circuit of the second embodiment in that the enable signal generating circuit 29B is removed and the low-speed clock signal CLKS via the delay element 40 is used as the enable control signal EN. Different from 1B. The delay with respect to the low-speed clock signal CLKS can be given, for example, by increasing the wiring length. At this time, the delay element 40 need not be used. Therefore, the semiconductor integrated circuit 1F can reduce the circuit area compared to the semiconductor integrated circuit 1B of the second embodiment.

  FIG. 13 is a timing chart showing a circuit operation of semiconductor integrated circuit 1F according to the sixth embodiment of the present invention.

  Referring to FIG. 13, low-speed clock signal CLKS falls at times t1, t4, t7, and t10, and rises at times t2, t5, t8, and t11. The rising speed of the high-speed clock signal CLKF is synchronized with the low-speed clock signal CLKS, and the number of rising times per unit time is eight times that of the low-speed clock signal CLKS. When the signal SBK changes at times t2, t5, t8, and t11, the interface signal IF_F changes at times t3, t6, t9, and t12.

  In the sixth embodiment, the selector 30a in FIG. 12 selects the output signal of the flip-flop circuit 11a at times t2, t5, t8, and t11 when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized. Yes. As described above, in the sixth embodiment, since a signal obtained by delaying the clock signal CLKS is used as the enable control signal EN, the times t2 and t5 when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized. , T8, t11, the enable control signal EN is always at the L level.

  Accordingly, the flip-flop circuit 11a of FIG. 12 reloops its own output signal at times t2, t5, t8, and t11, and the interface signal IF_F does not change. As a result, the flip-flop circuit 11e can sample the interface signal IF_F with a sufficient hold margin at times t2, t5, t8, and t11 when the rising edges of the high-speed clock signal CLKF and the low-speed clock signal CLKS are synchronized.

  The signal SBK that has not been selected by the selector 30a of FIG. 12 at the times t2, t5, t8, t11 is selected by the selector 30a of FIG. 12 at the next rising time of the high-speed clock signal CLKF, and the interface signal IF_F Is output as The interface signal IF_F is sampled by the flip-flop circuit 11e at the next rising edge of the low-speed clock signal CLKS.

  As described above, according to the sixth embodiment, by removing the enable signal generation circuit 29B and using a signal obtained by delaying the low-speed clock signal CLKS as the enable control signal EN, in addition to the effects of the second embodiment. Thus, the circuit area of the semiconductor integrated circuit 1F can be reduced.

  In the above embodiment, for the purpose of explaining the contents of the invention, the number of flip-flop circuits is limited, and further, sampling is performed at the rising edge, that is, it operates in synchronization with the rising edge of the clock signal. . However, the present invention is not limited to these, and for example, sampling may be performed at the falling edge of the flip-flop circuit.

  Further, in the above embodiment, for the purpose of explaining the contents of the invention, the description has been given by limiting the number of circuit areas to two with two clock signals. However, the present invention is not limited to these.

  In the above embodiments, the number of rising times per unit time of the high-speed clock signal CLKF has been described as eight times that of the low-speed clock signal CLKS for the convenience of describing the contents of the invention. However, the present invention is not limited to these, and the present invention is applicable as long as the frequency of the high-speed clock signal CLKF is higher than the frequency of the low-speed clock signal CLKS.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic configuration diagram showing a schematic configuration of a semiconductor integrated circuit 1A according to a first embodiment of the present invention. 3 is a circuit diagram showing an enable signal generation circuit 29 which is an example of a specific circuit configuration of the enable signal generation circuit 29A. FIG. FIG. 5 is a timing chart showing a circuit operation of an enable signal generation circuit 29 which is an example of a specific circuit configuration of the enable signal generation circuit 29A. FIG. 3 is a timing diagram showing a circuit operation of the semiconductor integrated circuit 1A according to the first embodiment of the present invention. FIG. 10 is a timing diagram showing waveforms of enable signals ENA1 to ENA6, which are other examples of waveforms of the enable control signal ENa. FIG. 5 is a schematic configuration diagram showing a schematic configuration of a semiconductor integrated circuit 1B according to a second embodiment of the present invention. FIG. 12 is a timing diagram showing a circuit operation of the semiconductor integrated circuit 1B according to the second embodiment of the present invention. FIG. 10 is a schematic configuration diagram showing a schematic configuration of a semiconductor integrated circuit 1C according to a third embodiment of the present invention. FIG. 10 is a schematic configuration diagram showing a schematic configuration of a semiconductor integrated circuit 1D according to a fourth embodiment of the present invention. FIG. 10 is a schematic configuration diagram showing a schematic configuration of a semiconductor integrated circuit 1E according to a fifth embodiment of the present invention. FIG. 10 is a timing diagram showing a circuit operation of a semiconductor integrated circuit 1E according to a fifth embodiment of the present invention. It is a schematic block diagram showing a schematic configuration of a semiconductor integrated circuit 1F according to a sixth embodiment of the present invention. It is a timing diagram which showed the circuit operation | movement of the semiconductor integrated circuit 1F by Embodiment 6 of this invention.

Explanation of symbols

  10A-10F high-speed circuit area, 11a-11h, 11p-11s flip-flop circuit, 20A-20F low-speed circuit area, 29, 29A-29D enable signal generation circuit, 21, 21a-21c, 22 combinational circuit, 30a-30e selector, 291 3-bit counter, 292 3-bit flip-flop circuit, 293 incrementer, 294 NAND circuit.

Claims (7)

A first circuit region that outputs an interface signal from the combinational circuit, and includes a combinational circuit and a first flip-flop circuit that outputs an input signal to the combinational circuit in synchronization with a first clock signal;
A second circuit region that operates in synchronization with a second clock signal having a frequency different from that of the first clock signal and receives the interface signal;
The second circuit region is
A flip-flop circuit operating in synchronization with the second clock signal;
At the timing when the first flip-flop circuit outputs the input signal to the combinational circuit, the output signal of the second flip-flop circuit is selected and output to the second flip-flop circuit, which is different from the timing. And a selection circuit that selects the interface signal and outputs the selected signal to the second flip-flop circuit. An enable signal generating circuit that outputs an enable control signal that changes after a predetermined time delay from the change of the second clock signal;
2. The selection circuit according to claim 1, wherein the selection circuit selects one of an output signal of the second flip-flop circuit and the interface signal in accordance with the enable control signal, and outputs the selected signal to the second flip-flop circuit. The semiconductor integrated circuit as described.   The selection circuit selects either the output signal of the second flip-flop circuit or the interface signal in accordance with a signal obtained by delaying the first clock signal, and the second flip-flop circuit The semiconductor integrated circuit according to claim 1, wherein A second circuit region that operates in synchronization with the second clock signal and outputs a second interface signal;
A first flip-flop that operates in synchronization with a first clock signal having a frequency different from that of the second clock signal and outputs the second interface signal to the first combination circuit; And a first circuit region including a circuit,
The second circuit region is
A second combinational circuit;
A second flip-flop circuit that operates in synchronization with the second clock signal;
At the timing when the first flip-flop circuit outputs the second interface signal to the first combinational circuit, the output signal of the second flip-flop circuit is selected and output to the second flip-flop circuit. And a selection circuit that selects an output signal of the second combinational circuit at a timing different from the timing and outputs the output signal to the second flip-flop circuit,
The semiconductor integrated circuit, wherein the second interface signal is output from the second flip-flop circuit. An enable signal generating circuit that outputs an enable control signal that changes after a predetermined time delay from the change of the second clock signal;
5. The selection circuit according to claim 4, wherein the selection circuit selects one of an output signal of the second flip-flop circuit and the interface signal in accordance with the enable control signal, and outputs the selected signal to the second flip-flop circuit. The semiconductor integrated circuit as described.   The selection circuit selects either the output signal of the second flip-flop circuit or the interface signal in accordance with a signal obtained by delaying the first clock signal, and the second flip-flop circuit 5. The semiconductor integrated circuit according to claim 4, wherein A second circuit region that operates in synchronization with the second clock signal and outputs a second interface signal;
A first flip-flop circuit that operates in synchronization with a first clock signal having a frequency different from that of the second clock signal and outputs the second interface signal to the first combination circuit. And a first circuit region for outputting a first interface signal,
The second circuit region is
A second combinational circuit;
A second flip-flop circuit that operates in synchronization with the second clock signal;
At the timing when the first flip-flop circuit outputs the second interface signal to the first combinational circuit, the output signal of the second flip-flop circuit is selected and output to the second flip-flop circuit. And a selection circuit that selects at least one of the output signal of the second combinational circuit and the first interface signal at a timing different from the timing and outputs the selected signal to the second flip-flop circuit,
The semiconductor integrated circuit, wherein the second interface signal is output from the second combinational circuit.

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