JP2006244460A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2006244460A5 JP2006244460A5 JP2005366569A JP2005366569A JP2006244460A5 JP 2006244460 A5 JP2006244460 A5 JP 2006244460A5 JP 2005366569 A JP2005366569 A JP 2005366569A JP 2005366569 A JP2005366569 A JP 2005366569A JP 2006244460 A5 JP2006244460 A5 JP 2006244460A5
- Authority
- JP
- Japan
- Prior art keywords
- data
- processor
- data storage
- cache memory
- storage means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013500 data storage Methods 0.000 claims 16
- 238000001514 detection method Methods 0.000 claims 5
- 238000007726 management method Methods 0.000 claims 4
- 238000013523 data management Methods 0.000 claims 2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005366569A JP4904802B2 (ja) | 2005-02-01 | 2005-12-20 | キャッシュメモリ及びプロセッサ |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005024976 | 2005-02-01 | ||
| JP2005024976 | 2005-02-01 | ||
| JP2005366569A JP4904802B2 (ja) | 2005-02-01 | 2005-12-20 | キャッシュメモリ及びプロセッサ |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006244460A JP2006244460A (ja) | 2006-09-14 |
| JP2006244460A5 true JP2006244460A5 (enExample) | 2009-01-15 |
| JP4904802B2 JP4904802B2 (ja) | 2012-03-28 |
Family
ID=37050782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005366569A Expired - Fee Related JP4904802B2 (ja) | 2005-02-01 | 2005-12-20 | キャッシュメモリ及びプロセッサ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4904802B2 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201015321A (en) * | 2008-09-25 | 2010-04-16 | Panasonic Corp | Buffer memory device, memory system and data trnsfer method |
| JP5417879B2 (ja) * | 2009-02-17 | 2014-02-19 | 富士通セミコンダクター株式会社 | キャッシュ装置 |
| WO2012077400A1 (ja) | 2010-12-09 | 2012-06-14 | インターナショナル・ビジネス・マシーンズ・コーポレーション | マルチコアシステム、及びそのコアのデータ読み出し方法 |
| JP2020532795A (ja) * | 2017-08-31 | 2020-11-12 | レール ビジョン リミテッドRail Vision Ltd | 複数計算における高スループットのためのシステムおよび方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02224041A (ja) * | 1988-11-17 | 1990-09-06 | Nec Ic Microcomput Syst Ltd | キャッシュメモリ制御回路 |
| JPH02204834A (ja) * | 1989-02-03 | 1990-08-14 | Nec Corp | オペランド差換え方式 |
| JP3609656B2 (ja) * | 1999-07-30 | 2005-01-12 | 株式会社日立製作所 | コンピュータシステム |
| US6901450B1 (en) * | 2000-09-22 | 2005-05-31 | Hitachi, Ltd. | Multiprocessor machine and cache control method for providing higher priority to shared cache that is accessed by multiprocessors |
-
2005
- 2005-12-20 JP JP2005366569A patent/JP4904802B2/ja not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10019369B2 (en) | Apparatuses and methods for pre-fetching and write-back for a segmented cache memory | |
| US8949544B2 (en) | Bypassing a cache when handling memory requests | |
| US10019368B2 (en) | Placement policy for memory hierarchies | |
| US9223710B2 (en) | Read-write partitioning of cache memory | |
| US8473689B2 (en) | Predictive sequential prefetching for data caching | |
| CN106909515B (zh) | 面向混合主存的多核共享末级缓存管理方法及装置 | |
| US20100138607A1 (en) | Increasing concurrency and controlling replication in a multi-core cache hierarchy | |
| US7552288B2 (en) | Selectively inclusive cache architecture | |
| US9672161B2 (en) | Configuring a cache management mechanism based on future accesses in a cache | |
| US10185619B2 (en) | Handling of error prone cache line slots of memory side cache of multi-level system memory | |
| US20110173400A1 (en) | Buffer memory device, memory system, and data transfer method | |
| CN101772759A (zh) | 高速缓存锁定设备及其方法 | |
| US10261901B2 (en) | Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory | |
| JP2011519461A5 (enExample) | ||
| JP2009524137A5 (enExample) | ||
| JP2005158040A5 (enExample) | ||
| CN104798032B (zh) | 用于缩短缓存的清空时间的设备和方法 | |
| US10120806B2 (en) | Multi-level system memory with near memory scrubbing based on predicted far memory idle time | |
| CN103076992A (zh) | 一种内存数据缓冲方法及装置 | |
| JP2001222468A5 (enExample) | ||
| WO2015125971A1 (ja) | キャッシュ存在情報を有するtlb | |
| CN110674054B (zh) | 存储系统及其操作方法 | |
| US8473685B2 (en) | Cache memory device, processor, and control method for cache memory device to reduce power unnecessarily consumed by cache memory | |
| JP2006244460A5 (enExample) | ||
| CA2601779A1 (en) | Global modified indicator to reduce power consumption on cache miss |