JP2006244460A5 - - Google Patents
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- JP2006244460A5 JP2006244460A5 JP2005366569A JP2005366569A JP2006244460A5 JP 2006244460 A5 JP2006244460 A5 JP 2006244460A5 JP 2005366569 A JP2005366569 A JP 2005366569A JP 2005366569 A JP2005366569 A JP 2005366569A JP 2006244460 A5 JP2006244460 A5 JP 2006244460A5
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- processor
- data storage
- cache memory
- storage means
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- 238000001514 detection method Methods 0.000 claims 5
Claims (8)
複数のプロセッサによってキャッシュされたデータが保存されるデータ保存手段と、
前記データ保存手段に記憶されているデータのアドレスを、前記データ保存手段が記憶しているデータ全体について一括して管理するアドレス管理手段と、
前記プロセッサによって供給を要求されたデータのアドレスを前記アドレス管理手段によって管理されているアドレスと照合し、供給を要求されたデータが前記データ保存手段から読出し可能であるか否か検出するヒット検出手段と、
前記ヒット検出手段によってデータが読出し可能であることが検出された場合、検出されたデータを前記プロセッサに供給するデータ供給手段と、
を備えることを特徴とするキャッシュメモリ。 A cache memory that caches at least a part of data read from a storage device by a plurality of processors and supplies at least a part of the cached data to the processor;
Data storage means for storing data cached by a plurality of processors;
Address management means for collectively managing addresses of data stored in the data storage means for the entire data stored in the data storage means ;
Hit detection means for comparing the address of data requested to be supplied by the processor with an address managed by the address management means and detecting whether the data requested to be supplied is readable from the data storage means When,
Data supply means for supplying the detected data to the processor when the hit detection means detects that the data is readable;
A cache memory comprising:
前記キャッシュメモリは、
複数のプロセッサによってキャッシュされたデータが保存されるデータ保存手段と、
前記データ保存手段に記憶されているデータのアドレスを、前記データ保存手段が記憶しているデータ全体について一括して管理するアドレス管理手段と、
前記プロセッサによって供給を要求されたデータのアドレスを前記アドレス管理手段によって管理されているアドレスと照合し、供給を要求されたデータが前記データ保存手段から読出し可能か否かを検出するヒット検出手段と、
前記ヒット検出手段によってデータが読出し可能であることが検出された場合、検出されたデータを前記プロセッサに供給するデータ供給手段と、を備えることを特徴とするプロセッサ。 A processor comprising a cache memory that caches at least a part of data read from a storage device by a plurality of processors and supplies at least a part of the cached data to the processor,
The cache memory is
Data storage means for storing data cached by a plurality of processors;
Address management means for collectively managing addresses of data stored in the data storage means for the entire data stored in the data storage means ;
Hit detection means for collating the address of the data requested to be supplied by the processor with the address managed by the address management means, and detecting whether the data requested to be supplied can be read from the data storage means; ,
And a data supply means for supplying the detected data to the processor when the hit detection means detects that the data can be read out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005366569A JP4904802B2 (en) | 2005-02-01 | 2005-12-20 | Cache memory and processor |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005024976 | 2005-02-01 | ||
| JP2005024976 | 2005-02-01 | ||
| JP2005366569A JP4904802B2 (en) | 2005-02-01 | 2005-12-20 | Cache memory and processor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006244460A JP2006244460A (en) | 2006-09-14 |
| JP2006244460A5 true JP2006244460A5 (en) | 2009-01-15 |
| JP4904802B2 JP4904802B2 (en) | 2012-03-28 |
Family
ID=37050782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005366569A Expired - Fee Related JP4904802B2 (en) | 2005-02-01 | 2005-12-20 | Cache memory and processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4904802B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201015321A (en) * | 2008-09-25 | 2010-04-16 | Panasonic Corp | Buffer memory device, memory system and data trnsfer method |
| JP5417879B2 (en) | 2009-02-17 | 2014-02-19 | 富士通セミコンダクター株式会社 | Cache device |
| DE112011104329T5 (en) | 2010-12-09 | 2013-09-26 | International Business Machines Corporation | Multi-core system and method for reading the core data |
| WO2019043710A1 (en) * | 2017-08-31 | 2019-03-07 | Rail Vision Ltd | System and method for high throughput in multiple computations |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02224041A (en) * | 1988-11-17 | 1990-09-06 | Nec Ic Microcomput Syst Ltd | Cache memory control circuit |
| JPH02204834A (en) * | 1989-02-03 | 1990-08-14 | Nec Corp | Operand replacing system |
| JP3609656B2 (en) * | 1999-07-30 | 2005-01-12 | 株式会社日立製作所 | Computer system |
| US6901450B1 (en) * | 2000-09-22 | 2005-05-31 | Hitachi, Ltd. | Multiprocessor machine and cache control method for providing higher priority to shared cache that is accessed by multiprocessors |
-
2005
- 2005-12-20 JP JP2005366569A patent/JP4904802B2/en not_active Expired - Fee Related
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