JP2001222468A5 - - Google Patents

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Publication number
JP2001222468A5
JP2001222468A5 JP2001010369A JP2001010369A JP2001222468A5 JP 2001222468 A5 JP2001222468 A5 JP 2001222468A5 JP 2001010369 A JP2001010369 A JP 2001010369A JP 2001010369 A JP2001010369 A JP 2001010369A JP 2001222468 A5 JP2001222468 A5 JP 2001222468A5
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JP
Japan
Prior art keywords
cache
store
load
miss
memory
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Application number
JP2001010369A
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English (en)
Japanese (ja)
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JP2001222468A (ja
JP3862959B2 (ja
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Priority claimed from US09/502,550 external-priority patent/US6360298B1/en
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Publication of JP2001222468A publication Critical patent/JP2001222468A/ja
Publication of JP2001222468A5 publication Critical patent/JP2001222468A5/ja
Application granted granted Critical
Publication of JP3862959B2 publication Critical patent/JP3862959B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2001010369A 2000-02-10 2001-01-18 マイクロプロセッサのロード／ストア命令制御回路、およびロード／ストア命令制御方法 Expired - Fee Related JP3862959B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US502550 2000-02-10
US09/502,550 US6360298B1 (en) 2000-02-10 2000-02-10 Load/store instruction control circuit of microprocessor and load/store instruction control method

Publications (3)

Publication Number Publication Date
JP2001222468A JP2001222468A (ja) 2001-08-17
JP2001222468A5 true JP2001222468A5 (enExample) 2005-01-13
JP3862959B2 JP3862959B2 (ja) 2006-12-27

Family

ID=23998317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001010369A Expired - Fee Related JP3862959B2 (ja) 2000-02-10 2001-01-18 マイクロプロセッサのロード／ストア命令制御回路、およびロード／ストア命令制御方法

Country Status (2)

Country Link
US (1) US6360298B1 (enExample)
JP (1) JP3862959B2 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7065632B1 (en) * 2000-04-07 2006-06-20 Ip First Llc Method and apparatus for speculatively forwarding storehit data in a hierarchical manner
US6675287B1 (en) * 2000-04-07 2004-01-06 Ip-First, Llc Method and apparatus for store forwarding using a response buffer data path in a write-allocate-configurable microprocessor
EP1304620A1 (en) * 2001-10-17 2003-04-23 Texas Instruments Incorporated Cache with selective write allocation
GB2391337B (en) 2002-04-26 2005-06-15 Motorola Inc Instruction cache and method for reducing memory conflicts
US6961821B2 (en) * 2002-10-16 2005-11-01 International Business Machines Corporation Reconfigurable cache controller for nonuniform memory access computer systems
US7240183B2 (en) * 2005-05-31 2007-07-03 Kabushiki Kaisha Toshiba System and method for detecting instruction dependencies in multiple phases
US20070022277A1 (en) * 2005-07-20 2007-01-25 Kenji Iwamura Method and system for an enhanced microprocessor
EP1988465B1 (en) * 2006-02-24 2011-11-23 Fujitsu Limited Processor, and cache control method
US7631149B2 (en) 2006-07-24 2009-12-08 Kabushiki Kaisha Toshiba Systems and methods for providing fixed-latency data access in a memory system having multi-level caches
JP5321782B2 (ja) * 2008-01-22 2013-10-23 日本電気株式会社 二重化システム及びメモリコピー方法
JP4888839B2 (ja) * 2008-10-03 2012-02-29 日本電気株式会社 キャッシュメモリを備えるベクトル計算機システム、及びその動作方法
GB2469299B (en) * 2009-04-07 2011-02-16 Imagination Tech Ltd Ensuring consistency between a data cache and a main memory
US8996812B2 (en) * 2009-06-19 2015-03-31 International Business Machines Corporation Write-back coherency data cache for resolving read/write conflicts
JP2011008731A (ja) * 2009-06-29 2011-01-13 Fujitsu Ltd キャッシュメモリ装置、半導体集積回路および演算処理装置
JP5482197B2 (ja) * 2009-12-25 2014-04-23 富士通株式会社 演算処理装置、情報処理装置及びキャッシュメモリ制御方法
GB2551351B (en) 2016-06-14 2019-05-08 Imagination Tech Ltd Executing memory requests out of order
US11803470B2 (en) * 2020-09-25 2023-10-31 Advanced Micro Devices, Inc. Multi-level cache coherency protocol for cache line evictions

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5671444A (en) * 1994-02-28 1997-09-23 Intel Corporaiton Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers
US5680572A (en) * 1994-02-28 1997-10-21 Intel Corporation Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers
JPH10154394A (ja) * 1996-11-21 1998-06-09 Toshiba Corp メモリ装置

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