JP3862959B2 - マイクロプロセッサのロード／ストア命令制御回路、およびロード／ストア命令制御方法 - Google Patents

マイクロプロセッサのロード／ストア命令制御回路、およびロード／ストア命令制御方法 Download PDF

Info

Publication number
JP3862959B2
JP3862959B2 JP2001010369A JP2001010369A JP3862959B2 JP 3862959 B2 JP3862959 B2 JP 3862959B2 JP 2001010369 A JP2001010369 A JP 2001010369A JP 2001010369 A JP2001010369 A JP 2001010369A JP 3862959 B2 JP3862959 B2 JP 3862959B2
Authority
JP
Japan
Prior art keywords
cache
store
load
instruction
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001010369A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001222468A (ja
JP2001222468A5 (enExample
Inventor
建 樹 小山内
ジョニー・シト
カイル・ツカモト
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of JP2001222468A publication Critical patent/JP2001222468A/ja
Publication of JP2001222468A5 publication Critical patent/JP2001222468A5/ja
Application granted granted Critical
Publication of JP3862959B2 publication Critical patent/JP3862959B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
JP2001010369A 2000-02-10 2001-01-18 マイクロプロセッサのロード／ストア命令制御回路、およびロード／ストア命令制御方法 Expired - Fee Related JP3862959B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US502550 2000-02-10
US09/502,550 US6360298B1 (en) 2000-02-10 2000-02-10 Load/store instruction control circuit of microprocessor and load/store instruction control method

Publications (3)

Publication Number Publication Date
JP2001222468A JP2001222468A (ja) 2001-08-17
JP2001222468A5 JP2001222468A5 (enExample) 2005-01-13
JP3862959B2 true JP3862959B2 (ja) 2006-12-27

Family

ID=23998317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001010369A Expired - Fee Related JP3862959B2 (ja) 2000-02-10 2001-01-18 マイクロプロセッサのロード／ストア命令制御回路、およびロード／ストア命令制御方法

Country Status (2)

Country Link
US (1) US6360298B1 (enExample)
JP (1) JP3862959B2 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7065632B1 (en) * 2000-04-07 2006-06-20 Ip First Llc Method and apparatus for speculatively forwarding storehit data in a hierarchical manner
US6675287B1 (en) * 2000-04-07 2004-01-06 Ip-First, Llc Method and apparatus for store forwarding using a response buffer data path in a write-allocate-configurable microprocessor
EP1304620A1 (en) * 2001-10-17 2003-04-23 Texas Instruments Incorporated Cache with selective write allocation
GB2391337B (en) 2002-04-26 2005-06-15 Motorola Inc Instruction cache and method for reducing memory conflicts
US6961821B2 (en) * 2002-10-16 2005-11-01 International Business Machines Corporation Reconfigurable cache controller for nonuniform memory access computer systems
US7240183B2 (en) * 2005-05-31 2007-07-03 Kabushiki Kaisha Toshiba System and method for detecting instruction dependencies in multiple phases
US20070022277A1 (en) * 2005-07-20 2007-01-25 Kenji Iwamura Method and system for an enhanced microprocessor
EP1988465B1 (en) * 2006-02-24 2011-11-23 Fujitsu Limited Processor, and cache control method
US7631149B2 (en) 2006-07-24 2009-12-08 Kabushiki Kaisha Toshiba Systems and methods for providing fixed-latency data access in a memory system having multi-level caches
JP5321782B2 (ja) * 2008-01-22 2013-10-23 日本電気株式会社 二重化システム及びメモリコピー方法
JP4888839B2 (ja) * 2008-10-03 2012-02-29 日本電気株式会社 キャッシュメモリを備えるベクトル計算機システム、及びその動作方法
GB2469299B (en) * 2009-04-07 2011-02-16 Imagination Tech Ltd Ensuring consistency between a data cache and a main memory
US8996812B2 (en) * 2009-06-19 2015-03-31 International Business Machines Corporation Write-back coherency data cache for resolving read/write conflicts
JP2011008731A (ja) * 2009-06-29 2011-01-13 Fujitsu Ltd キャッシュメモリ装置、半導体集積回路および演算処理装置
JP5482197B2 (ja) * 2009-12-25 2014-04-23 富士通株式会社 演算処理装置、情報処理装置及びキャッシュメモリ制御方法
GB2551351B (en) 2016-06-14 2019-05-08 Imagination Tech Ltd Executing memory requests out of order
US11803470B2 (en) * 2020-09-25 2023-10-31 Advanced Micro Devices, Inc. Multi-level cache coherency protocol for cache line evictions

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5671444A (en) * 1994-02-28 1997-09-23 Intel Corporaiton Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers
US5680572A (en) * 1994-02-28 1997-10-21 Intel Corporation Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers
JPH10154394A (ja) * 1996-11-21 1998-06-09 Toshiba Corp メモリ装置

Also Published As

Publication number Publication date
US6360298B1 (en) 2002-03-19
JP2001222468A (ja) 2001-08-17

Similar Documents

Publication Publication Date Title
JP2566701B2 (ja) 共有キャッシュ内のデータ・ユニットに対する所有権の変更制御装置
JP3862959B2 (ja) マイクロプロセッサのロード／ストア命令制御回路、およびロード／ストア命令制御方法
US20210173931A1 (en) Speculative side-channel attack mitigations
JP3741146B2 (ja) コンピュータシステム
JP4162825B2 (ja) マイクロプロセッサ
US5793941A (en) On-chip primary cache testing circuit and test method
US5930832A (en) Apparatus to guarantee TLB inclusion for store operations
US20020156962A1 (en) Microprocessor having improved memory management unit and cache memory
JP2004503870A (ja) 変換索引バッファのフラッシュフィルタ
JP3825974B2 (ja) トランスレーション・ルックアサイド・バッファ回路
WO2013084314A1 (ja) 演算処理装置及び演算処理装置の制御方法
US7707361B2 (en) Data cache block zero implementation
US6467027B1 (en) Method and system for an INUSE field resource management scheme
EP0374370B1 (en) Method for storing into non-exclusive cache lines in multiprocessor systems
US6389527B1 (en) Microprocessor allowing simultaneous instruction execution and DMA transfer
Knowles et al. The MU6-G virtual address cache
JPWO2013084314A1 (ja) 演算処理装置及び演算処理装置の制御方法

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040216

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040216

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060621

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060707

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060905

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060915

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060927

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101006

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees