JP4904802B2 - キャッシュメモリ及びプロセッサ - Google Patents

キャッシュメモリ及びプロセッサ Download PDF

Info

Publication number
JP4904802B2
JP4904802B2 JP2005366569A JP2005366569A JP4904802B2 JP 4904802 B2 JP4904802 B2 JP 4904802B2 JP 2005366569 A JP2005366569 A JP 2005366569A JP 2005366569 A JP2005366569 A JP 2005366569A JP 4904802 B2 JP4904802 B2 JP 4904802B2
Authority
JP
Japan
Prior art keywords
data
processor
memory
read
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005366569A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006244460A5 (enExample
JP2006244460A (ja
Inventor
晃成 轟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2005366569A priority Critical patent/JP4904802B2/ja
Publication of JP2006244460A publication Critical patent/JP2006244460A/ja
Publication of JP2006244460A5 publication Critical patent/JP2006244460A5/ja
Application granted granted Critical
Publication of JP4904802B2 publication Critical patent/JP4904802B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
JP2005366569A 2005-02-01 2005-12-20 キャッシュメモリ及びプロセッサ Expired - Fee Related JP4904802B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005366569A JP4904802B2 (ja) 2005-02-01 2005-12-20 キャッシュメモリ及びプロセッサ

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005024976 2005-02-01
JP2005024976 2005-02-01
JP2005366569A JP4904802B2 (ja) 2005-02-01 2005-12-20 キャッシュメモリ及びプロセッサ

Publications (3)

Publication Number Publication Date
JP2006244460A JP2006244460A (ja) 2006-09-14
JP2006244460A5 JP2006244460A5 (enExample) 2009-01-15
JP4904802B2 true JP4904802B2 (ja) 2012-03-28

Family

ID=37050782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005366569A Expired - Fee Related JP4904802B2 (ja) 2005-02-01 2005-12-20 キャッシュメモリ及びプロセッサ

Country Status (1)

Country Link
JP (1) JP4904802B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201015321A (en) * 2008-09-25 2010-04-16 Panasonic Corp Buffer memory device, memory system and data trnsfer method
JP5417879B2 (ja) * 2009-02-17 2014-02-19 富士通セミコンダクター株式会社 キャッシュ装置
WO2012077400A1 (ja) 2010-12-09 2012-06-14 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチコアシステム、及びそのコアのデータ読み出し方法
JP2020532795A (ja) * 2017-08-31 2020-11-12 レール ビジョン リミテッドＲａｉｌ Ｖｉｓｉｏｎ Ｌｔｄ 複数計算における高スループットのためのシステムおよび方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02224041A (ja) * 1988-11-17 1990-09-06 Nec Ic Microcomput Syst Ltd キャッシュメモリ制御回路
JPH02204834A (ja) * 1989-02-03 1990-08-14 Nec Corp オペランド差換え方式
JP3609656B2 (ja) * 1999-07-30 2005-01-12 株式会社日立製作所 コンピュータシステム
US6901450B1 (en) * 2000-09-22 2005-05-31 Hitachi, Ltd. Multiprocessor machine and cache control method for providing higher priority to shared cache that is accessed by multiprocessors

Also Published As

Publication number Publication date
JP2006244460A (ja) 2006-09-14

Similar Documents

Publication Publication Date Title
US5359723A (en) Cache memory hierarchy having a large write through first level that allocates for CPU read misses only and a small write back second level that allocates for CPU write misses only
EP1388065B1 (en) Method and system for speculatively invalidating lines in a cache
US6834327B2 (en) Multilevel cache system having unified cache tag memory
US7925840B2 (en) Data processing apparatus and method for managing snoop operations
US6272602B1 (en) Multiprocessing system employing pending tags to maintain cache coherence
US8185695B2 (en) Snoop filtering mechanism
US20110173393A1 (en) Cache memory, memory system, and control method therefor
US8700863B2 (en) Computer system having a cache memory and control method of the same
US20110173400A1 (en) Buffer memory device, memory system, and data transfer method
JP2008117388A (ja) キャッシュ及びキャッシュバイパス機能法
CN113853590A (zh) 伪随机路选择
GB2468007A (en) Data processing apparatus and method dependent on streaming preload instruction.
JP2006085292A (ja) 演算処理装置
US8332592B2 (en) Graphics processor with snoop filter
US11036639B2 (en) Cache apparatus and method that facilitates a reduction in energy consumption through use of first and second data arrays
US20070239940A1 (en) Adaptive prefetching
US8473686B2 (en) Computer cache system with stratified replacement
CN101228512B (zh) 用于管理高速缓冲存储器存取的方法和设备
US20110167223A1 (en) Buffer memory device, memory system, and data reading method
JP5157424B2 (ja) キャッシュメモリシステム及びキャッシュメモリの制御方法
US6446168B1 (en) Method and apparatus for dynamically switching a cache between direct-mapped and 4-way set associativity
US6477622B1 (en) Simplified writeback handling
JP4904802B2 (ja) キャッシュメモリ及びプロセッサ
US7779205B2 (en) Coherent caching of local memory data
US7543112B1 (en) Efficient on-chip instruction and data caching for chip multiprocessors

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081120

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20081120

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110809

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111007

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20111213

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20111226

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150120

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees