JP2006239284A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a fraudulence such as an attempt to intentionally make the figures of a game machine hit a winning pattern. <P>SOLUTION: A pachinko game machine PM has a random number generation part 750 and a random number generation circuit B31' and a random number acquisition means B33 which acquires one couted value as the first random number value out of random number values generated with the random number generation part 750 and one counted value as the second random number value out of random number values generated with the random number generation circuit B31' to generate the special game advantageous for players from the result of the acquisition by the random number acquisition means B33. The random number acquisition means B33 compares a criterion value which is computed from the first and second random number values for judging whether the special game should be generated or not with a preset winning random number value for generating the special game. When both the values coincide, the occurrence of the jackpot is decided. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a gaming machine, and more particularly to a gaming machine that generates a random number for determining a special game or the like by hardware configured by a random number clock generation circuit or the like, or software controlled by a CPU.

  In a gaming machine having a random number generation means for generating a random number for special game determination as described above, the random number generation means counts the random number value based on the reference clock of the CPU responsible for controlling the game by executing the program. -Updating is performed at a predetermined cycle. In a pachinko machine, which is a typical example of such a gaming machine, this count value is triggered by the winning of a starting prize provided on the gaming board or the falling of a game ball at a symbol operating gate. It is acquired as a random number for determining whether or not to generate a special game that gives a profit to the player, and a winning determination is made. And the stop symbol in the symbol display apparatus on a game board is determined by this winning result. A random number obtained by such a method is referred to as a software random number.

On the other hand, as an alternative to the method of acquiring a random number for winning determination or the like by executing the program as described above, as described in Patent Document 1 and Patent Document 2, for example, an oscillation of a crystal resonator or an oscillator A CPU that controls a game by causing a random number value of a predetermined number of digits to be periodically counted by a clock count circuit based on a clock generated at a predetermined cycle by a random number clock generation circuit constituted by a child, and a count value storage circuit The count value stored in is acquired and read, and the read count value is used as a random number for determining whether or not to generate a special game. By using a random number generator that counts random values by hardware as described above, the software load is reduced as compared with the case where software controlled by the CPU executes a program and counts random values. Random numbers can be generated and updated at high speed according to the clock generation cycle of the clock generation circuit.
JP 2003-190483 A JP 7-124296 A

  By the way, in recent years, a special device is installed on a control board that is equipped with a CPU and controls the operation of the gaming machine in an integrated manner, and the random number update timing is discriminated by such a device, which is advantageous for the player. There has been a problem of fraud such as intentionally drawing a random number that generates a game. Such fraudulent acts are inevitably made longer by the addition interval of the counter due to software processing, and because the update cycle of the counter is relatively long, it is easy to determine the timing of random number update. It was particularly easy to do in the method of obtaining random numbers for use.

  In view of the problems as described above, the present invention provides a gaming machine provided with a random number generating device with improved security by preventing unauthorized acts from the outside when acquiring random numbers. Objective.

  In order to solve the above-mentioned problem, the gaming machine according to the present invention includes a first random number generation unit (for example, a random number generation unit 750 in the embodiment) and a second random number generation unit (for example, counting random number values every required time). For example, the random number generation circuit B31 and the reference clock generation circuit 731 in the embodiment and the first random number generated by the first random number generation means are used as the first random number (for example, the hardware in the embodiment). Random number acquisition means (for example, a software random number in the embodiment) for acquiring one count value from among the random number values generated by the second random number generation means. And a random number acquisition means B33) in the embodiment, which generates a special game that gives a profit to the player based on the result obtained by the random number acquisition means. (For example, the pachinko machine PM in the embodiment), in which the random number acquisition unit compares the determination value calculated based on the first random number value and the second random number value with a preset random number value Then, when the determination value matches the winning random number value, it is determined that the winning is made and a special game is generated.

  Further, in the gaming machine configured as described above, the first random number generation means is generated by the random number clock generation means (for example, the random number clock generation circuit B51 in the embodiment) that generates a clock at a predetermined frequency and the random number clock generation means. Random number counting means (for example, clock count circuits B81 to B84 in the embodiment) that counts the random number value based on the clock, and the first random number value counted by the random number counting means by the random number acquisition means The second random number generation unit counts the second random number value based on a reference clock of a CPU (for example, the CPU 732 in the embodiment) that controls the operation of the random number acquisition unit. It is preferable to configure.

  Further, in the gaming machine configured as described above, the second random number value may be acquired from the random number values counted by the program control of the CPU.

  In the gaming machine configured as described above, the ratio at which the determination value matches the random number value may be constant regardless of the first random number value.

  In addition, the gaming machine having the above configuration includes notification signal output means (for example, the control unit 740 in the embodiment) that outputs a predetermined notification signal indicating an abnormal operation when the abnormal operation of the random number clock generation means occurs. It may be configured.

  According to the gaming machine of the present invention, by calculating each random value generated by a plurality of random number generation means as a determination value for determining whether or not to generate a special game that gives a profit to the player The obtained calculation value is used. For this reason, the process of generating the determination value can be made more complicated by calculation compared with the case where the random number generated by one type of random number generation means is determined as it is as the determination value. It is possible to prevent an illegal act such as intentionally drawing a random number that generates a special game advantageous to the player. In addition to the method of obtaining hardware random numbers that are relatively difficult to perform fraud, further complicated generation of judgment values as in the present invention provides a gaming machine with improved security problems. Is possible.

  In the present invention, one of a plurality of random number generation means includes a CPU, and it is possible to generate a so-called software random number by a method of counting random numbers by CPU program control based on a CPU reference clock. It is. In such a case, even if an abnormal operation occurs in hardware (first random number generation means) including random number clock generation means that constitutes the other of the plurality of random number generation means, Only a software random number generated by a CPU or the like constituting one of a plurality of random number generation means is acquired as a determination value, and a special game is generated regardless of a hardware failure related to random number generation unless the CPU itself fails. It is possible to draw such random numbers. In this way, even if a failure occurs in which the CPU repeatedly reads the same count value generated in the first random number generator, the parts such as the random number generator that caused the abnormal operation are replaced. In the meantime, it is possible to continue the game by using only the software random number as the judgment value.

  Furthermore, if the ratio at which the judgment value matches the random number value is set to be constant regardless of hardware failure, even if the same count value is repeatedly acquired due to hardware failure, Since the probability of a jackpot game that gives a profit to the player does not fluctuate, it is possible to continue the game without being directly affected by this abnormality without judging any hardware abnormality and taking any action It is.

  In addition, when an abnormality occurs in the hardware, if it is configured to notify the outside so that it can be recognized, only a software random number can be obtained by prompting the game hall to replace the hardware immediately after the abnormality has occurred. It is possible to minimize the decrease in security associated with continuing the game with the determination value.

  Hereinafter, a preferred embodiment of a gaming machine according to the present invention will be described in detail with reference to FIGS. 1 is an external front view of a pachinko machine described as an example of the above gaming machine, FIG. 2 is a rear view showing the internal structure of the pachinko machine, and FIG. 3 is an outline of a control system provided in the pachinko machine. FIG. 4 is a block diagram showing a part related to the control of the pachinko machine provided in the pachinko machine and a part related to the generation of random numbers. FIG. 5 shows a random number generation part and its surroundings in the pachinko machine. 6 is an enlarged view of the clock monitoring circuit in the random number generator, FIGS. 7 and 8 are timing charts showing signals generated in the random number generator, and FIG. 9 is provided in the pachinko machine. It is the block diagram showing the micro control unit (MCU) etc. of the control system currently used. FIG. 10 to FIG. 15 are diagrams showing procedures for obtaining and using special game determination random numbers.

  Here, first, a schematic configuration of a pachinko machine PM described as an example of the gaming machine will be described with reference to FIG. 1 and FIG. As shown in FIG. 1, this pachinko machine PM is configured to have a rectangular frame size and a rectangular frame size adapted to the opening front of the outer frame 1 that forms a vertically fixed holding frame. The front frame 2 is attached by hinge members 3a and 3b disposed on the upper left and right sides of the front side so that it can be opened and closed laterally and attached and detached. It is held in the engaged closed state.

  On the front side of the front frame 2, a glass door 5 that can be seen through the game board 20 through a transparent plate material such as a polycarbonate plate or a glass plate that has a square shape matched to the front area of the front frame 2 and is attached to the center portion; The upper ball tray 6 that aligns the game balls stored in the ball tray and guides them one by one to the hitting ball launching device 9 is assembled so as to be openable and closable and detachable sideways by a hinge mechanism built in the left edge. Usually, it is held in a closed state covering the front surface of the front frame 2 using the locking device 4 and a lock mechanism (not shown). A prize ball payout exit 6b for paying out a prize ball is provided on the upper left side of the contact plate 6a which is a horizontal rectangle in the upper ball tray 6 and can be opened and closed with respect to the front frame 2. On the lower left side of the upper ball tray 6, there is provided a sound emitting unit 6c that emits sound from a speaker (not shown) that generates sound effects according to the game development status. A lower ball tray 7 for storing game balls is provided at the lower part of the front frame 2, and an operation handle 8 for performing a game ball launching operation is attached along with the lower ball tray 7.

  The game board 20 includes a decorative board (also referred to as a veneer) 21 having a predetermined design cell attached to a surface of a laminated plywood having a thickness of about 19 mm cut into a predetermined shape. On the front side of the decorative plate 21, a belt-like outer rail 23a and an inner rail 23b are fixed in an arc shape, and a game area PA is defined on the inner side surrounded by the guide rails 23a and 23b. In the game area PA, the first start winning tool 24a, the second start winning tool 24b, the general winning tool 25, the winning tool such as an attacker having the large winning tool 26, and a predetermined pattern according to the progress of the game are displayed. A symbol display device 28 or the like that is displayed so as to be visible to the player is attached, and game balls that have fallen without winning the prize-winning tools 24a, 24b, 25, and 26 are placed on the back side of the game board 20 at the lower end of the game area PA. An outlet 27 for discharging is provided. Further, four special symbol holding lamps 90, 90, 90, 90 are provided above the symbol display device 28.

  The symbol display device 28 is located substantially in the center of the game board 20 and displays a “special symbol” composed of a combination of three-digit symbols on a liquid crystal screen. Of these special symbols, three digits are displayed. In any case, a combination of the same type of pattern is referred to as a “hit pattern”.

  In addition to a predetermined number of prize balls (for example, five balls) being paid out to the player from the prize ball outlet 6b of the upper ball tray 6 when there is a prize for the first start prize 24a or the second start prize 24b. The symbol display device 28 is activated, and the variation of the symbol is started. As a result of this change, when the special symbol to be stopped and displayed is a winning symbol, a “hit game” advantageous to the player is generated.

  In this jackpot game, the big prize 26 which is normally closed is opened. When there is a prize for the big prize tool 26, a predetermined number (for example, 15 balls) of prize balls are paid out to the player from the prize ball payout exit 6b. The big winning tool 26 is temporarily closed when either a predetermined time (for example, 30 seconds) has elapsed after being opened or when a predetermined number (for example, 10 balls) has been won. If there is a prize in a V zone (not shown) provided inside the big prize tool 26 while the big prize tool 26 is opened, the big prize tool 26 is once closed and then opened again. It is supposed to be. As a result, the opening of the big prize tool 26 can be continued up to 16 times. In addition, when the big winning tool 26 has been opened 16 times, or when there is no winning in the V zone during the opening of the big winning tool 26, the big hit game is ended.

  When the hit ball wins the first start winning tool 24a or the second start winning tool 24b during the variable display on the symbol display device 28, the special symbol holding lamps 90, 90, 90, 90 are a maximum of four. It is supposed to light up to pieces. That is, the subsequent operation of the symbol display device 28 is guaranteed by the number of times corresponding to the number of the special symbol holding lamps 90, 90, 90, 90 being lit.

  In the first start winning tool 24a, a hitting ball flow path for detecting the hit of the first starting winning tool 24a is detected and a detection signal is output to start the symbol display on the symbol display device 28. A first start winning sensor 51 is provided. The first start winning sensor 51 uses a magnetic sensor and outputs a first start signal that takes two states of a high signal and a low signal as a detection signal. The first start signal is output as a high signal when a hit ball is not detected, and is output as a low signal only while a hit ball is detected. An optical or mechanical sensor may be used as the first start winning sensor 51.

  In addition, the hitting flow path in the second start winning tool 24b is detected by the same magnetic sensor as the first start winning sensor 51 to detect the hit of the hit ball on the second starting winning tool 24b, and a detection signal is output. A second start winning sensor 52 is provided for starting the display of symbol variation on the display device 28. The second start winning sensor 52 outputs a second start signal that takes two states of a high signal and a low signal as a detection signal. The second start signal outputs a high signal when no hit ball is detected, but outputs a low signal only while the hit ball is passing. An optical or mechanical sensor may be used as the second start winning sensor 52.

As shown in FIG. 2, the lower part of the rear surface of the front frame 2 has a hitting ball launching device 9 that launches a game ball toward the outer rail 23 a, and an operation of the hitting ball launching device 9 in response to the turning operation of the operation handle 8. A launcher control board 200 to be controlled is attached. Further, behind the upper ball tray 6 is formed an auxiliary mechanism portion called a game assisting board whose front side is normally covered with the upper ball tray 6 that is normally held closed, and a ball hitting device on the front side. Foul ball collection that discharges the game ball launched by 9 toward the outer rail 23a and the foul ball returned to the ball launcher 9 side without reaching the game area PA to the lower ball tray 7 A route member, a speaker (not shown) and the like for generating sound effects according to the game development status are attached.

  A back set board 30 is attached to the back of the front frame 2. This back set board 30 has a rectangular shape somewhat smaller than the inner size of the outer frame 1, and is configured based on a base frame body 31 integrally formed with a window 31w penetrating the front and back at the center. . Back set board swinging hinge members 32 and 33 are fixed to the side edge of the base frame body 31 at a predetermined interval in the vertical direction. The upper and lower back set panel swinging hinge members 32 and 33 are fixed to the front frame 2. The back set board 30 is mounted on the back side of the front frame 2 so that it can be opened and closed laterally and detachable by engaging with the upper and lower fixed hinge members 12 and 13 and swinging or disengaging. The closing lever 34 is used to close and hold the back of the front frame 2.

  The back set board 30 is provided with a prize ball path for paying out prize balls so as to surround the window 31w. That is, on the back side of the base frame 31, a tank member 35 for storing and supplying game balls, an alignment rod member 36 for aligning and flowing down game balls supplied from the tank member 35, and an alignment rod member 36 are supplied. A prize ball standby passage 37 for receiving and waiting for a predetermined number of game balls, a ball payout device 38 for paying out the game balls waiting in the prize ball standby passage 37 based on predetermined winning conditions, etc. A prize ball path such as a prize ball payout path 39 for guiding the game balls paid out from the payout device 38 to the upper and lower ball trays 6 and 7 is provided. In addition, on the front side of the base frame 31, an out ball and a safe ball that are positioned below the window 31 w and discharged to the back side of the game board 20, and a punch that is discharged from the middle of the winning ball path by the ball punching mechanism. A collecting path (not shown) for collecting balls and the like is formed, and a ball discharging path (not shown) is formed on the back surface side of the base frame 31 to discharge the game balls gathered connected to the collecting path to a collection bucket on the gaming facility side. ing.

  In each part of the back surface of the back set board 30, a main board 700 that comprehensively controls the operation of the pachinko machine PM, a ball payout board 300 that controls the operation of the ball payout device 38 based on a command signal from the main board 700, A lamp / voice control board 400 that controls the operation of effect lighting and sound effects, a power supply board 500 that supplies power to these control boards and various electronic devices, and a gaming machine management device (management computer) installed in the game hall On the other hand, a circuit board such as an external terminal board 600 as an external connection device that outputs various game information is detachably attached, and each circuit board and electronic equipment are connected by a wire harness (not shown) to constitute a pachinko machine PM. Is done. Also, below the ball payout board 300, an error display device 61 (error LED) is used to notify when an abnormal operation or the like occurs in these circuit boards including the main board 700 on a screen using a light emitting diode. Is provided.

  The pachinko machine PM is used in a game with the glass door 5, the upper ball tray 6, the back set board 30 and the like closed, and the front frame 2 closed and locked to the outer frame 1. The game is started by storing the game balls in the upper ball tray 6 and rotating the operation handle 8, and the game balls stored in the upper ball tray 6 are sent one by one to the hitting ball launcher 9 and are operated. The pachinko game is developed by being struck into the game area PA with the strength corresponding to the rotation operation angle.

  Next, an outline of a control system for controlling the pachinko machine PM will be described with reference to FIG. As shown in FIG. 3, the control system includes a main board 700, a first start prize sensor 51, a second start prize sensor 52, a symbol display device 28, an external terminal board 600, and an error display device 61. These are electrically connected by a cable or the like.

  The main board 700 has a storage unit formed by a semiconductor memory or the like in which a system program for managing the entire operation of the pachinko machine PM and a game execution program are stored in advance, and a main control unit 730 for executing these programs. And a random number generator 750 for generating so-called hardware random numbers (65536 random numbers from 0 to 65535) for determining a special game regardless of the control of the main board 700. In the present invention, the random number is not only a value that is randomly generated in a mathematical sense, but even if the generation is regular, the acquisition timing is random, so that the random number is substantially a random number. It also means a functional value. In the present invention, the random value counted by the clock count circuits B81 to B84, which will be described later, and stored in the first and second count value storage circuits B91 and B92 will be specifically referred to as “count value”.

  The control unit 740 in the main control unit 730 includes a ROM 733 and a RAM 734, and a control program to be executed by the main control unit 730 and data necessary for the control process are described in the ROM 733. The main control unit 730 is provided with a reference clock generation circuit 731. The reference clock generation circuit 731 is a circuit that generates a reference clock that forms an operation reference of the CPU 732 (see FIG. 4) that plays a central role in controlling the pachinko machine PM. The reference clock generation circuit 731 uses a crystal oscillator, a crystal resonator, or the like at predetermined intervals. The pulse (clock signal) is generated. In addition, the reference clock may be obtained by appropriately dividing the pulse by the frequency divider 735.

  The main control unit 730 is generated by a random number generation circuit B31 that generates a so-called software random number and a hardware random number generated by the random number generation unit 750 and a random number generation circuit B31 in accordance with a random number generation program B37 stored in the ROM 733. It has a determination value calculation circuit B32 that executes a predetermined calculation process based on software random numbers, and a random number acquisition means B33 including a hit determination means B34.

  When the main board 700 detects a low signal from the first start prize sensor 51 or the second start prize sensor 52, the random number acquisition means B33 causes the random number generation unit 750 to sequentially generate one of 65536 random numbers. The count value (first random number value) and the software random number (second random number value) generated by the random number generation circuit B31 are acquired, and the stop symbol is determined in the symbol display device 28.

  In the hit determination table B36 on the ROM 733, data is recorded so that a unique determination result of “Random number” or “Lose random number” for one random number value is determined for the entire range of random values. ing. That is, the total random number value always belongs to one of the hit random number and the lost random number, and does not belong to either or both of them. Here, the winning random number means a random value that causes the symbol display device 28 to stop-display a predetermined winning symbol combination that generates a jackpot game.

  The hit determination means B34 compares the reference value calculated based on the first random number value and the second random number value acquired by the random number acquisition means B33 with the data stored in the determination table B36. Then, a determination result corresponding to the determination value, that is, whether the determination value is a hit random number or a lost random number is acquired.

  In the symbol data table B35 on the ROM 733, symbol data for determining a stop symbol in the symbol display device 28 is recorded. Each symbol data is given an address number, and one symbol data is specified from one address number. When the determination value calculated by the determination value calculation circuit B32 is determined to be a hit by the hit determination means B34, the symbol data in which the winning symbol is stored is selected appropriately. The Then, a predetermined symbol selected based on the control signal from the main board 700 is displayed on the symbol display device 28.

  As will be described later, the random number generation unit 750 includes a clock monitoring circuit B95 that detects whether or not the random number clock generation circuit B51 is operating normally.

  The main board 700 is electrically connected to the outside of the pachinko machine PM via the external terminal board 600, and various game information output from the main board 700 is transmitted to a management computer outside the pachinko machine PM. It can be made to. The game information includes a notification signal output from the control unit 740 that detects some abnormality in the main board 700 and the like, and can notify the management computer of the abnormality of the pachinko machine PM. The hall can immediately recognize this abnormality.

  Further, the error display device 61 is connected to the main board 700 via a wiring cable, and the error display device 61 is notified by a notification signal output from the control unit 740 that detects an abnormality in each circuit board such as the main board 700. Can be turned on.

  Here, with reference to FIG. 4 and FIG. 5, the structure of the part which concerns on generation | occurrence | production of the random number in the pachinko machine PM, acquisition of this, and abnormality detection of a random number generation means is demonstrated. The input circuit unit B40 is a part to which input information from outside the main substrate 700, a random number generated by a random number generation unit 750 provided in the main substrate 700, an abnormal signal from a clock monitoring circuit B95 described later, and the like are input. It is composed of a buffer IC or the like. Specifically, the input circuit unit B40 receives from the first start winning sensor 51 or the second start winning sensor 52 that is output in accordance with the winning of the hit ball to the first start winning tool 24a or the second start winning tool 24b. And the upper and lower 8 bits of the random number generated by the random number generator 750 are input. Further, an output signal from the random number clock generation means B51 is input to the input circuit section B40, and whether or not this output signal is a pulse signal due to normal operation of the random number clock generation means B51 is input via the input circuit section B40. Is monitored by the control unit 740.

  The output circuit unit B45 outputs a read signal for reading control signals to the electrical components (lamps, speakers, etc.) outside the main substrate 700 and random numbers generated by the random number generator 750 provided in the main substrate 700. This part is composed of an IC such as a buffer. Specifically, from the output circuit unit B45, when the main board 700 determines that the first starting prize-winning tool 24a has won a prize, the first read signal that triggers reading of the count value corresponding to the prize, When the main board 700 determines that the second starting prize-winning tool 24b has won a prize, a second read signal that triggers reading of the count value corresponding to the prize is output. Further, when an abnormal operation is detected in the random number clock generation means B51 or the clock count circuits B81 to B84, a notification signal is output to the outside of the pachinko machine PM through the external terminal board 600. In addition, a notification signal is output toward the error display device 61 to display a predetermined error.

  The first start signal from the first start winning sensor 51 is input to the 1A terminal of the IC 14 of the input circuit unit B40. On the other hand, the second start signal from the second start winning sensor 52 is input to the 2A terminal of the IC 14 of the input circuit unit B40. Further, the 3A terminal of the IC 14 is connected to the collector of the transistor TR1 constituting the clock monitoring circuit B95, and when a voltage is applied to the base of the transistor TR1, a collector current flows from the input circuit part B40 side. Yes.

  The random number generator 750 generates a count value used as a random number. Specifically, the random number generator 750 includes a random number clock generation circuit B51, a random number clock inversion circuit B61, first and second latch signal output circuits B71, B72, The first to fourth clock count circuits B81, B82, B83, and B84, first and second count value storage circuits B91 and B92, and a clock monitoring circuit B95 are included.

  The random number clock generation circuit B51 (OSC1) is for generating a clock for counting random numbers and includes a clock output unit (OUT) for outputting the generated clock. The random number clock generation circuit B51 is constituted by, for example, a crystal oscillator that generates a 7.15909 MHz clock.

  The random number clock inversion circuit B61 (IC18) inverts the clock output from the random number clock generation circuit B51, and uses the inverted clock as an inverted clock, which will be described later, a first latch signal output circuit B71 (IC16) and a second latch signal output circuit. The data is output to B72 (IC17). Specifically, in the IC 18, a signal obtained by inverting the signal output from the 1Q terminal is output as an inverted signal from the 1Q inverting terminal that is the inverted clock output unit, and the rising edge of the clock is the falling edge of the inverted clock. The falling edge of the clock corresponds to the rising edge of the inverted clock. The random number clock inverting circuit B61 may be configured using an IC such as a NOT gate.

  Each of the first to fourth clock count circuits B81, B82, B83, and B84 has a random number clock input unit (CK) for inputting a clock and a count output unit (QA to QD) for outputting the counted random number value. ing. As shown in FIG. 5, the first to fourth clock count circuits B81, B82, B83, and B84 are constituted by a circuit in which four 4-bit increment counters (from IC1 to IC4) are cascade-connected to generate a random number clock. This is a circuit for adding at the rising edge of the clock generated by the circuit B51 and outputting the addition result.

  In response to the input of the clock from the random number clock generation circuit B51, first, the first clock count circuit B81 (IC1) counts a value for four digits (for example, “0001” and “0011”). When "1111" is counted and the count of four digits ends, a carry signal is output from the CO terminal of IC1 to the ENT terminal of the second clock count circuit B82 (IC2) each time. In order for the second clock count circuit B82 to start counting, it is necessary to input the carry signal from the first clock count circuit B81. That is, in the IC2, the next four digits are started only after the carry signal and the clock (input to the CK terminal) from the random number clock generation circuit B51 are input simultaneously.

  Similarly, when a value for four digits (for example, “0001” or “0011”) is counted up to “1111” in IC2, a carry signal is sent from the CO terminal of IC2 to the third clock count circuit B83 each time. It is output to the ENT terminal of (IC3). In order for the third clock count circuit B83 to start counting, it is necessary to input the carry signal from the second clock count circuit B82. That is, in IC3, the count of the value for the next four digits is started only when the carry signal and the clock from the random number clock generation circuit B51 (input to the CK terminal) are input simultaneously.

  Similarly, when a value for four digits (for example, “0001” or “0011”) is counted up to “1111” in IC3, the carry signal is counted from the CO terminal of IC3 to the fourth clock each time. It is output to the ENT terminal of the circuit B84 (IC4). In order for the fourth clock count circuit B84 to start counting, it is necessary to input the carry signal from the third clock count circuit B83. That is, in the IC4, the count of the next four digits is started only when the carry signal and the clock (input to the CK terminal) from the random number clock generation circuit B51 are input simultaneously.

  As described above, 16-bit binary numbers are generated by the clock count circuits B81 to B84. That is, among the 16-digit binary numbers, the first clock count circuit B81 (IC1) is the lowest four digits, the second clock count circuit B82 (IC2) is the upper four digits, and the third clock count circuit B83 (IC3 ) Is further responsible for the upper 4 digits and the fourth clock count circuit B84 (IC4).

  The counts added by the four clock count circuits B81 to B84 are sent to the first count value storage circuit B91 and the second count value storage circuit B92 via the respective count output sections (QA, QB, QC and QD terminals). Each is output and stored. In this embodiment, an addition type increment counter is used as the clock count circuit. However, in other embodiments, a subtraction type decrement counter may be used. In this embodiment, a 16-bit random number (4 bits × 4) is generated. However, in other embodiments, the number of bits is not limited to 16 bits and may be changed as appropriate. .

  The latch signal output circuits B71 and B72 include a first latch signal output circuit B71 (IC16) related to acquisition of a random number associated with winning in the first starting prize-winning tool 24a and a random number associated with winning in the second starting prize-winning tool 24b. The second latch signal output circuit B72 (IC17) related to acquisition is divided.

  The inverted clock from the random number clock inverter circuit B61 (IC18) is input to the first latch signal output circuit B71 (IC16) via the first inverted clock input section (1CK). At the same time, the first start signal from the first start winning sensor 51 is input to the first start signal input unit (1D) via the buffer (IC13). When the first start signal (low signal) is input via the first start signal input section (1D), the first latch signal output circuit B71 uses the rising edge of this signal as the first inverted clock input. The first count value storage circuit B91 (IC5 and IC6) passes through the first latch signal output unit (1Q) as the first latch signal after being delayed in synchronization with the rising edge of the inverted clock input from the unit (1CK). Output to.

  On the other hand, the second latch signal output circuit B72 (IC17) receives the inverted clock from the random number clock inverter circuit B61 via the second inverted clock input section (2CK). At the same time, the second start signal from the second start winning sensor 52 is input to the second start signal input unit (2D). When the second start signal (low signal) is input through the second start signal input unit (2D), the second latch signal output circuit B72 sends the rising edge of this signal from the inverted clock input unit. After being delayed so as to be synchronized with the rising edge of the input inverted clock, the second latch signal is output to the second count value storage circuit B92 (IC7 and IC8) via the second latch signal output unit (2Q).

  The first and second start signals are also input to the main control unit 730 via the input circuit unit B40 and the like, as will be described later, and may be used as a timing for starting a program executed for random number acquisition. It is supposed to be used.

  The count value storage circuits B91 and B92 are a first count value storage circuit B91 that temporarily stores a random number derived from winning in the first start winning tool 24a and a random number derived from winning in the second starting winning tool 24b. Is divided into a second count value storage circuit B92 for temporarily storing.

  The first count value storage circuit B91 uses the count value counted by the clock count circuits B81 to B84 based on the first latch signal from the first latch signal output circuit B71 (the first count from the first start winning sensor 51). When a start signal is received and a latch signal is output from the first latch signal output circuit B71, it is stored. On the other hand, the second count value storage circuit B92 calculates the count value counted by the clock count circuits B81 to B84 based on the second latch signal from the second latch signal output circuit B72 (from the second start winning sensor 52). The second start signal is received and stored (when a latch signal is output from the second latch signal output circuit B72).

  As shown in FIG. 5, the first count value storage circuit B91 includes a register unit (IC5 and IC6) including two 8-bit ICs and a buffer unit (IC9 and IC10) including two 8-bit ICs. The Similarly, the second count value storage circuit B92 includes a register unit (IC7 and IC8) including two 8-bit ICs and a buffer unit (IC11 and IC12) including two 8-bit ICs.

  Of the register portion of the first count value storage circuit B91, the IC5 receives the 4-digit count value from the first clock count circuit B81 (IC1) through the D1 terminal to the D4 terminal, The 4-digit count value from the clock count circuit B82 (IC2) is input via the D5 terminal to the D8 terminal. That is, the D1 terminal to D8 terminal of the IC5 function as a count input unit, and the lower 8 digits of the 16-bit binary count value derived from the first start prize 24a are input to the IC5 through them. .

  Of the register section of the first count value storage circuit B91, the IC6 receives the 4-digit count value from the third clock count circuit B83 (IC3) via the D1 terminal to the D4 terminal, A 4-digit count value from the clock count circuit B84 (IC4) is input from the D5 terminal to the D8 terminal. That is, the D1 terminal to D8 terminal of the IC 6 function as a count input unit, and the upper 8 digits of the 16-bit binary count value derived from the first start prize 24a are input to the IC 6 through these. .

  Of the register unit of the second count value storage circuit B92, the IC7 receives the 4-digit count value from the first clock count circuit B81 (IC1) through the D1 terminal to the D4 terminal, The 4-digit count value from the clock count circuit B82 (IC2) is input via the D5 terminal to the D8 terminal. That is, the D1 terminal to D8 terminal of the IC 7 function as a count input unit, and the lower 8 digits of the 16-bit binary count value derived from the second start prize 24b are input to the IC 7 through these terminals. .

  Of the register unit of the second count value storage circuit B92, the IC8 receives the 4-digit count value from the third clock count circuit B83 (IC3) through the D1 terminal to the D4 terminal, A 4-digit count value from the clock count circuit B84 (IC4) is input from the D5 terminal to the D8 terminal. That is, the D8 terminal to D8 terminal of the IC8 function as a count input unit, and the IC8 receives the upper 8 digits of the 16-bit binary count value derived from the second start prize 24b through them. The

  The first latch signal from the first latch signal output circuit B71 is input to the CLOCK terminal in the register unit (IC5 and IC6) of the first count value storage circuit B91. That is, these CLOCK terminals function as a first latch signal input section, and at the time of the rising edge when the first latch signal input from the first latch signal input section becomes a high signal, the clock count circuit B81. The count value input from .about.B84 is stored in the register unit.

  The second latch signal from the second latch signal output circuit B72 is input to the CLOCK terminal in the register unit (IC7 and IC8) of the second count value storage circuit B92. That is, these CLOCK terminals function as a second latch signal input unit, and at the time of the rising edge when the second latch signal input from the second latch signal input unit becomes a high signal, the clock count circuit B81. The count value input from .about.B84 is stored in the register unit.

  The G1 terminal in the buffer unit (IC9 and IC10) of the first count value storage circuit B91 corresponds to a read signal output from the output circuit unit B45 of the main control unit 730 based on a program executed for random number acquisition. Thus, one count value consisting of 16 digits stored in the first count value storage circuit B91 is output to the CPU 732. That is, at the time of the falling edge when the read signal input from the read signal input unit becomes a low signal, the random numbers stored in the register units (IC5 and IC6) are transferred to the CPU via the Y1 terminal to Y8 terminal, respectively. Output to the data bus.

  Of the random numbers output from the first count value storage circuit B91, those passing through the IC 9 are input to the CPU 732 and handled as the lower 8 digits of the 16-digit random numbers. On the other hand, among the random numbers output from the first count value storage circuit B91, those passing through the IC 10 are input to the CPU 732 and handled as the upper 8 digits of the 16-digit random numbers.

  The terminal G1 in the buffer unit (IC11 and IC12) of the second count value storage circuit B92 stores a second count value according to the read signal output from the output circuit unit B45 of the main control unit 730 based on the program. One count value consisting of 16 digits stored in the circuit B 92 is output to the CPU 732. That is, at the time of the falling edge when the read signal input from the read signal input unit becomes a low signal, the random numbers stored in the register units (IC7 and IC8) are transferred to the CPU data via the Y1 terminal to Y8 terminal, respectively. Output to the bus.

  Among the random numbers output from the second count value storage circuit B92, those passing through the IC 11 are input to the CPU 732 and handled as the lower 8 digits of the 16-digit random numbers. On the other hand, among the random numbers output from the second count value storage circuit B92, those passing through the IC 12 are input to the CPU 732 and handled as the upper 8 digits of the 16-digit random numbers.

  Next, the clock monitoring circuit B95 will be described together with FIG. 6 which is an enlarged view of the clock monitoring circuit B95 in the random number generation unit 750. The clock monitoring circuit B95 for monitoring the abnormal operation of the clock generation circuit B51 is composed of capacitors C3 and C4, diodes D1 and D2, a transistor TR1 and the like. The capacitor C3 is connected to the 1Q terminal of the random number clock inverting circuit B61 as a coupling capacitor, and the collector side of the transistor TR1 is connected to the 3A terminal of the input circuit unit B40. The collector side of the transistor TR1 is also connected to the positive side of the power supply E via a resistor R6. The diode D1 and the resistor R5 are both for keeping the cathode side of the diode D1 always at a positive potential.

  The capacitor C3 has a role of passing only a periodic pulse signal (clock signal) from the clock generation circuit B51 from which the DC component is cut to the clock monitoring circuit B95 side. For this reason, when the clock generation circuit B51 stops operating (pulse oscillation is stopped) due to some trouble occurring in the clock generation circuit B51, the clock generation circuit B51 outputs a constant high signal or low signal that does not change with time. Thus, the output signal from the clock generation circuit B51 is not transmitted to the clock monitoring circuit B95 side. That is, the input signal input to the clock monitoring circuit B95 changes according to the operation status of the clock generation circuit B51.

  The smoothing circuit unit B96 configured in the clock monitoring circuit B95 smoothes the pulse signal input from the clock generation circuit B51 and always outputs a voltage higher than a predetermined value (for example, 5 V or more). It comprises a diode D2 connected as an anode, a smoothing capacitor C4 connected between the cathode of the diode D2 and the ground, and the like. The diode D2 is for always holding the cathode side at a positive potential. Further, the smoothing capacitor C4 smoothes the pulse signal that has passed through the diode D2 and always outputs a voltage higher than a predetermined value, and this output voltage is applied to the transistor TR1 as a base voltage.

  The collector side of the transistor TR1 is connected to the 3A terminal of the (IC14) of the input circuit unit B40. As described above, the branch line branched from the circuit to the input circuit unit B40 is connected to the power supply E via the resistor R6. Connected to the positive side. In a state where the clock generation circuit B51 normally oscillates a pulse signal, an output voltage equal to or higher than a predetermined level smoothed by the smoothing circuit portion B96 is applied to the transistor TR1 as a base voltage. When a predetermined base voltage (for example, 5 V) is applied to the transistor TR1, a collector current Ic flows from the collector side to the emitter side (ground side) of the transistor TR1.

  The collector current Ic is supplied from the power supply E. When a current flows from the power supply E to the collector side of the transistor TR1, the current Ia does not flow toward the input circuit section B40 (IC14). At this time, an abnormal signal indicating an abnormal operation of the clock generation circuit B51 is not output from the IC 14 to the CPU 732.

  On the other hand, when an abnormal operation occurs in the clock generation circuit B51 and the oscillation of the pulse signal is stopped, no voltage is applied from the smoothing circuit portion B96 to the transistor TR1, and the base voltage is zero (below a predetermined value). Collector current Ic does not flow. For this reason, the current Ia flows from the power source E toward the input circuit section B40 (IC14). When the current Ia flows through the IC 14, an abnormal signal is output from the IC 14 toward the CPU 732.

  As described above, the transistor TR1 serves as a switch that allows the current supplied from the power source E to flow to the clock monitoring circuit B95 side or cuts off this current, and to the IC14 side by stopping the oscillation of the pulse signal. When the current Ia flows, an abnormal signal is output from the IC 14 to the CPU 732 via the CPU data bus, so that the control unit 740 can determine the abnormal operation of the clock generation circuit B51.

  FIG. 7 and FIG. 8 are waveform diagrams showing temporal changes of signal waveforms in the clock generation circuit B51, the clock monitoring circuit B95, and the input circuit unit B40. 7 and 8, Va indicates a clock signal (pulse signal) output from the clock generation circuit B51 and input to the clock monitoring circuit B95. Vb represents the cathode side output of the diode D1 of the input signal that has passed through the coupling capacitor C3.

  As shown in FIG. 7, the clock generation circuit B51 operates normally until the time point a and the pulse signal is oscillated toward the clock monitoring circuit B95. Therefore, Vb has the same pulse as the input waveform to the clock monitoring circuit B95. Signal.

  On the other hand, when a low signal is output from the clock generation circuit B51, the oscillation of the pulse signal is stopped at the time point a, and after that, a constant low signal that does not change with time is output from the clock generation circuit B51. The signal does not pass through the capacitor C3, and the cathode side output Vb of the diode D1 becomes zero.

Vc shows the base voltage of the transistor TR1 which is smoothed by the smoothing circuit B96, the transistor TR1 is made to flow the collector current Ic when the base voltage Vc is greater than or equal _to V ₀ (e.g., more than 5V) is. As shown in FIG. 7, until a time point a, a base voltage equal to or higher than V _{0 is} always applied to the transistor TR1 due to the input of the pulse signal to the clock monitoring circuit B95. Ic flows. On the other hand, after the time point a, the pulse signal does not pass through the capacitor C3 and the pulse signal is not output to the cathode side of the diode D1, so that the base voltage Vc of the transistor TR1 becomes V ₀ or less and the collector current Ic flows. Absent.

As described above, when the collector current Ic does not flow from the power source E toward the transistor TR1, a current flows from the power source E toward the IC 14, and the abnormal signal Vd is input to the 3A terminal of the IC 14. ing. As shown in FIG. 7, the abnormal signal Vd is not output toward the IC 14 (a low signal is output) until a time point a at which a base voltage equal to or higher than V ₀ is generated in the transistor TR1. On the other hand, after the time point “a” when the base voltage of the transistor TR1 becomes V ₀ or less, the abnormal signal Vd is output (a high signal is output).

  When the abnormal signal Vd is output to the 3A terminal of the IC 14, an abnormal signal as a low signal is output from the 3Y terminal of the IC 14. When the control unit 740 detects the abnormal signal as the low signal, the control unit 740 determines that an abnormal operation has occurred in the clock generation circuit B51 and outputs a notification signal to the outside of the pachinko machine PM via the external terminal board 600. To do. In addition, the control unit 740 can also output a notification signal to the error display device 61 to turn on the error display device 61 and notify the abnormal operation of the clock generation circuit B51.

On the other hand, as shown in FIG. 8, the pulse signal oscillation stops at the time point b when the high signal is output from the clock generation circuit B51, and thereafter, a constant high signal that does not change with time is generated from the clock generation circuit B51. The same applies to the case where the signal is output, and the abnormal signal Vd is not output until the time point b at which the base voltage equal to or higher than V ₀ is generated in the transistor TR1 (a low signal is output). On the other hand, after the time point b when the base voltage of the transistor TR1 becomes V ₀ or less, the abnormal signal Vd is output (a high signal is output). When the abnormal signal Vd is output, an abnormal signal as a low signal is output from the 3Y terminal of the IC 14, and when the control unit 740 detects the abnormal signal as the low signal, the control unit 740 causes the pachinko machine to A notification signal is output outside the PM, and the error display device 61 is turned on to notify the abnormal operation of the clock generation circuit B51.

  As described above, when the input circuit unit B14 (IC14) detects the abnormal signal Vd output from the input circuit unit B40 according to the operating state of the clock generation circuit B51, the clock generation circuit B51 operates normally. The control unit 740 can determine whether or not there is an abnormality, and when it is determined that an abnormal operation has occurred, this can be notified.

  The generation of random numbers and the acquisition thereof in the pachinko machine PM have been described above. However, the random number generation method is not limited to that by the random number generation unit 750 as described above. For example, as shown in FIG. 9A, a ROM 733, a RAM 734 and a CPU 732 having a random number generation program B37 are used as a micro control unit (hereinafter referred to as “MCU”) 800 to constitute one unit, and a second random number generation is performed. The MCU 800 as the means (random number generation circuit B31) may be configured to generate a random number (software random number). According to such a configuration, the CPU 732 in the MCU 800 has a pulse (clock signal) generated at a predetermined interval in the reference clock generation circuit 731, that is, a random number stored in the ROM 733 based on the reference clock that forms the operation reference of the CPU 732. A so-called software random number is generated by executing the generation program B37, and the generated random number is sequentially stored in the RAM 734.

  Alternatively, as shown in FIG. 9B, in addition to the ROM 733, the RAM 734, and the CPU 732, a micro control unit MCU800 ′ including a second clock count circuit 736 different from the clock count circuits B81 to B84 is configured. Random numbers may be generated by second random number generation means (random number generation circuit B31 ′) including the second clock count circuit 736. According to such a configuration, the second clock count circuit 736 counts a random number based on the reference clock generated in the reference clock generation circuit 731, and according to a read signal from the CPU 732 that is output every required time. A count value is acquired from the random number values counted by the second clock count circuit 736 and stored in the RAM 734.

  Next, the procedure for acquiring and using random numbers in an actual game will be described with reference to the flowcharts of FIGS. The control program is executed by the CPU 732 along the flowchart shown below. The control program to be executed by the CPU 732 and data necessary for the control process are described in the ROM 733.

  10 is a diagram showing a main routine in the procedure for acquiring and using a special game determination random number in the pachinko machine. FIG. 11 is an interrupt processing subroutine in the procedure for acquiring and using a special game determination random number in the pachinko machine. FIG. 12 and FIG. 13 are diagrams showing a part of a normal game processing subroutine in a procedure for obtaining and using a random number for determining a special game in a pachinko machine, and FIG. 14 is for determining a special game in a pachinko machine. FIG. 15 is a diagram showing a symbol variation processing subroutine in a procedure for acquiring and using a random number, and FIG. 15 is a diagram showing a symbol determining processing subroutine in the procedure for acquiring and using a random number for determining a special game in a pachinko machine. The flowcharts shown in FIG. 12 and FIG. 13 constitute one flowchart in which the portions of the circle A are connected.

  When the power of the pachinko machine PM is turned on, necessary parameters are initialized, and then a program relating to game processing is executed according to the main routine shown in FIG. In this main routine, an interrupt processing subroutine R0 is first executed according to the flowchart shown in FIG. In the interrupt processing subroutine R0, the normal game processing subroutine R1 is executed according to the flowcharts shown in FIGS. In the normal game processing subroutine R1, in step S100, the winning of the hit ball to the first starting winning tool 24a and the second starting winning tool 24b is checked.

  Here, the detection period of the start signal from the start winning sensors 51 and 52 by the CPU 732 is set to a predetermined period. A winning that is valid only when the start signal is detected to be a low signal in a certain detection cycle, and a high signal is detected twice in succession to the next detection cycle and further to the next detection cycle. Determined.

  In the subsequent step S110, it is determined whether or not there is a winning in the first start winning tool 24a. Here, if it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached four, the process proceeds to step S200 in FIG. On the other hand, if it is determined that the number of reserved balls is less than four and that there has been a prize, the number of reserved balls is incremented by 1, and the process proceeds to step S120.

  In step S120, the first read signal for the upper 8 bits of the 16-bit random number is output from the output circuit unit B45. Then, the first read signal for the upper 8 bits is input to the first read signal input section (G1 terminal of the IC 10) of the first count value storage circuit B91. The count value stored in the register unit (IC6) of the first count value storage circuit B91 is input to the first random number output unit (Y1 terminal to .about.Y1) of the buffer unit (IC10) by the input of the first latch signal based on the winning. Y8 terminal). Then, the process proceeds to step S130.

  In step S130, the count value output in the above stage is input to the main control unit 730 from the upper random number reading unit of the input circuit unit B40 via the CPU data bus. Then, the process proceeds to step S140. In step S140, the count value input in the above stage is stored in the RAM 734 as the upper 8 bits of the 16-bit random number. Then, the process proceeds to step S150.

  In step S150, the first read signal for the lower 8 bits of the 16-bit random number is output from the first read signal output unit of the output circuit unit B45. Then, the first read signal for the lower 8 bits is input to the first read signal input unit (G1 terminal of IC9) of the first count value storage circuit B91. Then, the count value stored in the register unit (IC5) of the first count value storage circuit B91 by the input of the first latch signal based on the winning is the first random number output unit (Y1 terminal to Y8) of the buffer unit (IC9). Terminal). Then, the process proceeds to step S160.

  In step S160, the count value output in the above stage is input from the lower random number reading unit of the input circuit unit B40 to the main control unit 730 via the CPU data bus. Then, the process proceeds to step S170. In step S170, the count value input in the above stage is stored in the RAM 734 as the lower 8 bits of a 16-bit random number. Then, together with the upper 8 bits stored in the previous step S140, it is handled as a 16-bit random number. The 16-bit random number (hardware random number) stored in the RAM 734 as described above is used as a first random number value for determining whether or not to generate a special game that gives a profit to the player.

  On the other hand, the random number generation circuit B31 reads the random number generation program B37 stored in the ROM 733, executes the program B37 based on the reference clock of the CPU 732, and generates a so-called software random number (generated in the random number generation unit 750 as described above). Generated hardware random number). Specifically, the random number generation program B37 performs an operation of adding 1 from 0 to a predetermined number at a predetermined cycle. The software random number generated by the random number generation circuit B31 in this way is used as a second random number value for determining whether or not to generate a special game that gives a profit to the player. Here, in step S180, the software random number added by the random number generation circuit B31 according to the random number generation program B37 at that time is acquired by the random number acquisition unit B33 and stored in the RAM 734 in the same manner as the hardware random number. Then, the process proceeds to step S200 in FIG.

  In step S200 of FIG. 13, it is determined whether or not there has been a prize for the second starting prize-winning tool 24b. If it is determined that there is no winning, or if there is a winning but the number of reserved balls has already reached four, the process returns to the interrupt processing subroutine R0 shown in FIG. On the other hand, if it is determined that the number of reserved balls is less than four and that there is a winning, the number of reserved balls is incremented by 1, and the process proceeds to step S210.

  In step S210, the second read signal for the upper 8 bits of the 16-bit random number is output from the second read signal output unit of the output circuit unit B45. Then, the second read signal for the upper 8 bits is input to the second read signal input unit (G1 terminal of IC12) of the second count value storage circuit B92. Then, the count value stored in the register unit (IC8) of the second count value storage circuit B92 by the input of the second latch signal based on the winning is the second random number output unit (Y1 terminal to Y8) of the buffer unit (IC12). Terminal). Then, the process proceeds to step S220.

  In step S220, the count value output in the above stage is input to the main control unit 730 from the upper random number reading unit of the input circuit unit B40 via the CPU data bus. Then, the process proceeds to step S230. In step S230, the count value input in the above stage is stored in the RAM 734 as the upper 8 bits of the 16-bit random number. Then, the process proceeds to step S240.

  In step S240, a second read signal for the lower 8 bits of the 16-bit random number is output from the second read signal output unit of the output circuit unit B45. Then, the second read signal for the lower 8 bits is input to the second read signal input unit (G1 terminal of IC11) of the second count value storage circuit B92. Then, the count value stored in the register unit (IC7) of the second count value storage circuit B92 by the input of the second latch signal based on the winning is the second random number output unit (Y1 terminal to Y8) of the buffer unit (IC11). Terminal). Then, the process proceeds to step S250.

  In step S250, the count value output in the above stage is input from the lower random number reading unit of the input circuit unit B40 to the main control unit 730 via the CPU data bus. Then, the process proceeds to step S260. In step S260, the count value input in the above stage is stored in the RAM 734 as the lower 8 bits of a 16-bit random number. Then, together with the upper 8 bits stored in the previous step S230, it is handled as a 16-bit random number. Then, the process proceeds to step S270.

  In step S270, the software random number added by the random number generation circuit B31 according to the random number generation program B37 at that time is acquired by the random number acquisition unit B33 and stored in the RAM 734. Then, the process returns to the interrupt process subroutine R0 shown in FIG. 11, and a random number update process is performed in step S10. In this random number update process, the random numbers already stored in the RAM 734 in the previous steps S170 and S260 are deleted from the storage area on the RAM 734. Subsequently, the symbol variation processing subroutine R2 is executed according to the flowchart shown in FIG.

  In the symbol variation processing subroutine R2, first, in step S300 in FIG. 14, is the symbol variation permitted state in which the symbol displayed on the symbol display device 28 is stopped and the special game is not executed? It is determined whether or not. Here, when it is determined that the symbol variation permission state is not set, that is, it is determined that the symbol is being variably displayed on the symbol display device 28 or the special game is being performed. If so, the process returns to the interrupt processing subroutine R0 shown in FIG.

  On the other hand, if it is determined that the symbol variation permission state is set, the process proceeds to step S310. In step S310, it is determined whether or not the number of reserved balls is one or more. When the number of held balls is 0, the symbol variation process is not executed, and the process returns to the interrupt process subroutine R0 shown in FIG. On the other hand, when the number of reserved balls is 1 or more, the process proceeds to step S320. In step S320, 1 is subtracted from the number of reserved balls. Then, the process proceeds to step S330.

  In step S330, among the 16-bit hardware random numbers (up to 4) stored in the RAM 734 in the previous normal game processing subroutine R1, the first stored random number is stored in the storage area on the RAM 734 from the control unit 740. Is read into the working storage area. Similarly, the software random number stored in the RAM 734 in the normal game processing subroutine R1 is also read from the storage area on the RAM 734 into the work storage area in the control unit 740. Then, the process proceeds to step S340.

  In step S340, based on the hardware random number and the software random number, the determination value calculation circuit B32 calculates a determination value for determining whether or not to generate a special game that benefits the player (determination value). Arithmetic processing). Specifically, an operation that performs any one of addition, subtraction, multiplication, and division of hardware random numbers and software random numbers, or an arithmetic process that combines these operations is executed.

For example, the arithmetic processing can be executed using a linear congruential method, which is one of random number generation methods by a computer. Linear congruential method, recurrence formula Xi + 1 = a * Xi + c (mod m), ( where, a, c, i and m is an integer, 0 <a <m, 0 <c <m, X 0 is The initial value is 0 <X ₀ <m), that is, a certain number Xi multiplied by a certain constant a and further added with a certain number c is referred to as a remainder obtained by dividing by a certain number m as Xi + 1. This is a method for obtaining a sequence of random numbers {Xi} (0 <Xi <m) that repeats periodically (cycle is m) by a recurrence formula that performs integer arithmetic.

  When the above linear congruence method is applied to the calculation of the determination value based on the hardware random number and the software random number acquired by the random number acquisition means B33, the following is obtained. The acquired software random number is set as the constant a in the above recurrence formula, the acquired hardware random number is set as the constant c in the same manner, and 65536 is set as m. If the calculation based on the recursion formula Xi + 1 = a * Xi + c (mod m) is executed by the judgment value calculation circuit B32, a random number sequence {Xi} (0 <Xi <65536) that repeats with 65536 as a period. ) Can be obtained. If one value of the sequence {Xi} calculated by the random number acquisition means B33 is extracted at an arbitrary time in a state where the operation for obtaining the sequence {Xi} is being executed, the range from 0 to 65536 is obtained. Any one of the values can be obtained as an arithmetic value based on a hardware random number and a software random number. Note that the random number generation algorithm is not necessarily limited to the linear congruent method described above. For example, when it is desired to generate a long-period random number at a higher speed than the linear congruent method, the Mersenne Twister method (Mersenne Twister method, for example) ) Is preferably applied.

  In step S350 following the determination value calculation process, the calculated value of the random number calculated based on the hardware random number and the software random number in step S340 is compared with the data in the hit determination table B36 by the hit determination means B34. Then, it is determined whether or not it is won.

  In the present invention, regardless of the occurrence of abnormal operation in the random number clock generation means B51 or the clock count circuits B81 to B84, the calculated value of the random number calculated based on the hardware random number and the software random number The ratio that matches the winning random number in the table B36 is constant. That is, for example, when a calculation of a determination value is performed such that a hardware random number and a software random number are added, the determination value added based on the normally updated hardware random number is a hit random number value The ratio and the ratio that the judgment value added when the same hardware random number is read repeatedly without being updated normally due to the abnormal operation of the hardware as described above is always a random number value. It is set to be constant. Therefore, even if an abnormal operation of hardware occurs, the probability of occurrence of a jackpot game does not change and is always constant, and the abnormal operation does not directly affect the game.

  When it is determined in step S350 that the winning random number value is set as described above, it is determined that the winning value is not won, that is, when it is determined that the calculated value is not the predetermined winning random number, the process proceeds to step S360. In step S360, a stop symbol that finally displays a predetermined losing symbol is selected from the symbol data in the symbol data table B35. Then, the process proceeds to step S390.

  On the other hand, if it is determined in step S350 that the game is won, that is, if it is determined that the calculated value is a predetermined hit random number, the process proceeds to step S370. In step S370, a stop symbol that finally displays a predetermined winning symbol is selected from the symbol data in the symbol data table B35. Then, the process proceeds to step S380.

  In step S380, a special game flag is set. Then, the process proceeds to step S390. In step S390, the symbol display device 28 on the game board 20 displays a variation display of the symbol that finally stops and displays the predetermined winning symbol selected in step S370 or the predetermined lose symbol selected in step S360. Is executed. Then, the process returns to the interrupt processing subroutine R0 shown in FIG.

  In the interrupt processing subroutine R0 shown in FIG. 11, a symbol determination processing subroutine R3 as shown in FIG. 15 is executed. Here, in step S400, it is determined whether or not the time period for which the symbol variation timer has already been set as the specified value has elapsed. If it is determined that the symbol variation timer has not yet passed the specified value, the process returns to the interrupt processing subroutine R0 shown in FIG.

  On the other hand, if it is determined in step S400 that the symbol variation timer has passed the specified value, the symbol determination flag is turned on in subsequent step S410. Then, the process returns to the interrupt processing subroutine R0 shown in FIG. Subsequently, in the interrupt processing subroutine R0, a special game processing subroutine R4 is executed.

  In the special game processing subroutine R4, if the symbol determination flag is turned on in step S410 of the previous symbol determination processing subroutine R3 and the special game flag is set in step S380 of the symbol variation processing subroutine R2, a special game flag is set. A game, that is, a jackpot game is executed. In this jackpot game, the big prize device 26 is opened for a predetermined time, which is advantageous for the player. Then, after the jackpot game ends, the special game flag and the symbol determination flag are cleared, and then the process returns to the main routine. On the other hand, when the special game flag or the symbol determination flag is not set, this process is terminated.

  Subsequently, in the main routine, a random number update process is executed in step S5. This random number update process deletes the random number stored in the RAM 734 from the storage area on the RAM 734 and is executed every predetermined time (for example, every 40 μsec) regardless of whether or not a special game has occurred. It has become so. In the main routine, the game is continued by repeating the interrupt processing subroutine R0 and the random number update processing described above.

  Here, the effects achieved in the present invention are as follows. That is, in the gaming machine according to the present invention, each random number value generated by a plurality of random number generation means is calculated as a determination value for determining whether or not to generate a special game that benefits the player. The calculation value obtained by this is used. For this reason, the process of generating the determination value can be made more complicated by calculation compared with the case where the random number generated by one type of random number generation means is determined as it is as the determination value. It is possible to prevent fraudulent acts such as intentionally drawing a random number that generates a special game advantageous to those who perform the game. In addition to the method of acquiring hardware random numbers that are relatively difficult to perform fraud, further complex judgment values as in the present invention can provide a gaming machine with improved security problems. is there.

  Further, according to the gaming machine according to the present invention, one of a plurality of random number generating means is configured to include a CPU, and a so-called software random number is obtained by a method of counting random numbers by CPU program control based on a CPU reference clock. Can be generated. In such a case, even if an abnormal operation occurs in hardware (first random number generation means) including random number clock generation means that constitutes the other of the plurality of random number generation means, Only a software random number generated by a CPU constituting one of a plurality of random number generation means is obtained as a determination value, and a special game is generated regardless of a hardware failure related to random number generation unless the CPU itself fails. Random numbers can be drawn. In this way, even if a failure occurs in which the CPU repeatedly reads the same count value generated in the first random number generator, the parts such as the random number generator that caused the abnormal operation are replaced. In the meantime, it is possible to continue the game by using only the software random number as the judgment value.

  Furthermore, if the ratio at which the judgment value matches the random number value is set to be constant regardless of hardware failure, even if the same count value is repeatedly read due to hardware failure, Since the probability of a jackpot game that gives a profit to the player does not fluctuate, it is possible to continue the game without being directly affected by this abnormality without judging any hardware abnormality and taking any action It is.

  In addition, when an abnormality occurs in the hardware, if it is configured to notify the outside so that it can be recognized, only a software random number can be obtained by prompting the game hall to replace the hardware immediately after the abnormality has occurred. It is possible to minimize the decrease in security associated with continuing the game with the determination value.

  Although the preferred embodiments of the present invention have been described so far, the scope of the present invention is not limited to the above-described embodiments. For example, in the above embodiment, the random number generation program B37 stored in the ROM 733 is read, and the random number generation circuit B31 constituting the second random number generation means generates a predetermined interval generated in the crystal oscillator of the reference clock generation circuit 731. Although the random number generation program B37 is executed on the basis of the pulse (clock signal), that is, the reference clock forming the operation reference of the CPU 732, the software random number is generated. The second clock count circuit 736 (see (b)) is used, and the second clock count circuit 736 generates a random number acquired as the second random number value based on the reference clock generated by the reference clock generation circuit 731. You may comprise so that it may count.

  Each of the first random number generation means and the second random number generation means is constituted by a random number generation unit 750 having a random number clock generation circuit B51, and the hardware random number generated by these random number generation units 750 is determined as a determination value. A calculation value obtained by performing a predetermined calculation by the calculation circuit B32 may be used as a determination value for determining whether or not to generate a special game. With such a configuration, the process of generating the judgment value is more complicated by calculation and the security against fraud is further improved as compared to the case where the single random number generator 750 generates a hardware random number alone. It will be done.

  Alternatively, both the first random number generation unit and the second random number generation unit may be configured by the random number generation circuit B31. In such a case, a calculation value obtained by performing a predetermined calculation on the plurality of software random numbers generated according to the random number generation program B37 by the determination value calculation circuit B32 is set as a determination value for occurrence of the special game. Even with such a configuration, compared with the case where the generated software random number is used as a determination value without performing arithmetic processing, security against fraud is further improved.

  Furthermore, in the above embodiment, a gaming machine equipped with a random number generator has been described taking the pachinko machine PM as an example, but the pachinko machine PM is an example of a gaming machine, and the gaming machine is not limited to a pachinko machine. It may be a slot machine. In this case, the symbol display device that displays a plurality of types of symbols based on the result obtained by the random number obtaining means is constituted by, for example, a spinning reel device having a plurality of spinning reels that can be rotated by a motor. .

It is a front view of the game board of the gaming machine according to the present invention. It is a rear view showing the internal structure of the gaming machine according to the present invention. It is a block diagram showing the outline of the control system provided in the said gaming machine. It is a block diagram showing the part concerning control of the gaming machine provided in the gaming machine and the part concerning generation of random numbers. It is a circuit diagram showing the random number generation part and its periphery in the said gaming machine. It is an enlarged view of a clock monitoring circuit in the random number generator. It is the figure which showed the signal produced | generated in the said random number generation part with the timing chart. It is the figure which showed the signal produced | generated in the said random number generation part with the timing chart. It is a block diagram showing MCU etc. of the control system provided in the said game machine, (a) shows the random number generation method based on a random number generation program, (b) shows the random number based on a 2nd clock count circuit It is a figure which shows the production | generation method of. It is the figure which showed the main routine in the procedure of acquisition and utilization of the random number for special game determination of the said gaming machine. It is the figure which showed the interruption processing subroutine in the procedure of acquisition and use of the random number for special game decision of the aforementioned gaming machine. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition and utilization of the random number for special game determination of the said gaming machine. It is the figure which showed a part of normal game processing subroutine in the procedure of acquisition and utilization of the random number for special game determination of the said gaming machine. It is the figure which showed the design fluctuation processing subroutine in the procedure of acquisition and use of the random number for special game decision of the aforementioned gaming machine. It is the figure which showed the symbol decision processing subroutine in the procedure of acquisition and use of the random number for special game decision of the aforementioned gaming machine.

Explanation of symbols

PM Pachinko machine (game machine)
1 Outer frame 2 Front frame 20 Game board 28 Symbol display device 732 CPU
733 ROM
734 RAM
740 Control unit (notification signal output means)
750 random number generator (first random number generator)
800 MCU (micro control unit)
B31, B31 ′ random number generation circuit (second random number generation means)
B32 determination value calculation circuit B33 random number acquisition means B34 hit determination means B35 symbol data table B36 hit determination table B37 random number generation program B51 random number clock generation circuit (random number clock generation means)
B81 First clock count circuit (random number counting means)
B82 Second clock count circuit (random number counting means)
B83 Third clock count circuit (random number counting means)
B84 Fourth clock count circuit (random number counting means)
B91 First count value storage circuit B92 Second count value storage circuit B95 Clock monitoring circuit B96 Smoothing circuit section

Claims (5)

First random number generation means and second random number generation means for counting random values every required time, and one random number value generated by the first random number generation means is used as a first random value. Random number acquisition means for acquiring a count value as a second random number value from among the random number values generated by the second random number generation means, and obtaining the result obtained by the random number acquisition means A gaming machine that generates a special game that benefits players based on:
The random number acquisition unit compares the determination value calculated based on the first random number value and the second random number value with a preset hit random number value, and the determination value is the hit random number value. A game machine characterized in that if it matches, the game is determined to be a hit and the special game is generated. The first random number generation means includes a random number clock generation means for generating a clock at a predetermined frequency, and a random number count means for counting a random value based on the clock generated by the random number clock generation means. The first random number value is acquired from the random number values counted by the random number counting unit by the random number acquiring unit,
2. The gaming machine according to claim 1, wherein the second random number generation means counts the second random number value based on a reference clock of a CPU that controls the operation of the random number acquisition means.   The gaming machine according to claim 2, wherein the second random number value is acquired from random number values counted by program control of the CPU.   The gaming machine according to claim 3, wherein a rate at which the determination value matches the winning random number value is constant regardless of the first random number value.   5. The gaming machine according to claim 4, further comprising notification signal output means for outputting a predetermined notification signal indicating the abnormal operation when an abnormal operation of the random number clock generation means occurs.

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