JP2006236105A - アクセス制御装置及びその制御方法 - Google Patents

アクセス制御装置及びその制御方法 Download PDF

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Publication number
JP2006236105A
JP2006236105A JP2005051369A JP2005051369A JP2006236105A JP 2006236105 A JP2006236105 A JP 2006236105A JP 2005051369 A JP2005051369 A JP 2005051369A JP 2005051369 A JP2005051369 A JP 2005051369A JP 2006236105 A JP2006236105 A JP 2006236105A
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JP
Japan
Prior art keywords
memory
access
memory module
address
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2005051369A
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English (en)
Japanese (ja)
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JP2006236105A5 (https=
Inventor
Koji Aoki
恒治 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2005051369A priority Critical patent/JP2006236105A/ja
Priority to US11/345,388 priority patent/US20060195665A1/en
Priority to CNA2006100078923A priority patent/CN1825473A/zh
Publication of JP2006236105A publication Critical patent/JP2006236105A/ja
Publication of JP2006236105A5 publication Critical patent/JP2006236105A5/ja
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
JP2005051369A 2005-02-25 2005-02-25 アクセス制御装置及びその制御方法 Withdrawn JP2006236105A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2005051369A JP2006236105A (ja) 2005-02-25 2005-02-25 アクセス制御装置及びその制御方法
US11/345,388 US20060195665A1 (en) 2005-02-25 2006-02-02 Access control device, method for changing memory addresses, and memory system
CNA2006100078923A CN1825473A (zh) 2005-02-25 2006-02-23 存储器控制装置、改变存储器地址的方法以及存储系统

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005051369A JP2006236105A (ja) 2005-02-25 2005-02-25 アクセス制御装置及びその制御方法

Publications (2)

Publication Number Publication Date
JP2006236105A true JP2006236105A (ja) 2006-09-07
JP2006236105A5 JP2006236105A5 (https=) 2008-04-10

Family

ID=36933127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005051369A Withdrawn JP2006236105A (ja) 2005-02-25 2005-02-25 アクセス制御装置及びその制御方法

Country Status (3)

Country Link
US (1) US20060195665A1 (https=)
JP (1) JP2006236105A (https=)
CN (1) CN1825473A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011530734A (ja) * 2008-08-08 2011-12-22 ヒューレット−パッカード デベロップメント カンパニー エル．ピー． 標準メモリモジュールとピン互換性のあるメモリモジュール内における独立制御可能且つ再構成可能な仮想メモリデバイス
US8867294B2 (en) 2010-03-12 2014-10-21 Ps4 Luxco S.A.R.L. Semiconductor device, refresh control method thereof and computer system

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7904639B2 (en) * 2006-08-22 2011-03-08 Mosaid Technologies Incorporated Modular command structure for memory and memory system
JP2008242731A (ja) * 2007-03-27 2008-10-09 Oki Electric Ind Co Ltd マイクロプロセッサ設計プログラム、マイクロプロセッサ設計装置及びマイクロプロセッサ
JP5171448B2 (ja) * 2007-07-31 2013-03-27 キヤノン株式会社 画像形成装置及びその制御方法
JP2011081732A (ja) * 2009-10-09 2011-04-21 Elpida Memory Inc 半導体装置及びその調整方法並びにデータ処理システム
CN111158600B (zh) * 2019-12-30 2023-10-27 中国人民解放军国防科技大学 一种提升高带宽存储器（hbm）访问效率的装置和方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6571325B1 (en) * 1999-09-23 2003-05-27 Rambus Inc. Pipelined memory controller and method of controlling access to memory devices in a memory system
JP4159415B2 (ja) * 2002-08-23 2008-10-01 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
US7222224B2 (en) * 2004-05-21 2007-05-22 Rambus Inc. System and method for improving performance in computer memory systems supporting multiple memory access latencies

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011530734A (ja) * 2008-08-08 2011-12-22 ヒューレット−パッカード デベロップメント カンパニー エル．ピー． 標準メモリモジュールとピン互換性のあるメモリモジュール内における独立制御可能且つ再構成可能な仮想メモリデバイス
KR101477849B1 (ko) * 2008-08-08 2014-12-30 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 메모리 모듈 및 메모리 모듈 제어 방법
US8924639B2 (en) 2008-08-08 2014-12-30 Hewlett-Packard Development Company, L.P. Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules
US8867294B2 (en) 2010-03-12 2014-10-21 Ps4 Luxco S.A.R.L. Semiconductor device, refresh control method thereof and computer system

Also Published As

Publication number Publication date
US20060195665A1 (en) 2006-08-31
CN1825473A (zh) 2006-08-30

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