JP2006229784A - Digital/analog converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a very small size digital/analog converter by reducing the circuits in size. <P>SOLUTION: The digital analog converter 10 forms, on the front surface of a p-substrate, a plurality of resistors R1 to R9 that are connected in series, a plurality of switching elements of n-type MOS transistors N1 to N7 and p-type MOS transistors P1 to P7 and outputs analog voltages, corresponding to the predetermined digital values by sequentially selecting voltages of each connecting point of a plurality of resistors R1 to R9, connected in series with the switching of the n-type MOS transistors N1 to N7 and p-type MOS transistors P1 to P7. The n-type MOS transistors N1 to N7 and p-type MOS transistors P1 to P7 are formed in the well-well W1 to W7, formed individually in separation and the well potential can be set individually. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital-to-analog converter (DAC) used in a MOS integrated circuit, and in particular, outputs from series-connected resistance elements and connection points of the resistance elements. The present invention relates to a digital-analog converter having a switch element using a MOS transistor for selecting an arbitrary potential.

  As a conventional digital-analog converter (DAC (Digital-to-Analog Converter)), for example, as disclosed in Patent Document 1, a potential is extracted from each connection point of a resistance element, and a MOS transistor is used. There is a method of selecting an arbitrary potential in the tournament format.

  That is, the digital-analog converter of the above publication has a circuit that outputs eight levels of voltages as shown in FIG. The power supply VDD supplied from the outside is applied to one end of the series resistors R21 to R29 constituting this circuit, and the other end is grounded. The potential at each contact point of the series resistors R21 to R29 is an integer multiple of VDD / 9 when the resistance values are equal.

  In the digital-analog converter having the above configuration, the inputs IN21 to IN23 must be set as shown in Table 1 in order to output a voltage to the output OUT.

Japanese Patent Laid-Open No. 60-112327 (released on June 18, 1985)

  In the above conventional digital-analog converter, in the operating state, the drain-well voltage (VDB) and the source-well voltage (VSB) of each of the N-type MOS transistors N21 to N34 are as shown in Table 1. The maximum voltage is close to VDD, such as VDD × 1/9 to VDD × 8/9. This is because, in the digital-analog converter including the N-type MOS transistors N21 to N34 shown in FIG. 5, a large P-well is formed in one semiconductor substrate, and an N-type high-concentration diffusion layer is injected into the P-well. Sources and drains for the N-type MOS transistors N21 to N34 are formed. Since this P well is common to all of the N-type MOS transistors N21 to N34, it is set to the ground (GND) potential as shown in FIG. As a result, the drain-well voltage (VDB) and the source-well voltage (VSB) of each of the N-type MOS transistors N21 to N34 become a potential difference between the voltage applied to the source and the ground (GND) potential.

  On the other hand, the area (S) of the MOS transistor is determined by the magnitude of the drive voltage. H. Due to the scaling law shown by Dennard, it increases in proportion to the square of the drive voltage as shown in FIG.

  As a result, the MOS transistors used in the conventional digital-analog converter circuit have a problem that there is a limit in reducing the transistor size unless the VDD voltage value is lowered in order to secure the breakdown voltage by this scaling rule. Yes.

  The present invention has been made in view of the above-described conventional problems, and its object is to reduce the drive voltage of the MOS transistor and reduce the transistor size without lowering the VDD voltage by devising the well structure and the circuit. Thus, it is to provide a fine digital-analog converter with a reduced circuit scale.

  In order to solve the above-described problems, the digital-analog converter according to the present invention includes, for example, a plurality of resistors connected in series and a plurality of MOS transistors serving as switching elements formed on a surface of a substrate such as a semiconductor substrate. A digital that outputs an analog voltage corresponding to the predetermined digital value by sequentially selecting a voltage from each connection point of the plurality of resistors connected in series by switching by each MOS transistor when a value is input In the analog converter, each of the MOS transistors is formed in a well formed separately, and the well potential can be individually set.

  That is, conventionally, a large well is formed on the surface of one semiconductor substrate, and a plurality of MOS transistors are formed in the well. Therefore, conventionally, since the potential in the well of one MOS transistor affects the MOS transistors in other locations, it is necessary to apply a back gate bias voltage. The generation of the back bias voltage has the following two problems. One is a problem that the transistor size cannot be reduced by the above-described scaling rule to secure the withstand voltage, and the other is that the threshold voltage rises while the voltage applied to the gate is constant. The rise in voltage is a problem that the ON current of the MOS transistor is reduced and the driving capability of each MOS transistor is lowered.

  However, according to the present invention, each MOS transistor is formed separately and the well potential can be individually set. As a result, in the case of the well-separated MOS transistor as in the present invention, the drive voltage of each MOS transistor can be lowered and the transistor size can be reduced as much as there is no back gate bias effect. The driving capability of the MOS transistor can be improved.

  Therefore, by devising the well structure and the circuit, it is possible to reduce the circuit scale and provide a fine digital analog converter by reducing the driving voltage of the MOS transistor and reducing the transistor size without reducing the VDD voltage. .

  In the present invention, it is preferable that the source potential of each MOS transistor is formed to be the same potential as the well.

  That is, by adopting a well-separated MOS transistor, the source potential of each MOS transistor can be the same as that of the well. Then, by making the source potential of each MOS transistor the same as that of the well, the driving voltage of the MOS transistor can be reduced. As a result, the installation area of the MOS transistor can be reduced, so that the circuit scale can be greatly reduced and a fine digital-analog converter can be provided.

  In the present invention, the well is formed with a source electrode and a drain electrode of a MOS transistor and an electrode terminal, and the source electrode and the electrode terminal are electrically connected by a conductor such as a wiring pattern. It is preferable that This ensures that the source potential and the well are the same potential.

  In order to solve the above problems, the digital-analog converter of the present invention has a plurality of resistors connected in series and MOS transistors as a plurality of switch elements formed on the surface of the substrate, and a predetermined digital value is input. A digital analog converter that sequentially selects a voltage from each connection point of the plurality of resistors connected in series by switching by each MOS transistor and outputs an analog voltage corresponding to the predetermined digital value. A pair of P-type MOS transistor and N-type MOS transistor constituting each set is formed in a first well formed separately for each set, and the P-type MOS transistor or the N-type MOS transistor is formed. Either one of the two is formed in the second well formed in the first well. It is a symptom.

  In the present invention, a pair of P-type MOS transistor and N-type MOS transistor constituting each set is formed in a first well formed separately for each set, and the P-type MOS transistor or N-type MOS transistor or N-type MOS transistor is formed. One of the type MOS transistors is formed in the second well formed in the first well.

  In this way, a pair of P-channel and N-channel P-type MOS transistors and N-type MOS transistors are paired, and one MOS transistor is formed in a double well structure called a second well formed in the first well. When provided, the entire occupied area can be reduced, and the demand for downsizing can be met. Further, in the case of this structure, it is possible to reduce the number of driving wirings as compared with the prior art by making good use of the characteristic that the voltage that is ON at P / N is reversed. Therefore, it is possible to contribute to simplification and miniaturization of the circuit.

  In the present invention, the first source potential of either the P-type MOS transistor or the N-type MOS transistor is formed to be the same potential as the first well, and the P-type MOS transistor or the N-type MOS transistor It is preferable that the other second source potential of the type MOS transistor is formed to be the same potential as the second well.

  Thereby, the driving voltage of the MOS transistor can be reliably reduced. As a result, the installation area of the MOS transistor can be reduced, so that the circuit scale can be greatly reduced and a fine digital-analog converter can be provided.

  In the present invention, the first well is formed with the first source electrode, the first drain electrode, and the first electrode terminal of either the P-type MOS transistor or the N-type MOS transistor, and The first source electrode and the first electrode terminal are electrically connected by a conductor such as a wiring pattern, and the second well has either the P-type MOS transistor or the N-type MOS. The second source electrode, the second drain electrode, and the second electrode terminal are formed, and the second source electrode and the second electrode terminal are electrically connected by a conductor such as a wiring pattern. Is preferred. This ensures that the source potential and the well are the same potential.

  In the present invention, the first well is an N well, a P-type MOS transistor is formed in the N well, and the second well is a P well, and the N-type MOS is formed in the P well. A transistor is preferably formed.

  Generally, the substrate is a silicon (Si) substrate and is a P-well. Therefore, a pure N well is formed as a first well on this substrate to form a P-type MOS transistor. Then, a second well that is a P well is formed in the first well that is the N well, and an N-type MOS transistor is formed.

  Therefore, with the configuration of the present invention, a pair of P-type MOS transistor and N-type MOS transistor formed separately for each set can be easily manufactured.

  Further, in the present invention, each MOS transistor selects a voltage from each connection point of the plurality of resistors connected in series in order from a lower bit in the predetermined digital value by switching by each MOS transistor. It is preferable to output an analog voltage corresponding to the predetermined digital value.

  As a result, it is possible to employ a method of selecting from the lower bits generally performed in a fine digital-to-analog converter with a reduced circuit scale.

  Further, in the present invention, each MOS transistor selects a voltage from each connection point of the plurality of resistors connected in series in order from an upper bit in the predetermined digital value by switching by each MOS transistor. It is preferable to output an analog voltage corresponding to the predetermined digital value.

  In the case of such a method of selecting from the upper bits, since the lower bits are the final stage, it is possible to finally output the voltage with the minimum resolution of the voltage value divided by the resistance. That is, it is possible to further increase the resolution (gradation) using this output.

  In the digital-analog converter of the present invention, as described above, each MOS transistor is formed in a well formed separately and the well potential can be individually set.

  In addition, as described above, the digital-analog converter of the present invention includes a pair of P-type MOS transistors and N-type MOS transistors that are formed in a first well formed separately for each set. In addition, either the P-type MOS transistor or the N-type MOS transistor is formed in the second well formed in the first well.

  Therefore, in the case of the well-separated MOS transistor as in the present invention, the driving voltage of each MOS transistor can be lowered and the transistor size can be reduced as much as there is no back gate bias effect. The driving capability of the MOS transistor can be improved.

  Therefore, by devising the well structure and the circuit, it is possible to reduce the circuit scale and provide a fine digital analog converter by reducing the driving voltage of the MOS transistor and reducing the transistor size without reducing the VDD voltage. There is an effect.

  The digital-analog converter of the present invention is formed so that the source potential of each MOS transistor is the same as that of the well.

  That is, by adopting a well-separated MOS transistor, the source potential of each MOS transistor can be the same as that of the well. Then, by making the source potential of each MOS transistor the same as that of the well, the driving voltage of the MOS transistor can be reduced. As a result, since the installation area of the MOS transistor can be reduced, the circuit scale can be greatly reduced and a fine digital-analog converter can be provided.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIGS. 1 to 3 as follows.

  As shown in FIG. 1, the digital-analog converter 10 of the present embodiment includes a plurality of resistors Rm (m is 1 to 9 in the present embodiment) connected in series and a P-type MOS transistor Pn that is a plurality of switch elements. (N is 1 to 7 in the present embodiment) and an N-type MOS transistor Nn (n is 1 to 7 in the present embodiment). Note that m and n are not necessarily limited to this, and may take other positive integer values.

  In the present embodiment, the P-type MOS transistor Pn and the N-type MOS transistor Nn are each combined one by one. The P-type MOS transistor Pn and the N-type MOS transistor Nn in each set are respectively It is formed in a well Wn (n is 1 to 7 in the present embodiment) separated for each set.

  That is, in the present embodiment, as shown in FIG. 2, the P-type MOS transistor Pn is formed in the N well 2 which is the well Wn as the first well partitioned in the P substrate 1 as the figure substrate. Yes. On the other hand, the N-type MOS transistor Nn is also formed in the P well 3 formed inside the N well 2 which is the well Wn in the same section in the P substrate 1. Therefore, in the present embodiment, the N-type MOS transistor Nn has the double well structure 4 because the P well 3 is formed inside the N well 2. This double well structure 4 is sometimes referred to as a triple well because it is a triple well when the P substrate 1 is considered as a P well.

  In this embodiment, since the P substrate 1 is used as the semiconductor substrate, the well Wn is the N well 2. However, if an N substrate is used as the semiconductor substrate, the well Wn is P. It becomes well 3.

  Specifically, the P-type MOS transistor Pn is formed in the P-type high-concentration diffusion layers 5 and 5 injected into two places in the N well 2 defined in the P substrate 1 as shown in FIG. And a gate electrode 7 with a gate insulating film 6 formed above the channel width region between the PMOS source 11 and the PMOS drain 12. Further, an N-type high concentration diffusion layer 9 is implanted on the side thereof. Further, a field insulating film 8 is formed around the P-type high concentration diffusion layers 5 and 5 and the N-type high concentration diffusion layer 9.

  On the other hand, the N-type MOS transistor Nn specifically has an N-type high concentration diffusion layer 9 implanted in two places in the P-well 3 formed inside the N-well 2 as shown in FIG. The NMOS source 21 and the NMOS drain 22 constituted by 9 and the gate electrode 7 through the gate insulating film 6 formed above the channel width region between the NMOS source 21 and the NMOS drain 22 ing. Further, a P-type high concentration diffusion layer 5 is implanted on the side thereof. Further, a field insulating film 8 is formed around the N-type high concentration diffusion layers 9 and 9 and the P-type high concentration diffusion layer 5.

  Here, in this embodiment, the PMOS source 11 and the N-type high concentration diffusion layer 9 are connected by the wiring pattern 14 shown in FIG. 1 through the contact hole 13 shown in FIG. As a result, the PMOS source 11 is connected to the N well 2 via the wiring pattern 14 and the N type high concentration diffusion layer 9, and the source potential of the PMOS source 11 and the N well 2 in the P type MOS transistor Pn. Are at the same potential.

  The NMOS source 21 and the P-type high concentration diffusion layer 5 are connected by the wiring pattern 15 shown in FIG. 1 through the contact hole 13 shown in FIG. As a result, the NMOS source 21 is connected to the P well 3 via the wiring pattern 15 and the P-type high concentration diffusion layer 5, and the source potential of the NMOS source 21 and the P well 3 in the N-type MOS transistor Nn. Are at the same potential.

  Here, as shown in FIG. 1, the digital-analog converter 10 of the present embodiment has a circuit system in which selection is made from the lower bits as in the prior art.

  In this embodiment, the connection point between the series-connected resistors R1 and R2 is connected to the NMOS source 21 of the N-type MOS transistor N1, and the series-connected resistors R2 and R3 are connected to each other. A connection point between them is connected to the PMOS source 11 of the P-type MOS transistor P1. A connection point between the series-connected resistors R3 and R4 is connected to the NMOS source 21 of the N-type MOS transistor N2, and a connection point between the series-connected resistors R4 and R5 is a P-type MOS. It is connected to the PMOS source 11 of the transistor P2. A connection point between the series-connected resistors R5 and R6 is connected to the NMOS source 21 of the N-type MOS transistor N3, and a connection point between the series-connected resistors R6 and R7 is a P-type MOS. The transistor P3 is connected to the PMOS source 11. The connection point between the resistor R7 and the resistor R8 connected in series is connected to the NMOS source 21 of the N-type MOS transistor N4, and the connection point between the resistor R8 and the resistor R9 connected in series is the P-type MOS. It is connected to the PMOS source 11 of the transistor P4.

  The NMOS drain 22 of the N-type MOS transistor N1 and the PMOS drain 12 of the P-type MOS transistor P1 are connected to the NMOS source 21 of the N-type MOS transistor N5, and the NMOS drain 22 and the P-type of the N-type MOS transistor N2. The PMOS drain 12 of the MOS transistor P2 is connected to the NMOS source 21 of the P-type MOS transistor P5. The NMOS drain 22 of the N-type MOS transistor N3 and the PMOS drain 12 of the P-type MOS transistor P3 are connected to the NMOS source 21 of the N-type MOS transistor N6, and the NMOS drain 22 and the P-type MOS transistor of the N-type MOS transistor N4. The PMOS drain 12 of P4 is connected to the NMOS source 21 of the P-type MOS transistor P6.

  Further, the NMOS drain 22 of the N-type MOS transistor N5 and the PMOS drain 12 of the P-type MOS transistor P5 are connected to the NMOS source 21 of the N-type MOS transistor N7, and the NMOS drain 22 and the P-type of the N-type MOS transistor N6. The PMOS drain 12 of the MOS transistor P6 is connected to the NMOS source 21 of the P-type MOS transistor P7.

  The NMOS drain 22 of the N-type MOS transistor N7 and the PMOS drain 12 of the P-type MOS transistor P7 are connected to the output OUT.

  Further, the control signal IN1 is input to the gate electrodes 7 of the N-type MOS transistors N1 to N4 and the P-type MOS transistors P1 to P4 via the inverter INV1. The control signal IN2 is input to the gate electrodes 7 of the N-type MOS transistors N5 and N6 and the P-type MOS transistors P5 and P6 via the inverter INV2. The control signal IN3 is input to the gate electrodes 7 of the N-type MOS transistor N7 and the P-type MOS transistor P7 via the inverter INV3.

  A method for extracting the drive voltage in the digital-analog converter 10 having the above configuration will be described.

  For example, in order to extract a drive voltage of VDD × 7/9 from the output OUT with this digital analog converter 10, as shown in Table 2, the control signals IN1, IN2, and IN3 are set to (0, 1, 1). To do.

  As a result, first, as shown in FIG. 1, the control signal IN1 “0” is inverted by the inverter INV1 to become “1”, the N-type MOS transistors N1 to N4 are turned on, and the P-type MOS transistors P1 to P4 are turned on. Is turned off. As a result, VDD × 1/9 is output from the N-type MOS transistor N1 and input to the N-type MOS transistor N5, and VDD × 3/9 is output from the N-type MOS transistor N2 to output the P-type MOS transistor. Input to P5. Further, VDD × 5/9 is output from the N-type MOS transistor N3 and input to the N-type MOS transistor N6, and VDD × 7/9 is output from the N-type MOS transistor N4 to output the P-type MOS transistor P6. Is input.

  Next, the control signal IN2 “1” is inverted by the inverter INV2 to become “0”, the N-type MOS transistors N5 and N6 are turned off, and the P-type MOS transistors P5 and P6 are turned on. As a result, VDD × 3/9 is output from the P-type MOS transistor P5 and input to the N-type MOS transistor N7, and VDD × 7/9 is output from the P-type MOS transistor P6. Input to P7.

  Next, the control signal IN3 “1” is inverted by the inverter INV3 to become “0”, the N-type MOS transistor N7 is turned off, and the P-type MOS transistor P7 is turned on. As a result, VDD × 7/9 is output from the P-type MOS transistor P7, and VDD × 7/9 is output from the output OUT.

  On the other hand, when VDD × 7/9 is extracted from the output OUT described above, in the present embodiment, the source potential of the NMOS source 21 and the P well 3 in the N-type MOS transistor Nn are at the same potential, and P The source potential of the PMOS source 11 and the N well 2 in the type MOS transistor Pn are at the same potential.

  For this reason, the drive voltages of the N-type MOS transistors N1 to N4 are zero. The drive voltage of the P-type MOS transistors P1 to P4 is VDD × 1/9 by the following calculation.

P-type MOS transistor P1: VDD × 2 / 9−VDD × 1/9 = VDD × 1/9
P-type MOS transistor P2: VDD × 4 / 9−VDD × 3/9 = VDD × 1/9
P-type MOS transistor P3: VDD × 6 / 9−VDD × 5/9 = VDD × 1/9
P-type MOS transistor P4: VDD × 8 / 9−VDD × 7/9 = VDD × 1/9
Next, the drive voltage of the P-type MOS transistors P5 and P6 becomes zero. Further, the drive voltage of the N-type MOS transistors N5 and N6 is VDD × 2/9 by the following calculation.

N-type MOS transistor N5: VDD × 3 / 9−VDD × 1/9 = VDD × 2/9
N-type MOS transistor N6: VDD × 7 / 9−VDD × 5/9 = VDD × 2/9
Next, the drive voltage of the P-type MOS transistor P7 becomes zero. The driving voltage of the N-type MOS transistor N7 is VDD × 4/9 by the following calculation.

N-type MOS transistor N7: VDD × 7 / 9−VDD × 3/9 = VDD × 4/9
In summary, the driving voltages of the N-type MOS transistor Nn and the P-type MOS transistor Pn are as shown in Table 2.

  Similarly, when other voltages are taken out, the voltages shown at the output OUT in Table 2 can be taken out by setting the control signals IN1, IN2, and IN3 as shown in Table 2. Further, the driving voltages of the respective N-type MOS transistors Nn and P-type MOS transistors Pn at that time are as shown in Table 2.

  Therefore, in this digital-analog converter 10, the voltage applied to the N-type MOS transistor Nn and the P-type MOS transistor Pn has a drain-well voltage (VDB) of VDD × 1/9 to VDD × 4/9, Compared to VDD × 8/9 in the prior art, the voltage value is reduced to ½.

  As described above, in the digital-analog converter 10 according to the present embodiment, the pair of P-type MOS transistor Pn and N-type MOS transistor Nn constituting each set is formed as a first well formed separately for each set. One of the P-type MOS transistor Pn and the N-type MOS transistor Nn is formed in the second well formed in the first well, and the well potential is individually formed. Can be set.

  That is, in the present embodiment, the N-type MOS transistor Nn is formed in the P well 3 as the second well formed in the N well 2 as the first well. However, the present invention is not limited to this, and a pair of P-type MOS transistor Pn and N-type MOS transistor Nn constituting each set is formed in a P well 3 as a first well formed separately for each set. In addition, the P-type MOS transistor Pn can be formed in the N well 2 as the second well formed in the P well 3 as the first well.

  Thus, the P-channel and N-channel P-type MOS transistor Pn and the N-type MOS transistor Nn are paired, and one MOS transistor has a double well structure called a second well formed in the first well. When it is provided inside, the entire occupied area can be reduced, and the demand for miniaturization can be met. Further, in the case of this structure, it is possible to reduce the number of driving wirings as compared with the prior art by making good use of the characteristic that the voltage that is ON at P / N is reversed. Specifically, the number of gate signal lines can be halved compared to the conventional number. Therefore, it is possible to contribute to simplification and miniaturization of the circuit.

  In the present embodiment, the source potential of the PMOS source 11 of the P-type MOS transistor Pn is formed to be the same as that of the N-well 2 as the first well, and the NMOS source of the N-type MOS transistor Nn. The source potential 21 is the same as that of the P well 3 as the second well.

  Thereby, the drive voltage of the P-type MOS transistor Pn and the N-type MOS transistor Nn can be reliably reduced. As a result, the installation area of the P-type MOS transistor Pn and the N-type MOS transistor Nn can be reduced, so that the circuit scale can be greatly reduced and the fine digital-analog converter 10 can be provided.

  In the present embodiment, the PMOS well 11 and the PMOS drain 12 of the P-type MOS transistor Pn and the N-type high concentration diffusion layer 9 are formed in the N-well 2, and the PMOS source 11 and the N-type high-concentration layer 9 are formed. The wiring layer 14 is electrically connected to the concentration diffusion layer 9. Also, the NMOS source 21 and the NMOS drain 22 of the N-type MOS transistor Nn and the P-type high concentration diffusion layer 5 are formed in the P well 3, and the NMOS source 21 and the P-type high concentration diffusion layer 5 are The wiring pattern 15 is electrically connected. Thereby, the source potential of the PMOS source 11 and the N well 2 can be surely set to the same potential, and the source potential of the NMOS source 21 and the P well 3 can be reliably set to the same potential.

  In the present embodiment, the first well is the N well 2, and the P-type MOS transistor Pn is formed in the N well 2. The second well is a P well 3, and an N-type MOS transistor Nn is formed in the P well 3.

  Therefore, with the configuration of the present embodiment, a pair of P-type MOS transistor Pn and N-type MOS transistor Nn formed separately for each group can be easily manufactured as in the conventional case.

  Further, in the present embodiment, each P-type MOS transistor Pn and N-type MOS transistor Nn applies a voltage from each connection point of a plurality of resistors Rm connected in series in order from a lower bit in a predetermined digital value. The analog voltage corresponding to a predetermined digital value is output by selecting by switching with the MOS transistor Pn and the N-type MOS transistor Nn. As a result, it is possible to employ a general method of selecting from the lower bits in the fine digital-analog converter 10 with a reduced circuit scale.

  In the digital-analog converter 10 according to the present embodiment, a combination of a P-type MOS transistor Pn and an N-type MOS transistor Nn is combined into a well Wn (n is the number in the present embodiment). Although it formed in 1-7) in the form, it does not necessarily restrict to this.

  That is, for example, as in the prior art, all transistors can be constituted by N-type MOS transistors Nn, and the P-wells 3 for forming the N-type MOS transistors Nn can be formed independently of each other. Further, in this case, all the transistors can be constituted by the P-type MOS transistor Pn, and the N well 2 when the P-type MOS transistor Pn is formed can be formed independently of each other.

  In the case of such well-separated N-type MOS transistor Nn and P-type MOS transistor Pn, the drive voltage of each N-type MOS transistor Nn and P-type MOS transistor Pn is lowered by the amount corresponding to the absence of the back gate bias effect. Thus, the transistor size can be reduced, and the driving capability of the N-type MOS transistor Nn and the P-type MOS transistor Pn can be improved.

  Therefore, the circuit scale can be reduced and reduced by reducing the drive voltage of the N-type MOS transistor Nn and the P-type MOS transistor Pn and reducing the transistor size without lowering the VDD voltage by devising the well structure and the circuit. A digital-to-analog converter 10 can be provided.

  Further, in this case, the source potential of each N-type MOS transistor Nn is formed to be the same potential as that of the P well 3, or the source potential of the P-type MOS transistor Pn is formed to be the same potential as that of the N well 2. .

  That is, by adopting the well-separated N-type MOS transistor Nn or P-type MOS transistor Pn, the source potential of each N-type MOS transistor Nn or P-type MOS transistor Pn can be set to the same potential as the well. it can. Then, by making the source potential of each N-type MOS transistor Nn or P-type MOS transistor Pn the same as that of the well, the drive voltage of the N-type MOS transistor Nn and the P-type MOS transistor Pn can be reduced. As a result, the installation area of the N-type MOS transistor Nn and the P-type MOS transistor Pn can be reduced, so that the circuit scale can be greatly reduced and the fine digital-analog converter 10 can be provided.

  In this case, the NMOS source 21 and the NMOS drain 22 of the N-type MOS transistor Nn and the P-type high concentration diffusion layer 5 are formed in the P well 3, and the NMOS source 21 and the P-type high concentration diffusion layer are formed. 5 can be electrically connected by a conductor such as the wiring pattern 15 or the like. In the N well 2, a PMOS source 11 and a PMOS drain 12 of the P-type MOS transistor Pn and an N-type high concentration diffusion layer 9 are formed, and the PMOS source 11 and the N-type high concentration diffusion layer 9 are It is possible to electrically connect with a conductor such as the wiring pattern 14. This ensures that the source potential and the well are the same potential.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIG. Configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanation thereof is omitted.

  Whereas the digital-analog converter 10 of the first embodiment is a circuit system that selects from the lower bits, the digital-analog converter 30 of the present embodiment selects from the upper bits as shown in FIG. It is a circuit system.

  That is, in the digital-analog converter 30 of the present embodiment, as shown in the figure, the connection point between the series-connected resistors R11 and R12 is connected to the NMOS source 21 of the N-type MOS transistor N11. The connection point between the resistor R12 and the resistor R13 connected in series is connected to the NMOS source 21 of the N-type MOS transistor N12, and the connection point between the resistor R13 and the resistor R14 connected in series is N A connection point between the resistor R14 and the resistor R15 connected in series to the NMOS source 21 of the type MOS transistor N13 is connected to the NMOS source 21 of the N type MOS transistor N14. That is, the connection point of the lower level resistor connected in series is connected to the NMOS source 21 of the N-type MOS transistors N11 to N14, and the connection point of the upper level resistor connected in series is the PMOS of the P-type MOS transistors P11 to P14. Connected to the source 11.

  The NMOS drain 22 of the N-type MOS transistor N11 and the PMOS drain 12 of the P-type MOS transistor P11 are connected to the NMOS source 21 of the N-type MOS transistor N15, and the NMOS drain 22 and the P-type of the N-type MOS transistor N12. The PMOS drain 12 of the MOS transistor P12 is connected to the NMOS source 21 of the N-type MOS transistor N16, and the NMOS drain 22 of the N-type MOS transistor N13 and the PMOS drain 12 of the P-type MOS transistor P13 are P-type MOS transistors. The NMOS drain 22 of the N-type MOS transistor N14 and the PMOS drain 12 of the P-type MOS transistor P14 connected to the PMOS source 11 of P15 are connected to the P-type MOS transistor P. It is connected to the PMOS source 11 of 6.

  Similarly, the output of the lower level resistor is connected to the NMOS source 21 of the N-type MOS transistors N15 and N16, and the output of the upper level resistor is connected to the PMOS source 11 of the P-type MOS transistors P15 and P16. .

  Further, the NMOS drain 22 of the N-type MOS transistor N15 and the PMOS drain 12 of the P-type MOS transistor P15 are connected to the NMOS source 21 of the N-type MOS transistor N17, and the NMOS drain 22 and the P-type of the N-type MOS transistor N16. The PMOS drain 12 of the MOS transistor P16 is connected to the NMOS source 21 of the P-type MOS transistor P17.

  The NMOS drain 22 of the N-type MOS transistor N17 and the PMOS drain 12 of the P-type MOS transistor P17 are connected to the output OUT.

  Further, the control signal IN11 is input to the gate electrodes 7 of the N-type MOS transistors N11 to N14 and the P-type MOS transistors P11 to P14 via the inverter INV11. The control signal IN12 is input to the gate electrodes 7 of the N-type MOS transistors N15 and N16 and the P-type MOS transistors P15 and P16 via the inverter INV12. The control signal IN13 is input to the gate electrodes 7 of the N-type MOS transistor N17 and the P-type MOS transistor P17 via the inverter INV13.

  Other configurations are the same as those of the digital-analog converter 10 of the first embodiment.

  A method for extracting the drive voltage in the digital-analog converter 30 having the above configuration will be described.

  For example, in order to extract the drive voltage of VDD × 7/9 from the output OUT with the digital analog converter 30, the control signals IN11, IN12, and IN13 are set to (1, 1, 0) as shown in Table 3. To do.

  As a result, first, as shown in FIG. 4, the control signal IN11 “1” is inverted by the inverter INV11 to become “0”, the P-type MOS transistors P11 to P14 are turned on, and the N-type MOS transistors N11 to N14 are turned on. Is turned off. As a result, VDD × 5/9 is output from the P-type MOS transistor P11 and input to the N-type MOS transistor N15, and VDD × 7/9 is output from the P-type MOS transistor P13 to output the P-type MOS transistor. Input to P15. Further, VDD × 6/9 is output from the P-type MOS transistor P12 and input to the N-type MOS transistor N16, and VDD × 8/9 is output from the P-type MOS transistor P14 to output the P-type MOS transistor P16. Is input.

  Next, the control signal IN12 “1” is inverted by the inverter INV12 to become “0”, the P-type MOS transistors P15 and P16 are turned on, and the N-type MOS transistors N15 and P16 are turned off. As a result, VDD × 7/9 is output from the P-type MOS transistor P15 and input to the N-type MOS transistor N7, and VDD × 8/9 is output from the P-type MOS transistor P16 to output the P-type MOS transistor. Input to P17.

  Next, the control signal IN13 “0” is inverted by the inverter INV13 to become “1”, the N-type MOS transistor N17 is turned on, and the P-type MOS transistor P17 is turned off. As a result, VDD × 7/9 is output from the N-type MOS transistor N17, and VDD × 7/9 is output from the output OUT.

  On the other hand, when VDD × 7/9 is extracted from the output OUT described above, in the present embodiment, the source potential of the NMOS source 21 and the P well 3 in the N-type MOS transistor Nn are at the same potential, and P The source potential of the PMOS source 11 and the N well 2 in the type MOS transistor Pn are at the same potential.

  For this reason, the drive voltage of the P-type MOS transistors P11 to P14 is zero. The drive voltage of the N-type MOS transistors N11 to N14 is VDD × 4/9 by the following calculation.

N-type MOS transistor N11: VDD × 5 / 9−VDD × 1/9 = VDD × 4/9
N-type MOS transistor N12: VDD × 6 / 9−VDD × 2/9 = VDD × 4/9
N-type MOS transistor N13: VDD × 7 / 9−VDD × 3/9 = VDD × 4/9
N-type MOS transistor N14: VDD × 8 / 9−VDD × 4/9 = VDD × 4/9
Next, the drive voltage of the P-type MOS transistors P15 and P16 becomes zero. Further, the drive voltage of the N-type MOS transistors N15 and N16 is VDD × 2/9 by the following calculation.

N-type MOS transistor N15: VDD × 7 / 9−VDD × 5/9 = VDD × 2/9
N-type MOS transistor N16: VDD × 8 / 9−VDD × 6/9 = VDD × 2/9
Next, the drive voltage of the N-type MOS transistor N17 becomes zero. The drive voltage of the P-type MOS transistor P17 is VDD × 1/9 by the following calculation.

P-type MOS transistor P17: VDD × 8 / 9−VDD × 7/9 = VDD × 1/9
In summary, the driving voltages of the N-type MOS transistor Nn and the P-type MOS transistor Pn are as shown in Table 3.

  Similarly, when other voltages are taken out, the voltages shown at the output OUT in Table 3 can be taken out by setting the control signals IN11, IN12, and IN13 as shown in Table 3. Further, the driving voltages of the respective N-type MOS transistors Nn and P-type MOS transistors Pn at that time are as shown in Table 3.

  Therefore, in this digital analog converter 30, the voltage applied to the N-type MOS transistor Nn and the P-type MOS transistor Pn has a drain-well voltage (VDB) of VDD × 1/9 to VDD × 4/9, Compared to VDD × 8/9 in the prior art, the voltage value is reduced to ½.

  In the digital-analog converter 30 according to the present embodiment, a combination of a P-type MOS transistor Pn and an N-type MOS transistor Nn is combined into a well Wn (n is the number of the present embodiment) separated for each set. Although it formed in 1-7) in the form, it does not necessarily restrict to this.

  That is, for example, as in the prior art, all transistors can be constituted by N-type MOS transistors Nn, and the P-wells 3 for forming the N-type MOS transistors Nn can be formed independently of each other. Further, in this case, all the transistors can be constituted by the P-type MOS transistor Pn, and the N well 2 when the P-type MOS transistor Pn is formed can be formed independently of each other.

  As described above, in the digital-analog converter 30 according to the present embodiment, each P-type MOS transistor Pn and N-type MOS transistor Nn is connected to a plurality of resistors Rm connected in series in order from the upper bit in a predetermined digital value. A voltage from the point is selected by switching by each P-type MOS transistor Pn and N-type MOS transistor Nn, and an analog voltage corresponding to a predetermined digital value is output.

  In the case of such a method of selecting from the upper bits, since the lower bits are the final stage, it is possible to finally output the voltage with the minimum resolution of the voltage value divided by the resistance. That is, it is possible to further increase the resolution (gradation) using this output.

  The present invention relates to a digital-to-analog converter (DAC) used in a MOS integrated circuit, and in particular, outputs from series-connected resistance elements and connection points of the resistance elements. The present invention can be applied to a digital / analog converter having a switch element using a MOS transistor for selecting an arbitrary potential, a display element driving apparatus for driving a plurality of display elements, and the display element using the digital / analog converter For example, the display device can be used in an active matrix liquid crystal display device, an electrophoretic display, a twist ball display, and a fine prism film. Such as reflective displays and digital mirror devices In addition to a display using a modulation element, as a light emitting element, an organic EL light emitting element, an inorganic EL light emitting element, a display using a variable light emitting luminance element such as an LED (Light Emitting Diode), a field emission display (FED), plasma It can also be used for displays.

It is a circuit diagram showing one embodiment of a digital analog converter in the present invention. 2 is a plan view showing a pair of a P-type MOS transistor and an N-type MOS transistor in the digital-analog converter. FIG. 2A shows the P-type MOS transistor, and is a cross-sectional view taken along the line AA in FIG. 2, and FIG. 2B shows the N-type MOS transistor, and shows a line BB in FIG. It is line sectional drawing. It is a circuit diagram which shows other embodiment of the digital analog converter in this invention. It is a circuit diagram which shows the conventional digital analog converter. It is an interphase figure which shows the relationship between the drive voltage of a MOS transistor, and a transistor area.

Explanation of symbols

1 P substrate (substrate)
2 N well (first well)
3 P well (second well)
4 Double well structure 5 P-type high concentration diffusion layer (electrode terminal, second electrode terminal)
7 Gate electrode 9 N-type high concentration diffusion layer (electrode terminal, first electrode terminal)
10 Digital-analog converter 11 PMOS source (source electrode, first source electrode)
12 PMOS drain 14 Wiring pattern 15 Wiring pattern 21 NMOS source (source electrode, second source electrode)
22 NMOS drain IN1-3 control signal IN11-13 control signal INV1-3 inverter INV11-13 inverter Nn N-type MOS transistor OUT output Pn P-type MOS transistor Rm resistance Wn well (first well)

Claims (9)

On the surface of the substrate, a plurality of resistors connected in series and a MOS transistor as a plurality of switch elements are formed, and when a predetermined digital value is input, from each connection point of the plurality of resistors connected in series In a digital-analog converter that sequentially selects a voltage by switching by each MOS transistor and outputs an analog voltage corresponding to the predetermined digital value,
Each of the MOS transistors is formed in a well formed separately, and the well potential can be individually set.   2. The digital-analog converter according to claim 1, wherein the source potential of each MOS transistor is formed to be the same potential as the well. In the well, a source electrode and a drain electrode of the MOS transistor and an electrode terminal are formed, and
3. The digital analog converter according to claim 1, wherein the source electrode and the electrode terminal are electrically connected by a conductor. On the surface of the substrate, a plurality of resistors connected in series and a MOS transistor as a plurality of switch elements are formed, and when a predetermined digital value is input, from each connection point of the plurality of resistors connected in series In a digital-analog converter that sequentially selects a voltage by switching by each MOS transistor and outputs an analog voltage corresponding to the predetermined digital value,
A pair of P-type MOS transistor and N-type MOS transistor constituting each set is formed in a first well formed separately for each set, and
Any one of the P-type MOS transistor and the N-type MOS transistor is formed in a second well formed in the first well. The first source potential of either the P-type MOS transistor or the N-type MOS transistor is formed to be the same potential as the first well,
5. The digital-analog converter according to claim 4, wherein the second source potential of the other of the P-type MOS transistor and the N-type MOS transistor is formed to be the same potential as the second well. In the first well, a first source electrode, a first drain electrode, and a first electrode terminal of either the P-type MOS transistor or the N-type MOS transistor are formed, and the first source electrode The first electrode terminal is electrically connected by a conductor,
In the second well, a second source electrode, a second drain electrode, and a second electrode terminal of the other of the P-type MOS transistor and the N-type MOS transistor are formed, and the second source electrode 6. The digital-analog converter according to claim 4, wherein the second electrode terminal is electrically connected by a conductor. The first well is an N well, a P-type MOS transistor is formed in the N well, and
7. The digital-analog converter according to claim 5, wherein the second well is a P-well, and an N-type MOS transistor is formed in the P-well.   Each of the MOS transistors selects the voltage from each connection point of the plurality of resistors connected in series in order from the lower bit in the predetermined digital value by switching by the MOS transistor, and the predetermined digital value 8. The digital-to-analog converter according to claim 1, wherein an analog voltage corresponding to is output.   Each of the MOS transistors selects the voltage from each connection point of the plurality of resistors connected in series in order from the upper bit in the predetermined digital value by switching by the MOS transistor, and the predetermined digital value 8. The digital-to-analog converter according to claim 1, wherein an analog voltage corresponding to is output.

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