JP2006180033A - Level shifter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shifter circuit realizing cost reduction while reducing the size of a transistor at the input stage. <P>SOLUTION: The level shifter circuit converts a signal operating with a low voltage power supply into a signal operating with a high voltage power supply on the negative side. A first low breakdown voltage NMOS, a first high breakdown voltage PMOS, sixth and third high breakdown voltage NMOS and second low breakdown voltage NMOS, a second high breakdown voltage PMOS, fifth and fourth high breakdown voltage NMOS are connected, respectively, in series between the high potential of the low voltage power supply and the low potential of the high voltage power supply on the negative side. Gates of the first and second low breakdown voltage NMOS are connected, respectively, with the signal operating with the low voltage power supply and its inverted signal and its substrate is connected with the low potential of the low voltage power supply. Gates of the first and second high breakdown voltage PMOS are connected with a bias signal and its substrate is connected with the high potential of the low voltage power supply. The signal operating with the high voltage power supply on the negative side and its inverted signal are outputted, respectively, from the drain of the first and second high breakdown voltage PMOS. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a level shifter circuit that converts a low-voltage signal into a positive-side and negative-side high-voltage signal.

  For example, in a circuit that operates with a positive and negative high-voltage power supply other than a low-voltage power supply VDD-VSS for a logic circuit, such as a liquid crystal driver, the voltage range of the low-voltage power supply for the logic circuit A circuit that shifts the level of an operating signal to a signal that operates in the voltage range of the high-voltage power supply on the positive side and the negative side is required. At that time, in the case of a configuration requiring many level shifter circuits, the size becomes a very important problem in terms of cost.

  FIG. 4 is a circuit diagram showing an example of a configuration of a conventional level shifter circuit. The level shifter circuit 30 shown in FIG. 1 is configured to use signals IN and XIN operating at a low voltage power supply VDD (high potential) -VSS (low potential) as a positive high voltage power supply VH (high potential) -VSS (low potential). ) To operate signals OUT and XOUT. The input stage high breakdown voltage N-type MOS transistors (hereinafter referred to as NMOS) 22a and 22b and the high breakdown voltage P-type MOS transistor (hereinafter referred to as PMOS). 24a and 24b.

  Here, the signals IN and XIN are input to the gates of the NMOSs 22a and 22b, respectively, and their sources are connected to the power supply VSS. The gates of the PMOSs 24a and 24b are connected to the internal nodes B and A, respectively, their sources are connected to the power supply VH, and their drains are connected to the drains of the NMOSs 22a and 22b, respectively. Signals XOUT and OUT are output from the internal nodes A and B, respectively.

  In the following description, the power supply VH> the power supply VDD> the power supply VSS, the high level of the signals IN and XIN is the power supply VDD, the low level is the potential of the power supply VSS, the high levels of the signals OUT and XOUT are the power supply VH, and the low level is the power supply. This is the potential of VSS.

  In the level shifter circuit 30, when the signal IN is at a high level and the inverted signal XIN is at a low level, the NMOS 22a is turned on and the NMOS 22b is turned off. Therefore, the signal XOUT is connected to the power supply VSS via the NMOS 22a and becomes low level. The PMOS 24b is turned on by the low level of the signal XOUT, and the signal OUT is connected to the power supply VH via the PMOS 24b and becomes the high level. The PMOS 24a is turned off by the high level of the signal OUT.

  Subsequently, when the signal IN is at a low level and the signal XIN is at a high level, the NMOS 22a is turned off and the NMOS 22b is turned on. Therefore, the signal OUT is connected to the power supply VSS via the NMOS 22b and becomes low level. The PMOS 24a is turned on by the low level of the signal OUT, and the signal XOUT is connected to the power supply VH via the PMOS 24a and becomes high level. Then, the PMOS 24b is turned off by the high level of the signal XOUT.

  By the way, in the level shifter circuit 30, when the signals IN and XIN change, the PMOS 24a and NMOS 22a, or the PMOS 24b and NMOS 22b are temporarily turned on simultaneously, and a through current flows from the power supply VH to the power supply VSS. For example, when the signal IN changes from the low level to the high level and the signal XIN changes from the high level to the low level, the NMOS 22a is turned on and the NMOS 22b is turned off. At this time, the PMOS 24a is still on and the PMOS 24b is off. .

  Therefore, a through current flows from the power supply VH to the power supply VSS via the PMOS 24a and the NMOS 22a in the on state. In the state where this through current flows, the PMOS 24b is turned on by pulling out the charge of the gate of the PMOS 24b due to the drive capability of the NMOS 22a, and the PMOS 24a is turned off when the signal OUT becomes high level through the PMOS 24b which is turned on. The signal XOUT becomes low level via the NMOS 22a.

  Therefore, in the level shifter circuit 30, it is necessary to increase the drive capability of the NMOSs 22a and 22b in the input stage, that is, the transistor size as the level shift amount (potential difference between VDD and VH) increases. was there.

  A level shifter circuit 32 shown in FIG. 5 improves this problem. In the level shifter circuit 32, in the level shifter circuit 30, a high breakdown voltage type PMOS 26a is provided between the drain of the PMOS 24a and the internal node A, and a high breakdown voltage type PMOS 26b is provided between the drain of the PMOS 24b and the internal node B. Signals IN and XIN are connected to the gates of the PMOSs 26a and 26b, respectively.

  In the level shifter circuit 32, the PMOS 26a is turned off when the signal IN is changed from a low level to a high level and the NMOS 22a is turned on by cascode-connecting the PMOS and inputting the signals IN and XIN to the gates of the PMOSs 26a and 26b, respectively. When the signal XIN changes from low level to high level and the NMOS 22b is turned on, the PMOS 26b is turned off.

  For example, when the signal IN changes from the low level to the high level, the PMOS 26a is not completely turned off because the source is connected to the high voltage power source VH via the PMOS 24a, but the PMOS 26a does not pass through the PMOS 24a, 26a and the NMOS 22a. Can be reduced. For this reason, the drive capability of the NMOSs 22a and 22b of the main input stage can be lowered, and a transistor having a small transistor size can be used.

  The level shifter circuits 30 and 32 are well-known circuits as positive side level shifter circuits. According to this well-known circuit configuration, signals IN and XIN that operate with a low-voltage power supply VDD-VSS are converted into signals OUT and XOUT that operate with a negative high-voltage power supply VDD (high potential) -VL (low potential). The circuit to be replaced has a configuration in which the PMOS and the NMOS are interchanged, and the power supply VH-VSS and the power supply VDD-VL are interchanged. Power supply VH> power supply VDD> power supply VSS> power supply VL.

  For example, the level shifter circuit 34 shown in FIG. 6 operates with the negative high voltage power supply VDD-VL with respect to the level shifter circuit 32 that performs level shift to a signal operating with the positive high voltage power supply VH-VSS. A level shift is performed on the signal. The level shifter circuit 34 includes high-breakdown-voltage input stage PMOSs 13a and 13b, high-breakdown-voltage NMOSs 16a and 16b, and high-breakdown-voltage NMOSs 18a and 18b.

  In addition, the level shifter circuit shown in FIG. 7 changes from a signal operating with the low voltage power supply VDD-VSS to a signal operating with the positive and negative high voltage power supplies VH (high potential) -VL (low potential). A shift is performed. The level shifter circuit shown in FIG. 7 receives signals OUT and XOUT output from the level shifter circuit 34 as signals IN and XIN of the level shifter circuit 32, and is level-shifted from the level shifter circuit 32 to high voltages on the positive side and negative side. The signals OUT and XOUT are output.

  In the level shifter circuit shown in FIG. 7, the sources of the NMOSs 22a and 22b in the input stage of the level shifter circuit 32 are connected not to the power source VSS but to the lowest potential VL.

  In the circuit that shifts the level to the positive side and the negative side, as in the level shifter circuit shown in FIG. 7, the negative level shifter circuit 34 causes the signals IN and XIN that operate with the low-voltage power supply VDD-VSS to After converting the signal to operate with the voltage power supply VDD-VL, the positive level shifter circuit 32 converts the signal operating with the negative high voltage power supply VDD-VL to the positive and negative high voltage power supplies. It is necessary to convert to signals OUT and XOUT operating at VH-VL.

  The reason is as follows. For example, when the high-breakdown-voltage type NMOS 22a is manufactured on a P substrate, the substrate potential is set to the potential of the lowest negative high-voltage power supply VL so that the PN junction is not forward. The Accordingly, if the substrate potential of the NMOS 22a is VL and the source potential thereof is VSS, the substrate potential is lower than the source potential, so that the threshold voltage of the NMOS 22a becomes higher due to the influence of the back gate bias.

  Therefore, the order of the positive-side level shifter circuit 32 and the negative-side level shifter circuit 34 is switched. First, the positive-side level shifter circuit 32 converts the signals IN and XIN operating at the low voltage power supply VDD-VSS to the positive level. If conversion is made to a signal that operates with the high-voltage power supply VH-VSS on the side, the operation cannot be performed if the threshold voltage of the NMOS 22a is higher than the potentials of the signals IN and XIN. For this reason, it is necessary to shift the level to the negative side first.

  Therefore, in the case of a circuit that performs level shift to a negative high voltage or a positive high voltage and a negative high voltage, the main input stage transistor is a high breakdown voltage type PMOS. Normally, the PMOS has a lower mobility than the NMOS, so that even if a cascode-connected NMOS is added, the transistor size needs to be considerably increased. Therefore, in the case of a circuit that requires a large number of level shifter circuits, there is a problem that the chip size is increased and the cost is increased.

  An object of the present invention is to provide a level shifter circuit that eliminates the problems associated with the prior art, reduces the size of the transistors in the input stage, and realizes cost reduction.

In order to achieve the above object, the present invention is a negative level shifter circuit that converts a signal operating with a low voltage power source into a signal operating with a negative high voltage power source,
The gate is connected to the signal operating with the low voltage power supply and the inverted signal thereof, the drain is connected to the high potential of the low voltage power supply, and the substrate is connected to the low potential of the low voltage power supply. First and second low breakdown voltage N-type MOS transistors;
The gate is connected to a bias signal for biasing the sources of the first and second low-breakdown-voltage N-type MOS transistors to a potential equal to or higher than the low potential of the low-voltage power supply. First and second high-breakdown-voltage P-type MOS transistors each connected to the source of a second low-breakdown-voltage N-type MOS transistor and whose substrate is connected to the high potential of the low-voltage power supply;
Third and fourth high-voltage transistors having gates connected to the drains of the second and first high-voltage P-type MOS transistors, respectively, and sources connected to the low potential of the negative high-voltage power source. A breakdown voltage type N-type MOS transistor;
Its gate is connected to the signal operating with the low voltage power supply and its inverted signal, its source is connected to the drains of the fourth and third high voltage N-type MOS transistors, and its drain is said And fifth and sixth high breakdown voltage N-type MOS transistors connected to the drains of the second and first high breakdown voltage P-type MOS transistors, respectively.
Provided is a level shifter circuit characterized in that a signal operating with the negative high-voltage power supply and its inverted signal are respectively output from the drains of the first and second high-breakdown-voltage P-type MOS transistors. Is.

Further, the present invention is a level shifter circuit that converts a signal that operates with a low-voltage power supply into a signal that operates with a positive-side and negative-side high-voltage power supply,
The negative side level shifter circuit according to claim 1 and the signal operating from the negative side high voltage power source output from the negative side level shifter circuit operate from the positive side and negative side high voltage power sources. And a positive level shifter circuit for converting the signal,
The positive level shifter circuit is
The gate is connected to the negative side high voltage power source output from the negative side level shifter circuit and its inverted signal, and the source is connected to the low potential of the negative side high voltage power source. Seventh and eighth high-breakdown-voltage N-type MOS transistors,
Third and fourth Ps whose gates are connected to the drains of the seventh and eighth high-breakdown-voltage N-type MOS transistors, respectively, and whose sources are connected to the high potential of the high-voltage power supply on the positive side. Type MOS transistor;
The gate is connected to a signal operating from the negative high voltage power source output from the negative level shifter circuit and its inverted signal, and its source is the drain of the fourth and third P-type MOS transistors. High breakdown voltage type fifth and sixth P-type MOS transistors each connected to the drains of the seventh and eighth high breakdown voltage type N-type MOS transistors, respectively.
A level shifter circuit characterized in that a signal operating with the positive and negative high voltage power supplies and an inverted signal thereof are respectively output from the drains of the eighth and seventh high breakdown voltage N-type MOS transistors. I will provide a.

  A low-breakdown-voltage N-type MOS transistor has a higher mobility and a higher drive capability than a high-breakdown-voltage P-type MOS transistor, so that the transistor size can be reduced. Further, since the main input stage transistor is a low-breakdown-voltage N-type MOS transistor having a large drive capability, the transistor size of the bias P-type MOS transistor cascode-connected thereto can also be reduced.

  Therefore, according to the present invention, the layout size of each level shifter circuit can be greatly reduced. Further, in a chip using a large number of level shifter circuits, the chip size can be reduced and the cost can be reduced.

  Hereinafter, a level shifter circuit of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

  FIG. 1 is a circuit diagram of an embodiment showing a configuration of a level shifter circuit of the present invention. The level shifter circuit 10 shown in FIG. 1 operates by using signals IN and XIN operating at a low voltage power supply VDD (high potential) −VSS (low potential) as a negative high voltage power supply VDD (high potential) −VL (low potential). ), Which operate in the input stage, low breakdown voltage type NMOS 12a, 12b, high breakdown voltage type PMOS 14a, 14b, high breakdown voltage type NMOS 16a, 16b, high breakdown voltage type NMOS 18a, 18b.

  The level shifter circuit 10 shown in FIG. 1 is obtained by applying the present invention to the conventional level shifter circuit 34 shown in FIG. 6. The main difference between the two is the high withstand voltage type PMOS 13a, 13b of the input stage shown in FIG. Instead of this, the low breakdown voltage type NMOSs 12a and 12b and the high breakdown voltage type PMOSs 14a and 14b shown in FIG. 1 are used. Components other than the above are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the level shifter circuit 10, the gates of the NMOSs 12a and 12b are connected to the signals IN and XIN, their drains are connected to the power supply VDD, and their substrates are connected to the power supply VSS. The PMOSs 14a and 14b are connected between the sources of the NMOSs 12a and 12b and the drains of the NMOSs 18a and 18b, respectively, their gates are connected to the bias signal BIAS, and their substrates are connected to the power supply VDD.

  In the level shifter circuit 10, the NMOSs 12a and 12b in the input stage have a source follower structure. Therefore, the gates of the cascode-connected NMOSs 18a and 18b are inverted from the level shifter circuit 34 shown in FIG. 6 and connected to the signals XIN and IN, respectively, and the signals OUT and XOUT are also different from the level shifter circuit 34 shown in FIG. Inverted and output from internal nodes C and D, respectively.

  In the level shifter circuit 10, the PMOSs 14a and 14b have the sources of the NMOSs 12a and 12b always equal to or higher than the power supply VSS so as not to exceed the voltage range of the low voltage power supply VDD-VSS that is the withstand voltage range of the low breakdown voltage type NMOSs 12a and 12b. It is biased to be a potential.

  The bias signal BIAS is generated by, for example, the circuit of FIG. The bias generation circuit 20 shown in FIG. 2 includes a high voltage type PMOS 28 and a constant current source 29. The gate of the PMOS 28 is connected to the drain, and its source and substrate are connected to the power supply VSS. The constant current source 29 is connected between the drain of the PMOS 28 and the power supply VL. The bias signal BIAS is output from the drain of the PMOS 28.

  In the bias generation circuit 20, when a constant current source 29 causes a predetermined constant current to flow from the power supply VSS to the power supply VL, the potential VSS of the bias signal BIAS is lower than the power supply VSS by the threshold voltage Vth of the PMOS 28. It is fixed at a potential of −Vth.

  When the potential VSS-Vth is input as the bias signal BIAS in the level shifter circuit 10, the PMOSs 14a and 14b bias the sources of the NMOSs 12a and 12b to the power supply VSS, respectively. For example, when IN is at the VDD level, the NMOS 12a is deeply biased to raise the source potential of the PMOS 14a and its own source potential. Therefore, both the NMOS 12a and the PMOS 14a are deeply biased, and the point C potential is raised by flowing a current. On the other hand, since XIN on the NMOS 12b side is at the VSS level, it is turned off and no current flows, and the source of the NMOS 12b holds the vicinity of the VSS potential. For this reason, the sources of the NMOSs 12a and 12b are always held at a potential equal to or higher than the power supply VSS.

  2 shows an example of a circuit that generates the bias signal BIAS, and the bias generation circuit used in the level shifter circuit of the present invention is not limited to that shown in FIG. Various configurations having similar functions can be used. One bias generation circuit 20 may be provided for each level shifter circuit 10 or only one for a plurality of level shifter circuits 10.

  Next, the operation of the level shifter circuit 10 will be described.

  In the following description, the power supply VDD> the power supply VSS> the power supply VL, the high level of the signals IN and XIN is the power supply VDD, the low level is the potential of the power supply VSS, the high levels of the signals OUT and XOUT are the power supply VDD, and the low level is the power supply. This is the potential of VL.

  In the level shifter circuit 10, when the signal IN is at a high level and the inverted signal XIN is at a low level, the NMOSs 12a and 18b are turned on and the NMOSs 12b and 18a are turned off. Therefore, the signal OUT is raised to the vicinity of the power supply VDD via the NMOS 12a and the PMOS 14a and becomes high level. The NMOS 16b is turned on by the high level of the signal OUT, and the signal XOUT is connected to the power supply VL via the NMOSs 16b and 18b and becomes the low level. The NMOS 16a is turned off by the low level of the signal XOUT.

  Subsequently, when the signal IN is at a low level and the signal XIN is at a high level, the NMOSs 12a and 18b are turned off and the NMOSs 12b and 18a are turned on. Therefore, the signal XOUT is raised to the vicinity of the power supply VDD via the NMOS 12b and the PMOS 14b and becomes high level. The NMOS 16a is turned on by the high level of the signal XOUT, and the signal OUT is connected to the power source VL via the NMOSs 16a and 18a and becomes the low level. Then, the NMOS 16b is turned off by the low level of the signal OUT.

  Next, a level shifter circuit that performs a level shift from a signal that operates with a low-voltage power supply VDD-VSS to a signal that operates with a positive-side and negative-side high-voltage power supply VH-VL will be described.

  The level shifter circuit shown in FIG. 3 uses signals IN and XIN operating with a low voltage power supply VDD (high potential) −VSS (low potential) as a positive and negative high voltage power supply VH (high potential) −VL ( Signal OUT, XOUT output from the negative level shifter circuit 10 shown in FIG. 1 is converted into signals XIN, XIN, of the positive level shifter circuit 32 shown in FIG. The signal is input as IN, and the level shifter circuit 32 outputs signals OUT and XOUT level-shifted to high voltages on both the positive and negative sides.

  The level shifter circuit shown in FIG. 3 is obtained by applying the present invention to the conventional level shifter circuit shown in FIG. 7. The main difference between the two is that the level shifter circuit 10 is used instead of the level shifter circuit 34. It is. As described above, the level shifter circuit 10 uses the NMOSs 12a and 12b and the PMOSs 14a and 14b instead of the NMOSs 13a and 13b. In the following, the same components are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the level shifter circuit shown in FIG. 3 as well, the sources of the NMOSs 22a and 22b in the input stage of the level shifter circuit 32 are connected to the power supply VL which is the lowest potential instead of the power supply VSS.

  Further, as described above, the signals OUT and XOUT output from the level shifter circuit 10 are opposite to the signals OUT and XOUT output from the level shifter circuit 34. Therefore, in the level shifter circuit shown in FIG. 3, in contrast to the level shifter circuit shown in FIG. 7, the signals OUT and XOUT output from the level shifter circuit 10 are input as the signals XIN and IN of the level shifter circuit 32. The signals OUT and XOUT output from the level shifter circuit 32 shown in FIG. 3 are opposite to the signals OUT and XOUT output from the level shifter circuit 32 shown in FIG.

  The operation of the level shifter circuit 10 is the same as that in FIG. The operation of the level shifter circuit 32 is the same as that shown in FIG. 5 except that reverse signals are input as the signals IN and XIN and reverse signals are output as the signals OUT and XOUT.

  By providing the PMOSs 14a and 14b, the main input stage transistor can be operated in the voltage range of the power supply VDD-VSS, which is the withstand voltage range, so that the low withstand voltage type NMOS 12a is used as the main input stage transistor. 12b can be used.

  The low breakdown voltage type NMOSs 12a and 12b have higher mobility and higher drive capability than the high breakdown voltage type PMOSs 13a and 13b shown in FIG. For this reason, the transistor size of the NMOSs 12a and 12b can be reduced. In addition, since the main input stage transistors are low-breakdown-voltage NMOSs 12a and 12b having a large drive capability, the transistor sizes of the PMOSs 14a and 14b connected to the NMOSs 12a and 12b in cascode can be reduced.

  More specifically, the total transistor size of the NMOSs 12a and 12b and the PMOSs 14a and 14b shown in FIG. 1 is smaller than the total transistor size of the PMOSs 13a and 13b shown in FIG. For example, when compared with a process of 0.35 μm and LV / HV = 3.3V / 18V, the level shifter circuit of the present invention is capable of layout shrinkage of about 40% as compared with the conventional level shifter circuit.

  Therefore, by using the level shifter circuit of the present invention, the layout size of each level shifter circuit can be greatly reduced. As a result, the chip size of a chip using a large number of level shifter circuits can be reduced, and the cost can be reduced.

The present invention is basically as described above.
The level shifter circuit according to the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications and changes may be made without departing from the spirit of the present invention. .

It is a circuit diagram of one embodiment showing composition of a level shifter circuit of the present invention. FIG. 2 is a circuit diagram illustrating a configuration of a bias generation circuit used in the level shifter circuit illustrated in FIG. 1. It is a circuit diagram of another embodiment showing the structure of the level shifter circuit of this invention. It is an example circuit diagram showing the structure of the conventional level shifter circuit. It is a circuit diagram of another example showing the structure of the conventional level shifter circuit. It is a circuit diagram of another example showing the structure of the conventional level shifter circuit. It is a circuit diagram of another example showing the structure of the conventional level shifter circuit.

Explanation of symbols

10, 30, 32, 34 Level shifter circuits 12a, 12b Low breakdown voltage N-type MOS transistors 13a, 13b, 14a, 14b, 24a, 24b, 26a, 26b, 28 High breakdown voltage P-type MOS transistors 16a, 16b, 18a , 18b, 22a, 22b High breakdown voltage type N-type MOS transistor 20 Bias generation circuit 29 Constant current source

Claims (2)

A negative level shifter circuit that converts a signal that operates with a low-voltage power source into a signal that operates with a negative high-voltage power source,
The gate is connected to the signal operating with the low voltage power supply and the inverted signal thereof, the drain is connected to the high potential of the low voltage power supply, and the substrate is connected to the low potential of the low voltage power supply. First and second low breakdown voltage N-type MOS transistors;
The gate is connected to a bias signal for biasing the sources of the first and second low-breakdown-voltage N-type MOS transistors to a potential equal to or higher than the low potential of the low-voltage power supply. First and second high-breakdown-voltage P-type MOS transistors each connected to the source of a second low-breakdown-voltage N-type MOS transistor and whose substrate is connected to the high potential of the low-voltage power supply;
Third and fourth high-voltage transistors having gates connected to the drains of the second and first high-voltage P-type MOS transistors, respectively, and sources connected to the low potential of the negative high-voltage power source. A breakdown voltage type N-type MOS transistor;
Its gate is connected to the signal operating with the low voltage power supply and its inverted signal, its source is connected to the drains of the fourth and third high voltage N-type MOS transistors, and its drain is said And fifth and sixth high breakdown voltage N-type MOS transistors connected to the drains of the second and first high breakdown voltage P-type MOS transistors, respectively.
A level shifter circuit characterized in that a signal operating with the negative high-voltage power supply and its inverted signal are output from the drains of the first and second high-breakdown-voltage P-type MOS transistors, respectively. A level shifter circuit that converts a signal that operates with a low-voltage power source into a signal that operates with a positive-side and negative-side high-voltage power source,
The negative side level shifter circuit according to claim 1 and the signal operating from the negative side high voltage power source output from the negative side level shifter circuit operate from the positive side and negative side high voltage power sources. And a positive level shifter circuit for converting the signal,
The positive level shifter circuit is
The gate is connected to the negative side high voltage power source output from the negative side level shifter circuit and its inverted signal, and the source is connected to the low potential of the negative side high voltage power source. Seventh and eighth high-breakdown-voltage N-type MOS transistors,
Third and fourth Ps whose gates are connected to the drains of the seventh and eighth high-breakdown-voltage N-type MOS transistors, respectively, and whose sources are connected to the high potential of the high-voltage power supply on the positive side. Type MOS transistor;
The gate is connected to a signal operating from the negative high voltage power source output from the negative level shifter circuit and its inverted signal, and its source is the drain of the fourth and third P-type MOS transistors. High breakdown voltage type fifth and sixth P-type MOS transistors each connected to the drains of the seventh and eighth high breakdown voltage type N-type MOS transistors, respectively.
A level shifter circuit characterized in that a signal operating with the positive and negative high voltage power supplies and an inverted signal thereof are respectively output from the drains of the eighth and seventh high breakdown voltage N-type MOS transistors. .

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