JPS6110324A - Digital-analog converting circuit - Google Patents

Abstract

PURPOSE:To decrease the effect of a back gate bias by dividing an MOS transistor (TR) forming a switch circuit for selecting reference voltage into two blocks and impressing a back gate voltage at each block. CONSTITUTION:A voltage Vr is divided into reference voltages V1-V8 by a resistance ladder 2 and each reference voltage is selected by a TR pair. TRs of the least significant bit and the 2nd bit are split into four blocks A-D and the lowest reference voltage selected by each block is used as the back gate voltage. TRs 10, 12, 6, 8 for the most significant bit are not blocked and each input voltage is inputted as a back gate voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a D/A conversion circuit using a MOS transistor as a reference voltage selection switch circuit.

(Prior art) Figure 1 is an example of a D/A conversion circuit with a CMOS configuration.
It converts a 3-bit digital signal into 8 types of analog signals. The voltage Vr is divided into eight types of reference voltages v1 to v8 by the resistor ladder 2, and one of the reference voltages is selected by a switch circuit having an 0MO8 configuration consisting of a pair of NMOS transistors and PMOS transistors.

Generally, a DC bias is applied to the back gate (also called substrate) of the electrodes of a MOS transistor. Conventionally, for NMOS transistors, GND
is taken as the back gate voltage, and for the PMOS transistor, the power supply voltage is taken as the back gate voltage. Therefore, in such an A/A conversion circuit, the reference voltage to be selected differs greatly depending on the position of the MOS transistor.
The back gate bias voltages of the S transistors will also differ greatly.

The following relationship exists between the threshold voltage vth of the MOS transistor and the back gate bias voltage Vbs.

Vt, h=Vth(0)-1-a(T-298)+Bk
(J Kado ■ Ougi - EI) Here, Vth (0): 25 'C Tetrain current is OP
A gate-source voltage (Vgs'), α: temperature coefficient of vth, T: ambient temperature (absolute temperature), Bk22 substrate number Φf: Fermi level.

B1 with mixed bipolar transistor and 0MO8
- In the CMOS process, the substrate constant Bk is NMO
The S transistor is about 10 times larger than the PMOS transistor, and the NMOS transistor is about 10 times larger than the PMOS transistor.
The S transistor is more strongly influenced by the back gate bias voltage.

Returning to Figure 1 again, in the case of an NMO8 transistor whose back gate voltage is set to GND as in the past, for example, in an NMOS transistor which selects a low reference voltage, its back gate bias voltage is small, but a high reference voltage is selected. As the NMOS transistor becomes an NMOS transistor, the absolute value of its back gate bias voltage increases, and the threshold voltage vth also increases. As a result, there is a problem that the on-resistance increases as the NMo5 transistor selects a higher reference voltage, and there is also a problem that the range of selectable reference voltages becomes narrower.

Conversely, in the case of a PMOS transistor, when a high reference voltage is selected, the back gate bias voltage is small, but as a low reference voltage is selected, the absolute value of the back gate bias voltage increases, and the on-resistance increases. It starts to come. Further, in the case of a PMOS transistor, a problem arises as the range of selectable reference voltages becomes narrower.

(Objective) The present invention provides a D/A conversion circuit that reduces the influence of back gate bias voltage, suppresses the increase in threshold voltage, shortens settling time, and allows selection of a wide range of reference voltages. The purpose is to

(Structure) In the D/A conversion circuit of the present invention, the reference voltage selection switch circuit is formed of a MOS transistor.

These MOS transistors are formed on the same semiconductor substrate and are divided into at least 2Il blocks, with a back gate voltage applied to each block.

The present invention will be specifically described below with reference to Examples.

FIG. 1 shows one embodiment, which has a 3-bit 0MO3 configuration in which the voltage Vr is divided into 8 levels of reference voltages V+''Va by a resistor ladder 2, and each reference voltage is selected by a pair of an NMOS transistor and a PMOS transistor. This is an example of an A conversion circuit.

In the NMo5 transistor, the transistors for the least significant bit and the second bit are divided into four blocks A to D, and the lowest reference voltage selected in each block is the back gate voltage of the NMOS transistor belonging to that block. . That is, block A uses reference voltage v2, block B uses reference voltage V4. In block C, the reference voltage v
6. In block D, the reference voltage v8 becomes the back gate voltage.

The same applies to the PMO8 transistor, and the transistors for the least significant bit and the second bit are divided into four blocks EH. However, in this case, unlike the case of NMOS transistors, the highest reference voltage selected in each block is the back gate voltage of the NMo5 transistor belonging to that block. That is, in block E, the reference voltage vl, and in block F, the reference voltage v
3. In the block G, the reference voltage (1) and the like, and in the block H, the reference voltage v7 becomes the back gate voltage.

10 NMO8 transistors for the most significant bit (MSB)
,12. Since the PMOS transistors 6.8 and 6.8 handle voltages in a wide range, their respective input voltages are applied as back gate voltages without being plotted.

Next, the operation of this embodiment will be explained.

Now, a 3-bit digital signal is input and the NMOS
On the transistor side, the NMOS is activated by the first bit signal.
Transistors 14, 16 and 18°20 are turned on, and the NMo5 transistor 22,2 is turned on by the second bit signal.
4 is turned on, the third bit signal turns on the NMO8 transistor 10, and on the PMO8)-transistor side, the first bit signal turns on the PMOS transistors 26, 28, 30, and 32, and the second The PMOS transistors 34 and 36 are turned on by the signal of the 3rd bit, and the PMOS transistor 6 is turned on by the signal of the 3rd bit.
Assume that reference voltage v3 is selected by turning on. At this time, the source voltage of the NMo5 transistor 16.22 is V3. Since the back gate voltage is v4, the bank gate bias voltage is 1/8Vr, the back gate bias voltage is 0 for the NMOS transistor 10, and the source voltage and back gate voltage for the PMOS transistors 28 and 34 are both v3, so the bank gate bias voltage is The gate bias voltage is 0, and even in the PMOS transistor 6, the back gate bias voltage is 0. Therefore, there is almost no increase in the threshold value due to the back gate bias voltage,
The reference voltage v3 can be outputted at high speed with low on-resistance.

A method of blocking IMOS transistors and applying a back gate voltage will be described below.

Regarding the NMOS transistor, if a P-well is formed in the N-type substrate 40 as shown in FIG. 2, and the NMOS transistor is formed in the P-well,
The P well may be divided into 42.44 parts, and a back gate voltage may be applied to each well using the method described above.

For PMOS transistors, for example B1-CMO
If there is a separation step such as the S process, the third
As shown in FIG.
54.56, each epitaxial layer 48.5
The PMOS transistors of each block may be formed at 0, and a back gate voltage may be applied using the method described above.

In addition, in the case of forming both an NMo5 transistor and a PMOS transistor into blocks, for example, as shown in FIG. 4, a part of the N type epitaxial layer on the P type substrate 46 is Separation layer 52,5
4.56, and P-type wells 60 and 62, which are separated from each other, are formed in a portion 58 of the N-type epitaxial layer. And each N-type epitaxial layer 48 divided into one
PMOS transistors of each block are formed at 48° 50, and NMOS transistors of each block are formed in each separated P type well 60, 62, and each epitaxial layer 48° 50 and each well 60, 6 is formed with an NMOS transistor of each block.
2, a back gate voltage may be applied using the method described above.

In the /A conversion circuit as shown in Figure 1, if the selected reference voltage is low, NMO8) - transistor is better than PMOS.
The operating conditions are better than transistors, and conversely, if the selected reference voltage is high, PMOS transistors have better N
Operating conditions are better than MO3 transistors. Therefore, in the figure, for example, the NMOS transistor belonging to block A and the PMOS transistor belonging to block H can be deleted. However, since the switch circuit selected by the most significant bit will handle a wide range of voltages, it is necessary to make sure that both the PMO5)-transistor and the NMo5 transistor can be used.

Although FIG. 1 shows an example of 3 bits, when the number of bits increases to 7 bits or more, reducing the number of transistors greatly contributes to reducing the chip size.

(Effects) According to the present invention, since the influence of the back gate bias voltage is reduced, the settling time from the input of a digital signal to the output of an analog signal in a D/A conversion circuit is shortened. Be able to handle voltage.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention; Fig. 2;
FIGS. 3 and 4 are schematic cross-sectional views each showing a method of dividing a back gate according to the present invention. 2...Resistance ladder, 42, 44, 60.62.
...Divided wells, 48, 50...
Divided epitaxial layer, A-H...blocked MOS transistor.

Claims (2)

[Claims] (1) The reference voltage selection switch circuit is formed of MOS transistors, and these MOS transistors are formed on the same semiconductor substrate, and are divided into at least two blocks, and the back gate voltage is set for each block. A D/A conversion circuit characterized in that a voltage is applied. (2) In a block including NMOS transistors, the lowest voltage among the reference voltages selected by the switch circuit in that block is used as the back gate voltage of the NMOS transistor in that block, and in a block including PMOS transistors, the lowest voltage among the reference voltages selected by the switch circuit in that block is used. The highest voltage among the reference voltages selected in the circuit is set to the PMO of that block.
The D/A conversion circuit according to claim 1, wherein the back gate voltage of the S transistor is used as the back gate voltage.