JP2006222239A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2006222239A
JP2006222239A JP2005033718A JP2005033718A JP2006222239A JP 2006222239 A JP2006222239 A JP 2006222239A JP 2005033718 A JP2005033718 A JP 2005033718A JP 2005033718 A JP2005033718 A JP 2005033718A JP 2006222239 A JP2006222239 A JP 2006222239A
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wiring
wiring board
semiconductor chip
semiconductor device
sealing
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Junichi Shinyashiki
順一 新屋敷
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of certain structure capable of preventing disconnection when a wiring board mounted with a semiconductor chip is sealed up with resin using a sealing mold. <P>SOLUTION: The semiconductor device has a configuration wherein the semiconductor chip 1 is mounted on a printed wiring board 2 and electrically connected to Cu wiring 3 formed on the wiring board 2, and the required area of the wiring board 2 where the semiconductor chip 1 is located is sealed up with a sealing resin 5. A wide part 3a which is as thick as the Cu wiring 3 and long enough in dimension to extend inside and outside the required area is provided to the Cu wiring 3 so as to surround the required area along its boundary. When the printed wiring board 2 is sealed up with resin while being pinched by a sealing mold, pressure applied by the sealing mold is received by the wide part 3a, so that pressure applied on per unit area of the total Cu wiring 3 becomes lower than usual, and the Cu wiring 3 is increased in cross-sectional area and improved in shearing stress-proofness. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、配線基板上に半導体チップを搭載してトランスファーモールド法で樹脂封止した半導体装置およびその製造方法に関するものである。   The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a wiring board and resin-sealed by a transfer molding method, and a manufacturing method thereof.

電子機器に搭載される半導体装置としては、古くはＳＩＰ（Single Inline Package）やＤＩＰ（Dual Inline Package）などの基板挿入型が主に使用されていたが、電子機器の多機能化、小型化に伴い、表面実装型であるＳＯＰ（Small Outline Package）やＱＦＰ（Quad Flat Package）などの半導体装置が主流を占めることとなった。近年では、電子機器の多機能化、小型化の加速により、半導体装置においても多ピン化や高密度実装に対応すべく、ＢＧＡ（Ball Grid Array）型、ＬＧＡ（Land Grid Array）型などの半導体装置が開発され、使用されている。これらＢＧＡ型を始めとする近年の半導体装置は、ＱＦＰなどと異なって特殊な構造が採用されている。   In the past, semiconductor devices mounted on electronic devices were mainly used for board insertion types such as SIP (Single Inline Package) and DIP (Dual Inline Package). Accordingly, semiconductor devices such as SOP (Small Outline Package) and QFP (Quad Flat Package), which are surface mount types, have become the mainstream. In recent years, semiconductor devices such as BGA (Ball Grid Array) type and LGA (Land Grid Array) type have been developed in order to cope with the increase in the number of pins and high-density mounting in semiconductor devices by increasing the functionality and miniaturization of electronic devices. Equipment is being developed and used. Unlike the QFP and the like, recent semiconductor devices such as the BGA type employ a special structure.

図６（ａ）はＢＧＡ型半導体装置の平面図（一部透過図示）、図６（ｂ）は同半導体装置の側面図である。半導体チップ１をプリント配線基板２の片側の面に固着剤を用いて搭載し、半導体チップ１上の接続端子１ａとプリント配線基板２上のＣｕ配線３とを金属ワイヤー４により電気的に接続し、半導体チップ１と金属ワイヤー４とを含んだプリント配線基板２上の所望範囲を封止樹脂５で封止し、プリント配線基板２のもう片側の面に、Ｃｕ配線３にスルーホール６を介して電気的に接続する金属ボール７を形成している（たとえば特許文献１参照）。   FIG. 6A is a plan view (partially transparent) of the BGA type semiconductor device, and FIG. 6B is a side view of the semiconductor device. The semiconductor chip 1 is mounted on one surface of the printed wiring board 2 using an adhesive, and the connection terminals 1a on the semiconductor chip 1 and the Cu wiring 3 on the printed wiring board 2 are electrically connected by the metal wires 4. The desired range on the printed wiring board 2 including the semiconductor chip 1 and the metal wire 4 is sealed with a sealing resin 5, and the Cu wiring 3 is inserted through the through hole 6 on the other surface of the printed wiring board 2. Thus, a metal ball 7 to be electrically connected is formed (see, for example, Patent Document 1).

この種のＢＧＡ型半導体装置の封止工程について説明する。
図７（ａ）は封止金型を示し、１１は上型、１２は下型である。図７（ｂ）に示すように、下型１２の凹部１２ａに、半導体チップ１が搭載され金属ワイヤー４で接続されたプリント配線基板２を設置する。そして、図７（ｃ）に示すように、上型１１と下型１２を閉じ、それにより形成される空房部（キャビティ）１３に対し、図７（ｄ）に示すように、上型１１に形成されたゲート１１ｂを通じて封止樹脂５を注入し、これを硬化させる。 A sealing process of this type of BGA type semiconductor device will be described.
FIG. 7A shows a sealing mold, 11 is an upper mold, and 12 is a lower mold. As shown in FIG. 7B, the printed wiring board 2 on which the semiconductor chip 1 is mounted and connected by the metal wire 4 is installed in the recess 12 a of the lower mold 12. Then, as shown in FIG. 7 (c), the upper mold 11 and the lower mold 12 are closed, and the upper mold 11 as shown in FIG. The sealing resin 5 is injected through the formed gate 11b and cured.

その際に、上型１１と下型１２とで形成される空房部１３に封止樹脂５を注入する金型構造であることから、封止樹脂５が空房部１３から上型１１とプリント配線基板２との境界部に向かって漏れ出す恐れがあり、それを防止するために、プリント配線基板２の表面を上型１１によって強い圧力で押さえ込むようにしている。
特表平１１−５０６２７４ At that time, since the sealing resin 5 is injected into the empty portion 13 formed by the upper die 11 and the lower die 12, the sealing resin 5 is transferred from the empty portion 13 to the upper die 11 and the printed wiring. There is a risk of leakage toward the boundary with the substrate 2, and in order to prevent this, the surface of the printed wiring board 2 is pressed by the upper mold 11 with a strong pressure.
Special table flat 11-506274

しかしながら、上記したような封止工程において、図８（ａ）に示すように、プリント配線基板２の製造上のばらつきでその板厚Ａが下型１２の凹部１２ａの深さＢを上回った場合には、プリント配線基板２を上型１１によって押さえ込むことで、板厚Ａと深さＢとの寸法差Ｃだけプリント配線基板２が押しつぶされることになる。その結果、図８（ｂ）に示すように、プリント配線基板２において、上型１１が接している領域と接していない領域との境界に変形Ｄが発生する。図８（ｃ）に拡大図示すると、プリント配線基板２の表面のＣｕ配線３およびレジストコート８が大きく変形を起こす。変形の大きさによっては、Ｃｕ配線３に無理な負荷が加わり、断線を引き起こしやすい。   However, in the sealing process as described above, when the thickness A exceeds the depth B of the recess 12a of the lower mold 12 due to manufacturing variations of the printed wiring board 2 as shown in FIG. In other words, by pressing the printed wiring board 2 with the upper mold 11, the printed wiring board 2 is crushed by the dimensional difference C between the plate thickness A and the depth B. As a result, as shown in FIG. 8B, in the printed wiring board 2, the deformation D occurs at the boundary between the area where the upper mold 11 is in contact and the area where it is not in contact. When enlarged in FIG. 8C, the Cu wiring 3 and the resist coat 8 on the surface of the printed wiring board 2 are greatly deformed. Depending on the size of the deformation, an unreasonable load is applied to the Cu wiring 3, and disconnection is likely to occur.

本発明は上記問題を解決するもので、半導体チップを搭載した配線基板を封止金型を用いて樹脂封止する際の断線を防止できる構造の半導体装置およびその製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problem, and to provide a semiconductor device having a structure capable of preventing disconnection when a wiring board mounted with a semiconductor chip is resin-sealed using a sealing mold and a method for manufacturing the same. And

上記課題を解決するために、本発明の半導体装置は、半導体チップを配線基板上に搭載し、前記半導体チップの接続端子と配線基板上の配線とを電気的に接続し、前記配線基板上の半導体チップを含んだ所望範囲を封止樹脂で封止した半導体装置において、前記配線基板の半導体チップ搭載面に、前記配線と同等の厚みおよび前記所望範囲の内外にわたる寸法を有する配線パターンを、前記配線と一体にあるいは前記配線から電気的に分離して、前記所望範囲の境界に沿って前記所望範囲を囲むように形成したことを特徴とする。   In order to solve the above problems, a semiconductor device of the present invention includes a semiconductor chip mounted on a wiring board, electrically connecting a connection terminal of the semiconductor chip and a wiring on the wiring board, and In a semiconductor device in which a desired range including a semiconductor chip is sealed with a sealing resin, a wiring pattern having a thickness equivalent to the wiring and a dimension extending in and out of the desired range is formed on the semiconductor chip mounting surface of the wiring board. It is characterized by being formed so as to surround the desired range along a boundary of the desired range, either integrally with the wiring or electrically separated from the wiring.

また本発明の半導体装置の製造方法は、半導体チップを配線基板上に搭載し、前記半導体チップの接続端子と配線基板上の配線とを電気的に接続するボンディング工程と、前記配線基板上の半導体チップを含んだ所望範囲を封止樹脂で封止する封止工程とを行う半導体装置の製造方法において、前記封止工程で、前記配線と同等の厚みおよび前記所望範囲の内外にわたる寸法を有する配線パターンを前記配線と一体にあるいは前記配線から電気的に分離して前記所望範囲の境界に沿って前記所望範囲を囲むように形成した前記配線基板を、前記所望範囲の外側を挟み込むように封止金型内に配置し、この封止金型のキャビティ内に封止樹脂材料を圧入し、成形硬化させることを特徴とする。   According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a bonding step of mounting a semiconductor chip on a wiring board, and electrically connecting a connection terminal of the semiconductor chip and a wiring on the wiring board; and a semiconductor on the wiring board. In a manufacturing method of a semiconductor device which performs a sealing step of sealing a desired range including a chip with a sealing resin, the wiring having a thickness equivalent to the wiring and a dimension extending in and out of the desired range in the sealing step The wiring board formed so as to surround the desired range along the boundary of the desired range by separating the pattern integrally with the wiring or electrically from the wiring is sealed so as to sandwich the outside of the desired range It is arranged in a mold, and a sealing resin material is press-fitted into the cavity of the sealing mold and is molded and cured.

上記各構成によれば、配線基板を封止金型で挟み込んで樹脂封止する際に、所望範囲の内外にわたって延びた配線と配線パターンとで封止金型の圧力を受けることになるため、前記配線パターンが存在しないときに比べて、前記配線の総数に加わる単位面積あたりの圧力が低下し、また配線パターンが配線と一体になっている時にはその一体化配線の断面積が増加し耐せん断応力が向上し、配線基板の変形が起こる圧力下でも前記配線の断線を防止することが可能となる。配線パターンが配線と分離した構造は、配線基板の面積的制約や製品特性の制約などにより前記配線の配置が限られる場合などに有利である。   According to each of the above configurations, when the wiring board is sandwiched between sealing molds and resin-sealed, the pressure of the sealing mold is received by the wiring and the wiring pattern extending over the inside and outside of the desired range. Compared to the case where the wiring pattern does not exist, the pressure per unit area applied to the total number of the wirings is reduced, and when the wiring pattern is integrated with the wiring, the cross-sectional area of the integrated wiring is increased and shear resistance is increased. The stress is improved, and it is possible to prevent the wiring from being disconnected even under pressure that causes deformation of the wiring board. The structure in which the wiring pattern is separated from the wiring is advantageous in the case where the arrangement of the wiring is limited due to the area limitation of the wiring substrate or the product characteristics.

配線と一体になって配線の幅広部を構成している配線パターンと、配線間に電気的に分離して形成された配線パターンとの両方を有していてよい。
配線基板の半導体チップ搭載面に背反する面に、前記半導体チップ搭載面の配線に電気的に接続する外部接続用のランドあるいは金属突起電極を有していてよい。ランドを有するＬＧＡ型半導体装置や金属ボールを有するＢＧＡ型半導体装置に対応する構成である。 You may have both the wiring pattern which is integrated with wiring, and comprises the wide part of wiring, and the wiring pattern formed by electrically isolate | separating between wiring.
On the surface opposite to the semiconductor chip mounting surface of the wiring substrate, an external connection land or metal projection electrode that is electrically connected to the wiring on the semiconductor chip mounting surface may be provided. This is a configuration corresponding to an LGA type semiconductor device having lands and a BGA type semiconductor device having metal balls.

半導体チップと配線基板との電気的接続は、ワイヤーあるいは金属バンプを介して行っていてよい。   The electrical connection between the semiconductor chip and the wiring board may be made through wires or metal bumps.

本発明の半導体装置およびその製造方法は、配線と同等の厚みおよび所望の封止範囲の内外にわたる寸法を有する配線パターンを、配線と一体にあるいは配線から電気的に分離して、前記所望封止範囲の境界に沿って前記所望封止範囲を囲むように形成した前記配線基板を用いるようにしたことで、配線パターンが存在しないときに比べて、前記配線の総数に加わる単位面積あたりの圧力を低下させることができ、また配線パターンが配線と一体になっている時にはその一体化配線の断面積の増加によって耐せん断応力を向上させることができるため、封止金型による押圧力に抗して前記配線の断線を防止可能である。   In the semiconductor device and the manufacturing method thereof according to the present invention, a wiring pattern having a thickness equivalent to a wiring and a dimension extending in and out of a desired sealing range is integrated with the wiring or electrically separated from the wiring, and the desired sealing is performed. By using the wiring board formed so as to surround the desired sealing range along the boundary of the range, the pressure per unit area applied to the total number of the wirings can be reduced as compared with the case where there is no wiring pattern. When the wiring pattern is integrated with the wiring, the shear resistance can be improved by increasing the cross-sectional area of the integrated wiring. It is possible to prevent disconnection of the wiring.

以下、本発明の実施の形態を図面に基づいて説明する。
図１（ａ）は本発明の第１の実施形態における半導体装置の平面図（一部透過図示）、図１（ｂ）は同半導体装置の断面図である。ここではＢＧＡ型半導体装置を示している。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a plan view (partially transparent) of the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view of the semiconductor device. Here, a BGA type semiconductor device is shown.

半導体チップ１をプリント配線基板２の片側の面に固着剤を用いて搭載し、半導体チップ１上の接続端子１ａとプリント配線基板２上のＣｕ配線３とを金属ワイヤー４により電気的に接続し、半導体チップ１と金属ワイヤー４とを含んだプリント配線基板２上の所望範囲を封止樹脂５で封止し、プリント配線基板２のもう片側の面に、Ｃｕ配線３にスルーホール６を介して電気的に接続する金属ボール７を形成している。   The semiconductor chip 1 is mounted on one surface of the printed wiring board 2 using an adhesive, and the connection terminals 1a on the semiconductor chip 1 and the Cu wiring 3 on the printed wiring board 2 are electrically connected by the metal wires 4. The desired range on the printed wiring board 2 including the semiconductor chip 1 and the metal wire 4 is sealed with a sealing resin 5, and the Cu wiring 3 is inserted through the through hole 6 on the other surface of the printed wiring board 2. Thus, a metal ball 7 to be electrically connected is formed.

この半導体装置が従来のものと相違するのは、プリント配線基板２において、半導体チップ１の近傍から上記所望範囲（以下、封止範囲という）の外部にわたって延びた複数のＣｕ配線３のそれぞれに、封止境界部５ａの内外にわたる寸法を有する幅広部３ａが形成されている点である。各幅広部３ａは、封止境界部５ａに沿うように拡がり、且つ封止範囲を囲むように、且つ互いに近接して形成されている。   This semiconductor device is different from the conventional one in the printed wiring board 2 in each of a plurality of Cu wirings 3 extending from the vicinity of the semiconductor chip 1 to the outside of the desired range (hereinafter referred to as a sealing range), A wide portion 3a having a dimension extending inside and outside the sealing boundary portion 5a is formed. Each wide part 3a is formed so as to extend along the sealing boundary part 5a and to surround the sealing range and close to each other.

このため、従来と同様にして半導体装置を製造する際の封止工程で（図７参照）、プリント配線基板２の変形、断線が起こり難い。つまり、図２に示すように、プリント配線基板２を上型１１と下型１２とで挟み込む際に、プリント配線基板２の表面を上型１１によって強い圧力で押さえ込んでも、上型１１が接している領域と接していない領域との境界、すなわち封止境界部５ａのＣｕ配線３には幅広部３ａが存在しているため、幅広部３ａで上型１１の圧力を受けることになり、幅広部３ａがない従来構造に比べて、Ｃｕ配線３の総数に加わる単位面積あたりの圧力が低下し、各Ｃｕ配線３に加わる負荷が低減されるとともに、Ｃｕ配線３の１本あたりの断面積が増加し破断強度が増加するからである。   For this reason, deformation and disconnection of the printed wiring board 2 are unlikely to occur in the sealing step when manufacturing the semiconductor device in the same manner as in the past (see FIG. 7). That is, as shown in FIG. 2, when the printed wiring board 2 is sandwiched between the upper mold 11 and the lower mold 12, even if the surface of the printed wiring board 2 is pressed with a strong pressure by the upper mold 11, the upper mold 11 is in contact. Since the wide part 3a exists in the Cu wiring 3 of the sealing boundary part 5a, that is, the boundary between the existing area and the non-contact area, the wide part 3a receives the pressure of the upper mold 11, and the wide part Compared to the conventional structure without 3a, the pressure per unit area applied to the total number of Cu wirings 3 is reduced, the load applied to each Cu wiring 3 is reduced, and the cross-sectional area per one of the Cu wirings 3 is increased. This is because the breaking strength increases.

図３は本発明の第２の実施形態における半導体装置の平面図（一部透過図示）である。
この半導体装置のプリント配線基板２には、上述した第１の実施形態の半導体装置のＣｕ配線３の幅広部３ａと同様の配置で、Ｃｕ配線３とは電気的に分離した補強Ｃｕ配線９が形成されている。すなわち、プリント配線基板２の半導体チップ搭載面に複数のＣｕ配線３が形成されるとともに、Ｃｕ配線３どうしの間に、封止境界部５ａの内外にわたる寸法を有する補強Ｃｕ配線９が、封止境界部５ａに沿うように、且つ封止範囲を囲むように、且つＣｕ配線３に近接するように形成されている。この補強Ｃｕ配線９は、Ｃｕ配線３と同材料、同工程で作製され、Ｃｕ配線３と同じ厚みを有している。 FIG. 3 is a plan view (partially transparent) of a semiconductor device according to the second embodiment of the present invention.
The printed wiring board 2 of this semiconductor device has a reinforcing Cu wiring 9 electrically separated from the Cu wiring 3 in the same arrangement as the wide portion 3a of the Cu wiring 3 of the semiconductor device of the first embodiment described above. Is formed. That is, a plurality of Cu wirings 3 are formed on the semiconductor chip mounting surface of the printed wiring board 2, and the reinforcing Cu wiring 9 having a dimension extending between the inside and outside of the sealing boundary 5 a is sealed between the Cu wirings 3. It is formed so as to be close to the Cu wiring 3 so as to be along the boundary 5a and to surround the sealing range. The reinforcing Cu wiring 9 is made of the same material and in the same process as the Cu wiring 3 and has the same thickness as the Cu wiring 3.

このため、上型１１の圧力をＣｕ配線３と補強Ｃｕ配線９とで受けることになり、補強Ｃｕ配線９がない従来構造に比べて、Ｃｕ配線３の単位面積あたりの圧力が低減され、Ｃｕ配線３に加わる負荷が低減される。この構造は、プリント配線基板２に面積的制約があったり、半導体装置の性能維持のためにＣｕ配線３の配置が制約される等で、上述したような幅広部３ａを形成するのが困難な場合などに都合よい。   For this reason, the pressure of the upper die 11 is received by the Cu wiring 3 and the reinforcing Cu wiring 9, and the pressure per unit area of the Cu wiring 3 is reduced compared to the conventional structure without the reinforcing Cu wiring 9, and Cu The load applied to the wiring 3 is reduced. In this structure, it is difficult to form the wide portion 3a as described above because the printed wiring board 2 has an area restriction or the arrangement of the Cu wiring 3 is restricted to maintain the performance of the semiconductor device. Convenient for cases.

図４は本発明の第３の実施形態における半導体装置の平面図（一部透過図示）である。
この半導体装置のプリント配線基板２には、上述した第１の実施形態の半導体装置と同様にＣｕ配線３に幅広部３ａが形成されるとともに、第２の実施形態の半導体装置と同様に、Ｃｕ配線３とは電気的に分離した補強Ｃｕ配線９が形成されている。 FIG. 4 is a plan view (partially transparent) of a semiconductor device according to the third embodiment of the present invention.
In the printed circuit board 2 of this semiconductor device, a wide portion 3a is formed in the Cu wiring 3 as in the semiconductor device of the first embodiment described above, and Cu is formed in the same manner as in the semiconductor device of the second embodiment. Reinforcing Cu wirings 9 that are electrically separated from the wirings 3 are formed.

この半導体装置でも、幅広部３ａ，補強Ｃｕ配線９を有することで、上述したのと同様の効果が得られる。この構造は、プリント配線基板２に面積的制約があったり、半導体装置の性能維持のためにＣｕ配線３の配置が制約される等で、幅広部３ａを大きく形成するのが困難な場合などに都合よい。   This semiconductor device also has the same effect as described above by having the wide portion 3a and the reinforcing Cu wiring 9. This structure is used when it is difficult to form a large wide portion 3a because the printed wiring board 2 has an area restriction or the arrangement of the Cu wiring 3 is restricted to maintain the performance of the semiconductor device. Convenient.

図５は本発明の第４の実施形態における半導体装置の断面図である。
この半導体装置では、半導体チップ１とプリント配線基板２との電気的接続を、上述した金属ワイヤーに代えて、半導体チップ１に形成した金属バンプ１ｂを介して行っている。またプリント配線基板２の半導体チップ搭載面に背反する面に、金属ボールに代えて外部接続用のランド１０を形成している。この半導体装置でも、プリント配線基板２を第１〜第３の実施形態と同様の配線構造とすることで、同様の効果が得られる。 FIG. 5 is a sectional view of a semiconductor device according to the fourth embodiment of the present invention.
In this semiconductor device, the electrical connection between the semiconductor chip 1 and the printed wiring board 2 is performed via metal bumps 1b formed on the semiconductor chip 1 instead of the metal wires described above. An external connection land 10 is formed on the surface opposite to the semiconductor chip mounting surface of the printed wiring board 2 instead of the metal ball. Also in this semiconductor device, the same effect can be obtained by making the printed wiring board 2 have the same wiring structure as in the first to third embodiments.

本発明によれば、半導体チップを搭載した配線基板を封止金型に挟み込んで樹脂封止することで生じやすい断線を防止することができ、半導体装置の多ピン化、高密度実装、さらには半導体装置を搭載する電子機器の多機能化、小型化に有用である。   According to the present invention, it is possible to prevent disconnection that is likely to occur by sandwiching a wiring board on which a semiconductor chip is mounted in a sealing mold and sealing with resin, thereby increasing the number of pins of a semiconductor device, high-density mounting, This is useful for multi-functionalization and miniaturization of electronic devices equipped with semiconductor devices.

本発明の第１の実施形態における半導体装置の平面図および断面図The top view and sectional drawing of the semiconductor device in the 1st Embodiment of this invention 図１の半導体装置を製造する際の封止工程を説明する断面図Sectional drawing explaining the sealing process at the time of manufacturing the semiconductor device of FIG. 本発明の第２の実施形態における半導体装置の平面図The top view of the semiconductor device in the 2nd Embodiment of this invention 本発明の第３の実施形態における半導体装置の平面図The top view of the semiconductor device in the 3rd Embodiment of this invention 本発明の第４の実施形態における半導体装置の断面図Sectional drawing of the semiconductor device in the 4th Embodiment of this invention 従来の半導体装置の平面図および側面図Plan view and side view of conventional semiconductor device 本発明および従来の半導体装置を製造する際の封止工程を説明する工程断面図Process sectional drawing explaining the sealing process at the time of manufacturing this invention and the conventional semiconductor device 従来の半導体装置を製造する際の封止工程での配線基板の変形を説明する模式図Schematic diagram for explaining the deformation of the wiring board in the sealing process when manufacturing a conventional semiconductor device

符号の説明Explanation of symbols

１ 半導体チップ
２ プリント配線基板
３ Ｃｕ配線
３ａ 幅広部
４ 金属ワイヤー
５ 封止樹脂
５ａ 封止境界部
７ 金属ボール
９ 補強Ｃｕ配線
１１ 上型
１２ 下型
１３ 空房部 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Printed wiring board 3 Cu wiring 3a Wide part 4 Metal wire 5 Sealing resin 5a Sealing boundary part 7 Metal ball 9 Reinforcement Cu wiring 11 Upper mold | type 12 Lower mold | type 13 Empty part

Claims (5)

半導体チップを配線基板上に搭載し、前記半導体チップの接続端子と配線基板上の配線とを電気的に接続し、前記配線基板上の半導体チップを含んだ所望範囲を封止樹脂で封止した半導体装置において、
前記配線基板の半導体チップ搭載面に、前記配線と同等の厚みおよび前記所望範囲の内外にわたる寸法を有する配線パターンを、前記配線と一体にあるいは前記配線から電気的に分離して、前記所望範囲の境界に沿って前記所望範囲を囲むように形成した半導体装置。 A semiconductor chip is mounted on a wiring board, a connection terminal of the semiconductor chip and a wiring on the wiring board are electrically connected, and a desired range including the semiconductor chip on the wiring board is sealed with a sealing resin. In semiconductor devices,
On the semiconductor chip mounting surface of the wiring board, a wiring pattern having a thickness equivalent to the wiring and a dimension extending in and out of the desired range is integrated with the wiring or electrically separated from the wiring, A semiconductor device formed so as to surround the desired range along a boundary. 配線と一体になって配線の幅広部を構成している配線パターンと、配線間に電気的に分離して形成された配線パターンとの両方を有した請求項１記載の半導体装置。   The semiconductor device according to claim 1, comprising both a wiring pattern that forms a wide portion of the wiring integrally with the wiring, and a wiring pattern that is formed by being electrically separated between the wirings. 配線基板の半導体チップ搭載面に背反する面に、前記半導体チップ搭載面の配線に電気的に接続する外部接続用のランドあるいは金属突起電極を有した請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, further comprising a land for external connection or a metal protruding electrode electrically connected to the wiring on the semiconductor chip mounting surface on a surface opposite to the semiconductor chip mounting surface of the wiring board. 半導体チップと配線基板とがワイヤーあるいは金属バンプを介して電気的に接続した請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor chip and the wiring board are electrically connected via a wire or a metal bump. 半導体チップを配線基板上に搭載し、前記半導体チップの接続端子と配線基板上の配線とを電気的に接続するボンディング工程と、前記配線基板上の半導体チップを含んだ所望範囲を封止樹脂で封止する封止工程とを行う半導体装置の製造方法において、
前記封止工程で、前記配線と同等の厚みおよび前記所望範囲の内外にわたる寸法を有する配線パターンを前記配線と一体にあるいは前記配線から電気的に分離して前記所望範囲の境界に沿って前記所望範囲を囲むように形成した前記配線基板を、前記所望範囲の外側を挟み込むように封止金型内に配置し、この封止金型のキャビティ内に封止樹脂材料を圧入し、成形硬化させる半導体装置の製造方法。 A semiconductor chip is mounted on a wiring board, a bonding step for electrically connecting the connection terminals of the semiconductor chip and wiring on the wiring board, and a desired range including the semiconductor chip on the wiring board is formed with a sealing resin. In a manufacturing method of a semiconductor device that performs a sealing step of sealing,
In the sealing step, a wiring pattern having a thickness equivalent to the wiring and a dimension extending in and out of the desired range is integrated with the wiring or electrically separated from the wiring and along the boundary of the desired range. The wiring board formed so as to surround the range is placed in a sealing mold so as to sandwich the outside of the desired range, and a sealing resin material is press-fitted into the cavity of the sealing mold, and is molded and cured. A method for manufacturing a semiconductor device.
JP2005033718A 2005-02-10 2005-02-10 Semiconductor device and its manufacturing method Pending JP2006222239A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250674A (en) * 2006-03-14 2007-09-27 Sanyo Electric Co Ltd Substrate and semiconductor device using the same
JP2013183002A (en) * 2012-03-01 2013-09-12 Ibiden Co Ltd Electronic component

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250674A (en) * 2006-03-14 2007-09-27 Sanyo Electric Co Ltd Substrate and semiconductor device using the same
JP2013183002A (en) * 2012-03-01 2013-09-12 Ibiden Co Ltd Electronic component

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