JP2007250674A - Substrate and semiconductor device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for preventing the separation of a wiring pattern and improving reliability in a semiconductor device. <P>SOLUTION: The semiconductor device 1 comprises: a first substrate 11 in which the wiring pattern 111 is formed; a semiconductor element 2 mounted on the surface of the first substrate 11; a second substrate 12 that has a hollowed-out section 121 penetrating from the front to the rear and is joined to the surface of the first substrate 11 so that the scooped-out section 121 stores the semiconductor element 2; and a protective film 13 provided on the surface of the second substrate 12 so that a space (hollow section) 14 surrounded by the first substrate 11 and the scooped-out section 121 is blocked. A reinforcement pattern made of the same material as that of the wiring pattern is formed on the rear of the first substrate 11 continuously to the wiring pattern so that the contact area between the wiring pattern and the first substrate 11 is increased. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a substrate and a semiconductor device using the same, and more particularly to a technique for improving the reliability of a semiconductor device by preventing peeling of a wiring pattern.

As seen in the related technology of CSP (Chip Size Package), with the recent miniaturization of electronic devices, semiconductor devices mounted on these electronic devices are required to be miniaturized and miniaturized. For this reason, high reliability is also demanded for wiring patterns formed on substrates used in these semiconductor devices.
Japanese Patent Laid-Open No. 9-198394 JP 20041655312 A

  As a technique for improving the reliability of a wiring pattern, for example, Patent Document 1 describes devising the material and cross-sectional shape of the wiring pattern, the adhesiveness between the wiring pattern and the substrate, and the like. Patent Document 2 describes a technique for preventing peeling of a wiring pattern that proceeds from a cross section of a wiring pattern exposed on an end face of a substrate when a semiconductor device is cut out by dicing. As described above, various attempts have been made to improve the reliability of semiconductor devices that are becoming smaller and finer by preventing the peeling of wiring patterns.

  The present invention relates to a technique for preventing peeling of a wiring pattern by a method different from these conventional techniques, and to provide a substrate capable of improving the reliability of a semiconductor device and a semiconductor device using the same. With the goal.

  The main invention of the present invention for achieving the above object is a substrate, wherein the reinforcing pattern made of the same material as the wiring pattern increases the contact area between the wiring pattern and the substrate. The wiring pattern is formed continuously.

  In this way, the reinforcing pattern made of the same material as the wiring pattern is continuously formed on the wiring pattern so as to increase the contact area between the wiring pattern and the substrate, thereby providing a wiring pattern substrate. The bonding strength to the wiring can be increased, and peeling of the wiring pattern can be reliably prevented.

  One of the other main inventions of the present invention is the substrate, wherein the wiring pattern is linear, and the reinforcing pattern is formed on the wiring pattern so as to increase a line width of the wiring pattern. It is assumed that it is formed at a predetermined position in the longitudinal direction.

  Thus, when the wiring pattern is linear, the reinforcing pattern is formed at a predetermined position in the longitudinal direction of the wiring pattern so as to increase the line width of the wiring pattern, thereby changing the shape of the wiring pattern. Reinforcing patterns can be formed while minimizing. Further, for example, with respect to peeling that proceeds from one end of the wiring pattern, it is possible to stop the peeling from progressing further at the reinforcing pattern portion. Therefore, for example, a reinforcing pattern is formed in front of the main part of the wiring pattern, such as a part to be a bonding pad, thereby reliably preventing the main part from peeling off while minimizing the area of the reinforcing pattern. be able to.

  The shape of the reinforcing pattern is preferably a semicircular shape, for example. The reinforcing pattern may be formed only on one side in the longitudinal direction of the wiring pattern, or may be formed on both sides in the longitudinal direction of the wiring pattern. Moreover, you may make it form a reinforcement pattern in several places along the longitudinal direction of a wiring pattern. The reinforcing pattern may be formed so as to extend one end in the longitudinal direction of the wiring pattern.

  According to the present invention, peeling of the wiring pattern can be prevented, and the reliability of the semiconductor device can be improved.

  Hereinafter, one embodiment of the present invention will be described in detail. FIG. 1A is a perspective view of a semiconductor device 1 described as an embodiment of the present invention as seen from the front side, and FIG. 1B is a perspective view of the semiconductor device 1 as seen from the back side.

  As shown in FIG. 1A, the semiconductor device 1 has a rectangular parallelepiped (or cubic) appearance, a flat rectangular parallelepiped (or flat cubic) first substrate 11 having a wiring pattern formed on the surface thereof, and A semiconductor element 2 mounted on the surface of the first substrate 11 and a rectangular parallelepiped shape (or cubic shape) constituting a wall body that is laminated on the surface of the first substrate 11 and is provided so as to surround the periphery of the semiconductor element 2. The second substrate 12 and the protective film 13 bonded to the surface of the second substrate 12 are included. The second substrate 12 is pierced into a flat, substantially rectangular parallelepiped shape (or a flat, generally cubic shape) by drilling, laser processing, or the like. Is formed. The hollow portion 14 accommodates the semiconductor element 2.

  Here, since the semiconductor device 1 does not have a resin sealing structure by a mold body such as an epoxy resin and has a hollow portion 14 in which the semiconductor element 2 is accommodated, the semiconductor element 2 is, for example, In the case of an optical element, there is no attenuation or refraction when the light passes through the mold body, and the emitted light from the semiconductor device 1 can be efficiently emitted to the outside. Further, the light incident on the semiconductor device 1 from the outside can be efficiently received by the semiconductor element 2. In addition, since the protective film 13 is provided so as to close the space surrounded by the first substrate 11 and the punched-through portion 121, the wiring pattern and the semiconductor element formed on the surface of the first substrate 11 have dust, dirt, etc. Can be prevented from adhering.

  The 1st board | substrate 11 and the 2nd board | substrate 12 are organic substrates which mixed paper, glass cloth, etc. in resin, such as epoxy, polyester, polyimide, phenol, for example, and glass cloth base-material epoxy resin copper clad laminated board and It consists of a prepreg, a glass substrate heat-resistant resin copper-clad laminate, a prepreg, a paper substrate phenolic resin copper-clad laminate, and the like.

  The semiconductor element 2 is, for example, an optical element having a light-receiving part or a light-emitting part, a discrete element such as a transistor or a diode, a thermal oxidation method, CVD (Chemical Vapor Deposition), sputtering, lithography, impurity diffusion, etc. on a semiconductor substrate. These are CMOS (Complementary Metal Oxide Semiconductor), bi-CMOS, MOS, linear (bipolar) IC, etc. manufactured through the process. In the following description, it is assumed that the semiconductor element 2 is an optical element having a light emitting part or a light receiving part 21 on the surface thereof.

  A plurality of electrode pads 22 (bonding pads) made of a conductor such as gold or aluminum are formed on the surface of the semiconductor element 2. A plurality of electrode leads 111 (inner leads) are formed on the surface of the first substrate 11. Each electrode pad 22 and the electrode lead 111 corresponding to each electrode pad 22 are connected by a bonding wire 15 made of a conductor wire such as gold or aluminum. A solder resist 123 is formed on the surface of the first substrate 11 except for an opening formed in a part thereof.

  As shown in FIG. 1B, a plurality of electrode leads 112 arranged along the edge of the first substrate 11 are formed on the back surface of the first substrate 11. A solder resist 124 is formed in a rectangular region on the back surface of the first substrate 11 including the center of the back surface of the semiconductor device 1 and excluding the end portions of the electrode leads 112.

  The protective film 13 serves to prevent dust and dirt from adhering to the semiconductor element 2, the wiring pattern, the bonding wire 15 and the like housed in the hollow portion 14. As a material of the protective film 13, a material that is resistant to infrared rays, visible rays, ultraviolet rays, and the like and has resistance to high temperatures such as during reflow is used. For example, polyimide or the like is used. In addition, in FIG. 1A, although the protective film 13 is drawn transparently, the protective film 13 may not be transparent. The protective film 13 is bonded to the second substrate 12 with an adhesive such as silicon or acrylic that is resistant to infrared rays, visible light, ultraviolet rays, or the like.

<< First substrate >>
FIG. 2A shows a plan view of the first substrate 11, and FIG. 2B shows a back view of the first substrate 11. As will be described later, solder resists 123 and 124 are formed on the front and back surfaces of the first substrate 11, but the solder resist 123 is formed on the first substrate 11 in FIGS. 2A and 2B. Represents the previous state.

  As shown in FIG. 2A, in the vicinity of the center on the front surface side of the first substrate 11, a rectangular element mounting for mounting the semiconductor element 2, each side being parallel to each side of the corresponding first substrate 11. Region 115 is provided.

  In FIG. 2A, a plurality of rectangular electrode leads 111 arranged along the contour line of the semiconductor element 2 are formed on the ± Y side of the element mounting region 115 where the semiconductor element 2 is disposed. A circular land 116 is formed at the end of each electrode lead 111 on the semiconductor element 2 side. Under each land 116, a penetrating electrode 113 that penetrates perpendicularly from the front surface to the back surface of the first substrate 11 is formed. On the outer peripheral side of the first substrate 11 of each electrode lead 111, a finer wiring pattern (hereinafter referred to as a lead line 117) than the electrode lead 111 is continuous. The lead line 117 is used for, for example, a continuity test. The other end of each lead line 117 reaches the outer peripheral edge of the first substrate 11.

  A conductor (copper foil) having the same thickness as that of the electrode lead 111 is formed in a substantially rectangular region that does not include the land 116 and the electrode lead 111 and includes a part of the element mounting region 115 near the center of the surface of the first substrate 11. Etc.) is formed, and a mesh-like wiring pattern (hereinafter referred to as a mesh pattern 118) is formed. Here, the mesh pattern 118 is provided for the purpose of ensuring the flatness of the element mounting region 115. That is, since the region sandwiched between the lands 116 arranged on the ± Y side of the element mounting region 115 on the surface of the first substrate 11 is depressed with respect to the land 116 part, the first If the solder resist 123 is formed on the surface of the substrate 11, unevenness is generated on the surface of the solder resist 123. However, by forming the mesh pattern 118, it is possible to ensure the flatness of the surface of the solder resist 123. Can do. In addition, by ensuring flatness in this way, the semiconductor element 2 can be reliably bonded to a position corresponding to the element mounting region 115 on the surface of the solder resist 123. That is, when the flatness is impaired, the void strength generated in the adhesive for bonding the semiconductor element 2 and the adhesive strength is reduced due to the non-uniform coating thickness of the adhesive. Can prevent problems. Note that the amount of material necessary for forming the wiring pattern can be saved by using a mesh-like wiring pattern instead of the entire surface.

  An L-shaped wiring pattern (hereinafter referred to as a position mark 119) is formed at a predetermined position on the surface of the first substrate 11. The position mark 119 is used as a mark when positioning the first substrate 11 in a semiconductor manufacturing apparatus such as a die bonding apparatus or a wire bonding apparatus.

  As shown in FIG. 2B, a through electrode 113 connected to the surface of the first substrate 11 is formed on the back surface of the first substrate 11. A circular land 120 is formed on the back surface of the first substrate 11 at a position where each through electrode 113 is formed.

  Each land 120 is formed with a plurality of rectangular electrode leads 112 extending in the ± Y direction of FIG. 2B and arranged in two rows in the ± X direction of FIG. 2B starting from each land. One end of each electrode lead 112 reaches the outer peripheral edge of the first substrate 11. A wiring pattern (hereinafter, referred to as a connection pattern 122) having one end connected to the land 120 is connected to the other end of each electrode lead 112. As shown in FIG. 2B, the continuous electrode lead 112 and the connection pattern 122 may be formed so as to cross each other or may be formed so that they are arranged in a straight line. . The shape of the electrode lead 112 or the connection pattern 122 is determined in various ways according to the shape of the semiconductor element 2 mounted on the first substrate 11, the arrangement of the electrode pads 22, the wiring layout of the first substrate 11, and the like. Is done.

  Around the connection portion between the electrode lead 112 and the connection pattern 122, the connection portion is formed so as to increase the line width of the wiring pattern continuously with the linear wiring pattern formed of the electrode lead 112 and the connection pattern 122. A substantially semicircular pattern (hereinafter, referred to as a reinforcing pattern 114) is formed on each of the two sides.

  Here, in this way, the reinforcing pattern 114 made of the same material as the wiring pattern is added to the wiring pattern made of the electrode lead 112 and the connection pattern 122 to increase the contact area between the wiring pattern and the first substrate 11. As a result, the bonding strength of the wiring pattern to the substrate is increased, and peeling of the wiring pattern can be prevented. In the case where peeling progresses from one end of the wiring pattern, the peeling stops at the position of the reinforcing pattern 114 that is firmly bonded to the substrate 11, and the peeling progresses to the connection pattern 122 side. Can be prevented.

  The reinforcing pattern 114 does not necessarily have to be formed at the position shown in FIG. 2B. Further, the shape of the reinforcing pattern 114 is not limited to the shape shown in FIG. 2B. For example, the reinforcing pattern 114 may be formed only on one of the left and right sides of the wiring pattern in the longitudinal direction, or may be formed on both the left and right sides of the wiring pattern in the longitudinal direction. Further, the reinforcing pattern 114 may be formed at a plurality of locations along the longitudinal direction of the wiring pattern.

  In other words, the shape of the reinforcing pattern 114 is a shape that can ensure the necessary bonding strength to prevent the wiring pattern from peeling off, does not change the electrical / magnetic characteristics of the semiconductor device 1, and is adjacent to the reinforcing pattern 114. The size may be such that it does not come into contact with other formed wiring patterns.

  In addition, the electrode lead 111 on the front surface side, the lead wire 117, the position mark 119, the electrode lead 112 on the back surface side, the reinforcing pattern 114, the mesh pattern 118, the land 120, and the connection pattern 122 described above are, for example, copper ( It is made of a thin film conductor such as Cu). These are formed by, for example, a subtractive method or a full additive method. Since the reinforcing pattern 114 and the mesh pattern 118 can be formed in the same process as other wiring patterns in this way, the process is not complicated by providing the mesh pattern 118. Each through electrode 113 is formed through a desmear process, an electroless plating or a surface plating process by electroplating after a via hole is formed in the first substrate 11 by drilling or laser processing. .

  FIG. 3A shows a plan view of the first substrate 11 after the solder resist 123 is formed. FIG. 3B shows a back view of the first substrate 11 after the solder resist 124 is formed. Further, FIG. 3C shows a plan view in a state in which the second substrate 12 is bonded to the surface of the first substrate 11.

  As shown in FIG. 3A, on the surface of the first substrate 11, except for openings formed in a part thereof, for example, a screen printing method using a thermosetting or ultraviolet curable ink material, a photosensitive resin A solder resist 123 is formed by a photographic method using a material. One of the openings (hereinafter referred to as the first resist opening 131) includes the element mounting region 115 and has an annular shape with a predetermined line width in a shape substantially similar to the inner periphery of the second substrate 12. Is formed.

  The inner peripheral edge of the penetrating part 121 of the second substrate 12 on the side facing the first substrate 11 is located inside the first resist opening 131. More specifically, the first resist opening 131 is formed so that the inner peripheral edge of the second substrate 12 coincides with a line passing through substantially the center of the line width of the first resist opening 131. . Here, the surplus of the adhesive applied when the first substrate 11 and the second substrate 12 are joined leaks around the second substrate 12, but the leaked adhesive is, for example, an electrode lead. If it adheres to 111, problems such as surface contamination and wire bonding failure may occur, but the first resist opening 131 serves to prevent this. 3D is a cross-sectional view of the semiconductor device 1 taken along the line PP ′ of FIG. 3C. As shown in FIG. 3D, the adhesive 145 leaked around the second substrate 12 is the first It flows into the resist opening 131 and the intrusion of the adhesive 145 into the first resist opening 131 is prevented. That is, the first resist opening 131 functions as a breakwater that prevents the leaked adhesive 145 from entering.

  On the inner periphery side of the first resist opening 131, on the ± Y side of the region where the semiconductor element 2 is disposed, a band-shaped opening (hereinafter referred to as an electrode lead 111) to which a bonding stitch is applied is exposed. , Second resist opening 132). A square opening for exposing the position mark 119 (hereinafter referred to as a third resist opening 133) is formed in a portion corresponding to the position mark 119 on the inner peripheral side of the first resist opening 131. Is formed.

  As shown in FIG. 3B, a rectangular solder resist 124 is formed on the back surface of the second substrate 12 so as to cover the lands 120 and the connection patterns 122 shown in FIG. 2B. For this reason, only the electrode lead 112 is exposed on the back surface of the second substrate 12. The solder resist 124 is also formed on the reinforcing pattern 114. For this reason, the electrode lead 112 and the connection pattern 122 are securely bonded to the first substrate 11 by the tension of the solder resist 124 and the formation of the reinforcing pattern 114, and the wiring pattern is surely peeled off. Can be prevented.

<< Manufacturing method >>
Next, a method for manufacturing the semiconductor device 1 described above will be described in detail. FIG. 4A is a plan view of a first collective substrate 41 used in the manufacturing method described below, and FIG. 4B is a plan view of a second collective substrate 42 used in the manufacturing method described below. FIG. 4C is a plan view showing a state in which the second collective substrate 42 is positioned and overlaid on the first collective substrate 41.

  As shown in FIG. 4A, the first collective substrate 41 includes the wiring patterns described above, that is, the electrode leads 112, lands 116, through electrodes 113, lead lines 117, mesh patterns 118, position marks 119, electrode leads 112, A plurality of first substrates 11 each including a connection pattern 122 and a land 120 are continuously arranged. Further, as shown in FIG. 4B, a plurality of second substrates 12 are continuously arranged on the second aggregate substrate 42. Note that the solder resists 123 and 124 described above are already formed on the first collective substrate 41.

  First, in the process shown in FIG. 5A (a), the semiconductor element 2 is picked up by a pickup device, placed in the region of the surface of the first collective substrate 41, and the first collective substrate 41 of the first collective substrate 41 is bonded by resin bonding or metal bonding. It is mounted on the element mounting region 115 of one substrate 11. In the case of resin bonding, an adhesive is a paste resin, a die attach film (DAF ((Die Attach Film)), or the like.

  In the subsequent step shown in FIG. 5A (b), wire bonding is performed to connect the electrode pads 22 and the electrode leads 111.

  5A (c), the first collective substrate 41 and the second collective substrate 42 are aligned, and the second collective substrate 42 is pasted on the surface of the first collective substrate 41. Or it joins using the adhesive agent of a sheet-like epoxy resin system. In the case of using a sheet-like adhesive, for example, this joining is performed by, for example, attaching a sheet-like adhesive with a carrier film in advance to the joining surface of the second aggregate substrate 42 and peeling off the carrier film. The second collective substrate 42 is bonded to the first collective substrate 41 and thermocompression bonded.

  In the step shown in FIG. 5A (d), a protective film sheet 43 to be the protective film 13 is bonded to the surface of the second aggregate substrate 42. As the protective film sheet 43, for example, a film in which a silicon-based or acrylic adhesive is applied to the bonding surface in advance is used.

  In the step shown in FIG. 5A (e), an acrylic or polyimide dicing sheet 44 is bonded to the back surface of the first collective substrate 41.

  In the step shown in FIG. 5A (f), the joined body of the first collective substrate 41 and the second collective substrate 42 is set on the cutting table 50 of the dicing apparatus, and each punched portion of the second collective substrate 42 is penetrated. Dicing is performed by full-cut dicing, with a line passing through the center of the lattice part that divides 121 (one of the dicing lines is shown as a QQ ′ line in FIG. 4A) as a dicing line. By cutting the joined body of the first collective substrate 41 and the second collective substrate 42 and the protective film sheet 43 by full-cut dicing in this way, the flatness of the cut surface is naturally secured, and protection after cutting is achieved. Each side surface of the film 13 and each side surface of the second substrate 12 corresponding to each side surface of the protective film 13 have a flat side structure that forms a continuous plane. By adopting such a flat side structure, for example, when the semiconductor device 1 is picked up by being picked up by a collet, the semiconductor device 1 can be picked up reliably, and the semiconductor device 1 can be attached to the equipment. Misalignment is less likely during assembly.

  By the way, in the example shown in FIG. 5A (f), the outer peripheral edge of the first collective substrate 41 protrudes slightly outside the second collective substrate 42, but dicing is performed by applying a dicing blade 51 to the protruding portion. If this is performed, the substrate may be damaged due to vibration and vibration. Therefore, in the dicing, the joined body is set in the dicing apparatus so that the first collective substrate 41 side is fixed to the cutting table 50 so that the second collective substrate 42 is positioned above, and the dicing blade 51 is attached to the protective film. This is performed so as to be applied from the side of the sheet 43.

  The protruding portion as shown in FIG. 5A (f) serves as a support portion when, for example, a joined body of the first aggregate substrate 41 and the second aggregate substrate 42 is set in a manufacturing apparatus such as a wire bonder. However, the protruding portion may not be necessary depending on the specifications of the manufacturing apparatus and the manufacturing process. In this case, the end surfaces of the first collective substrate 41 and the second collective substrate 42 can be matched and joined. In such a case, for example, as shown in FIG. 5B, the joined body is fixed to the cutting table 50 with the second aggregate substrate 42 side down, and the dicing blade 51 is fixed to the first aggregate substrate 41 side. It ’s a good idea to start with. That is, when the dicing blade 51 comes into contact with the edge of the protective film 13 that protrudes around the second aggregate substrate 42, the protective film 13 may be shaken and difficult to dice. Thus, dicing can be performed smoothly. In this case, the protective film 13 and the dicing sheet 44 are stacked and bonded together. In such a case, the protective film sheet 43 and the dicing sheet 44 are bonded in advance. By using it, the operation of attaching the protective film sheet 43 and the operation of attaching the dicing sheet 44 can be completed by a single operation, and the process can be simplified.

  According to the manufacturing method described above, the semiconductor device 1 can be produced efficiently. In particular, if it is attempted to cut the hollow portion 14 from a bulk material by drilling or laser processing, it is difficult to ensure the flatness of the surface of the first substrate 11 and the electrical characteristics of the semiconductor device 1 are adversely affected. However, by forming the hollow portion 14 by laminating the first collective substrate 41 and the second collective substrate 42 in this way, the above-mentioned problem is caused. There is no problem. When trying to cut the hollow portion 14 by drilling or laser processing, the workability is poor because the semiconductor element 2 is mounted in the narrow hollow portion 14 or the bonding wire 15 is connected after cutting. In the manufacturing method described above, since the semiconductor element 2 is mounted in advance before the second substrate 12 is bonded to the surface of the first substrate 11, efficient production is possible.

  In the manufacturing method described above, the semiconductor element 2 is mounted on the first collective substrate 41, and after wire bonding, the first collective substrate 41 and the second collective substrate 42 are bonded together. Alternatively, the semiconductor element 2 may be mounted on the first collective substrate 41 and wire bonding may be performed after the first collective substrate 41 and the second collective substrate 42 are bonded together. Alternatively, after mounting the semiconductor element 2 on the first collective substrate 41, the first collective substrate 41 and the second collective substrate 42 may be bonded together, and then wire bonding may be performed.

<< Protective film >>
When it is a premise that the semiconductor device 1 is used by peeling off the protective film 13, it is preferable that the protective film 13 is easily peeled off during use. Here, as a method for facilitating peeling off the protective film 13, for example, a protective film 13 having a property of peeling when heat is applied (thermal release sheet) is selected when a heating step such as reflow treatment is unnecessary. It is possible to do. Further, for example, as shown in FIG. 6A or 6B, the protective film 13 may be formed with a notch 150 serving as a clue when the film is peeled off.

  Here, the cutout 150 having the shape shown in FIG. 6A or FIG. 6B is, for example, a protective film bonded to the second aggregate substrate 42 as shown in FIG. 7A or FIG. 7B in the step before the dicing step. By forming a hole 151 that can be easily formed by drilling or the like at the intersection of dicing lines of the sheet 43, the sheet 43 can be formed easily.

  For example, FIG. 7A shows a state in which the protective film sheet 43 is bonded to the second aggregate substrate 42. As shown in FIG. 7A, a square hole 151 is formed at the intersection of the dicing lines of the protective film sheet 43. By drilling, four notches 150 having the shape shown in FIG. 6A can be formed for one hole 151 by dicing. For example, FIG. 7B shows a state in which the protective film sheet 43 is bonded to the second aggregate substrate 42. As shown in FIG. 7B, a circular hole is formed at the intersection of the dicing lines of the protective film sheet 43. By perforating 151, four portions of the notch 150 having the shape shown in FIG. 6B can be formed for one hole 151 by dicing. Note that the shape of the notch 150 is not limited to that shown above. For example, a shape obtained by dividing a polygon such as a square by a line passing through the center thereof, or a shape obtained by dividing a circle or an ellipse by a line passing through the center thereof may be used.

  As the protective film 13, for example, a long wavelength cut filter, a short wavelength cut filter, a band pass filter, or the like that functions as an optical filter that selectively passes only light (electromagnetic waves) having a specific wavelength may be used. For example, when the semiconductor element 2 is a light receiving element, such as when only the far infrared light is incident on the semiconductor element 2 when the semiconductor element 2 is a human sensor, only light of a specific wavelength is received. It can be made to enter into an element. Further, when the semiconductor element 2 is a light emitting element, only light having a specific wavelength can be emitted.

  By the way, description of the above embodiment is for making an understanding of this invention easy, and does not limit this invention. It goes without saying that the present invention can be changed and improved without departing from the gist thereof, and that the present invention includes equivalents thereof. For example, in the above-described embodiment, the first substrate 11 is a flat type, but the first substrate 11 may be a multilayer substrate. A plurality of semiconductor elements 2 may be mounted on the first substrate 11.

  For example, in the above-described embodiment, the first substrate 11 is a flat type, but the first substrate 11 may be a multilayer substrate. A plurality of semiconductor elements 2 may be mounted on the first substrate 11.

  The aspects of the reinforcing pattern 114 and the mesh pattern 118 are not limited to those described above. Various other forms of the reinforcing pattern 114 and the mesh pattern 118 are conceivable depending on the number and form of the substrate and the semiconductor elements 2 mounted thereon.

  8A and 8B are a plan view and a back view of a VQLP (Very Thin-Quad-Land-Peripheral Type Package) type substrate 110 having a reinforcing pattern 114 and a mesh pattern 118 which is different from the above-described embodiment. ing.

  As shown in FIG. 8A, the substrate 110 has a square shape. A plurality of through holes 113 and lands 116 are formed on the surface of the substrate 110 in an annular shape along the outer periphery of the substrate 110. In addition, electrode leads 111 extending in the outer peripheral direction of the substrate 110 are formed from each land 116 as a base point. The terminal end of the electrode lead 111 located on the outer peripheral side of the substrate 110 has a square shape. A mesh pattern 118 is formed in a region surrounded by each land 116 at the center of the substrate 110.

  On the other hand, as shown in FIG. 8B, a plurality of through holes 113 and lands 120 are formed on the back side of the substrate 110 in an annular shape along the outer periphery of the substrate 110. Further, with each land 120 as a base point, a connection pattern 122 extending in the outer peripheral direction of the substrate 110 and an electrode lead 112 extending in the outer peripheral direction continuously to one end of the connection pattern 122 are formed. In addition, a semicircular reinforcing pattern made of the same material as the wiring pattern is continuously provided around the portion where the electrode lead 112 and the connection pattern 122 are connected to each other, following the wiring pattern (the electrode lead 112 and the connection pattern 122). 114 is formed on one or both sides in the left-right direction with respect to the longitudinal direction of the wiring pattern. A mesh pattern 118 is formed in a region surrounded by each land 116 at the center of the back surface of the substrate 110.

  Here, as shown in FIG. 8B, in the case of this substrate 110, the electrode lead 112 reaches the end surface of the substrate 110, and the cut surface of the electrode lead 112 is exposed at the end surface of the substrate 110. For this reason, in the case of this substrate 110, peeling tends to proceed from one end of the electrode lead 112 exposed at the end surface of the substrate 110 toward the inside of the substrate 110. However, the progress of such peeling stops at the portion of the reinforcing pattern 114. That is, the reinforcing pattern 114 prevents the peeling from reaching the connection pattern 122 side.

  FIG. 9 shows a back view of a FLGA (Fine Pitch Land Grid Array) type substrate 110 having a reinforcing pattern 114 and a mesh pattern 118 having a different form from the above-described embodiment. As shown in the figure, the substrate 110 has a square shape, and a plurality of electrode leads 112 having a predetermined length in the direction of + 45 ° or −45 ° with respect to the X axis are formed on the back surface of the substrate 110. Yes. A land 116 is formed at one end of each electrode lead 112, and a through hole 113 that penetrates the surface of the substrate 110 is formed in the land 116. In addition, square terminals 126 are formed at four corners of the substrate 110. Further, in the region sandwiched between the four terminals 126 in the peripheral portion of the substrate 110, four linear mesh patterns 118 parallel to the outer periphery of the substrate 110 are formed.

  In each terminal 126, one of the electrode leads 112 extending in the direction of + 45 ° or −45 ° with respect to the X axis is formed continuously at a corner portion of each terminal 126 located on the inner peripheral side of the substrate 110. . One end of the electrode lead 112 continuing to each terminal 126 protrudes from the outer periphery of the terminal 126. The protruding portion serves to prevent the electrode lead 112 from peeling off.

It is the see-through | perspective perspective view which looked at the semiconductor device 1 demonstrated as one Embodiment of this invention from the surface side. It is the perspective view which looked at the semiconductor device 1 demonstrated as one Embodiment of this invention from the back surface side. It is a top view of the 1st board | substrate 11 demonstrated as one Embodiment of this invention. It is a back view of the 1st board | substrate 11 demonstrated as one Embodiment of this invention. It is a top view of the 1st board | substrate 11 after forming the soldering resist 123 demonstrated as one Embodiment of this invention. It is a back view of the 1st board | substrate 11 after forming the soldering resist 123 demonstrated as one Embodiment of this invention. It is a top view which shows the state which joined the 2nd board | substrate 12 to the surface of the 1st board | substrate 11 shown to FIG. 3A demonstrated as one Embodiment of this invention. It is sectional drawing of the semiconductor device 1 in the P-P 'line | wire of FIG. 3C demonstrated as one Embodiment of this invention. It is a top view of the 1st collective substrate 41 demonstrated as one Embodiment of this invention. It is a top view of the 2nd collective substrate 42 explained as one embodiment of the present invention. It is a figure which shows the state which bonded together the 1st collective substrate 41 demonstrated as one Embodiment of this invention, and the 2nd collective substrate 42, The top view which looked at the bonded state from the 2nd collective substrate 42 side It is. It is a process flow explaining the manufacturing method demonstrated as one Embodiment of this invention. It is a process flow explaining the manufacturing method demonstrated as one Embodiment of this invention. It is the perspective view which looked at the semiconductor device 1 which has the notch 150 used as a clue when peeling this to the protective film 13 demonstrated as one Embodiment of this invention from the surface side. It is the perspective view seen from the surface side of the semiconductor device 1 which has the notch 150 used as a clue when peeling this to the protective film 13 demonstrated as one Embodiment of this invention. It is a figure which shows the protective film sheet 43 explaining the method of forming the notch 150 in the protective film 13 demonstrated as one Embodiment of this invention, the 2nd aggregate substrate, and the 1st aggregate substrate, 1st aggregate It is the top view seen from the board | substrate side. It is a figure which shows the protective film sheet 43 explaining the method of forming the notch 150 in the protective film 13 demonstrated as one Embodiment of this invention, the 2nd aggregate substrate, and the 1st aggregate substrate, 1st aggregate It is the top view seen from the board | substrate side. It is a top view of the board | substrate 110 of the VQLP type demonstrated as one Embodiment of this invention. It is a back view of the VQLP type board | substrate 110 demonstrated as one Embodiment of this invention. It is a back view of the FLGA type board | substrate 110 demonstrated as one Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 1st board | substrate 12 2nd board | substrate 13 Protective film 14 Hollow part 15 Bonding wire 22 Electrode pad 41 1st aggregate substrate 42 2nd aggregate substrate 43 Protective film sheet 44 Dicing sheet 50 Cutting table 51 Dicing blade DESCRIPTION OF SYMBOLS 110 Substrate 111 Electrode lead 112 Electrode lead 113 Through electrode 114 Reinforcement pattern 115 Element mounting area 116 Land 126 Terminal 117 Lead line 118 Mesh pattern 119 Position mark 120 Land 121 Penetration part 122 Connection pattern 123 Solder resist 124 Solder resist 131 First resist Resist opening 132 Second resist opening 133 Third resist opening 150 Notch 151 Hole

Claims (11)

A substrate on which a wiring pattern is formed,
The board | substrate characterized by the reinforcing pattern which consists of the same material as the said wiring pattern being continuously formed in the said wiring pattern so that the contact area between the said wiring pattern and the said board | substrate may be increased. The substrate of claim 1,
The wiring pattern is linear,
The reinforcing pattern is formed at a predetermined position in the longitudinal direction of the wiring pattern so as to increase the line width of the wiring pattern. The substrate according to claim 2, wherein
The reinforcing pattern is substantially semicircular. The substrate according to claim 2, wherein
The reinforcing pattern is formed only on one side with respect to the longitudinal direction of the wiring pattern. The substrate according to claim 2, wherein
The board | substrate characterized by the said reinforcement pattern being formed in the both sides with respect to the longitudinal direction of the said wiring pattern. The substrate according to claim 2, wherein
The board | substrate characterized by the above-mentioned. The said reinforcement pattern is formed in several places along the longitudinal direction of the said wiring pattern. The substrate according to claim 2, wherein
The substrate, wherein the reinforcing pattern is formed so as to extend one end in the longitudinal direction of the wiring pattern. A substrate according to claim 7, wherein
The reinforcing pattern is formed so that one end of the reinforcing pattern protrudes from the periphery of the wiring pattern serving as an electrode terminal. The substrate according to claim 2, wherein
At least one end in the longitudinal direction of the wiring pattern reaches an edge of the substrate. A substrate on which a wiring pattern is formed;
A semiconductor element bonded to the surface of the substrate;
A wall provided on the surface of the substrate so as to surround the periphery of the semiconductor element;
Have
A semiconductor device, wherein a reinforcing pattern made of the same material as the wiring pattern is continuously formed on the wiring pattern so as to increase a contact area between the wiring pattern and the substrate. The semiconductor device according to claim 10,
The wiring pattern is linear,
The semiconductor device according to claim 1, wherein the reinforcing pattern is formed at a predetermined position in the longitudinal direction of the wiring pattern so as to increase a line width of the wiring pattern.

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