JP2006203230A - 配線基板およびそれを用いた電子装置 - Google Patents
配線基板およびそれを用いた電子装置 Download PDFInfo
- Publication number
- JP2006203230A JP2006203230A JP2006050956A JP2006050956A JP2006203230A JP 2006203230 A JP2006203230 A JP 2006203230A JP 2006050956 A JP2006050956 A JP 2006050956A JP 2006050956 A JP2006050956 A JP 2006050956A JP 2006203230 A JP2006203230 A JP 2006203230A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- melting point
- copper
- tin
- brazing material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】ガラスセラミックスから成る絶縁基体1に、電子部品3の電極が低融点ロウ材5を介して接続される、銅を主成分とした配線層2を形成して成る配線基板4であって、配線層2のうち前記電極が低融点ロウ材5を介して接続される領域の表面に、熱処理された銅錫合金層6および熱処理された銀または金と錫との合金層7が順次形成されている配線基板4である。低融点ロウ材5を配線層2に接続する際に、配線層2中の銅成分が低融点ロウ材5中に拡散することを効果的に防止することが可能となる。
【選択図】図1
Description
2・・・・配線層
3・・・・電子部品
4・・・・配線基板
5・・・・低融点ロウ材
6・・・・銅錫合金層
7・・・・銀または金と錫との合金層
8・・・・蓋体
9・・・・錫めっき層
10・・・・銀めっき層または金めっき層
Claims (4)
- 電子部品が搭載される絶縁基体と、該絶縁基体に形成された銅を主成分とした配線層とからなる配線基板であって、前記電子部品は、前記配線層上に、熱処理された銅錫合金層、熱処理された銀または金と錫との合金層、低融点ロウ材の順に積層された積層体を介して電気的に接続されるとともに、配線層中の銅、熱処理された銅錫合金層、熱処理された銀または金と錫との合金層、低融点ロウ材の順に融点が低くなる構成であることを特徴とする配線基板。
- 前記配線層の前記電子部品の電極が前記低融点ロウ材を介して接続される領域の表面に、0.5〜5μmの厚みを有する錫めっき層、および0.13〜1.3μmの厚みを有する銀めっき層が順次被着され、かつ熱処理されることにより銅錫合金層および銀錫合金層が順次形成される請求項1に記載の配線基板。
- 前記配線層の前記電子部品の電極が前記低融点ロウ材を介して接続される領域の表面に、0.5〜5μmの厚みを有する錫めっき層、および0.4〜4.1μmの厚みを有する金めっき層が順次被着され、かつ熱処理されることにより銅錫合金層および金錫合金層が順次形成される請求項1に記載の配線基板。
- 請求項1〜請求項3に記載の配線基板と、前記配線層と電気的に接合される電子部品とからなる電子装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006050956A JP4264091B2 (ja) | 2002-09-25 | 2006-02-27 | 配線基板の製造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002279128 | 2002-09-25 | ||
JP2006050956A JP4264091B2 (ja) | 2002-09-25 | 2006-02-27 | 配線基板の製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002331239A Division JP3792642B2 (ja) | 2002-09-25 | 2002-11-14 | 配線基板およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006203230A true JP2006203230A (ja) | 2006-08-03 |
JP4264091B2 JP4264091B2 (ja) | 2009-05-13 |
Family
ID=36960873
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006050956A Expired - Fee Related JP4264091B2 (ja) | 2002-09-25 | 2006-02-27 | 配線基板の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4264091B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010171367A (ja) * | 2008-12-27 | 2010-08-05 | Kyocer Slc Technologies Corp | 配線基板 |
CN114765923A (zh) * | 2021-05-20 | 2022-07-19 | 上海贺鸿电子科技股份有限公司 | 一种5g基站隔离器三层线路板及其制备方法 |
-
2006
- 2006-02-27 JP JP2006050956A patent/JP4264091B2/ja not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010171367A (ja) * | 2008-12-27 | 2010-08-05 | Kyocer Slc Technologies Corp | 配線基板 |
CN114765923A (zh) * | 2021-05-20 | 2022-07-19 | 上海贺鸿电子科技股份有限公司 | 一种5g基站隔离器三层线路板及其制备方法 |
Also Published As
Publication number | Publication date |
---|---|
JP4264091B2 (ja) | 2009-05-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9307637B2 (en) | Metallized via-holed ceramic substrate, and method for manufacture thereof | |
JP3555563B2 (ja) | 積層チップバリスタの製造方法および積層チップバリスタ | |
US9017563B2 (en) | Plating method of circuit substrate, production method of plated circuit substrate, and silver etching liquid | |
JP2006339536A (ja) | 電子部品および電子部品の製造方法 | |
KR20150086359A (ko) | 적층 세라믹 전자부품 및 그 제조방법 | |
KR100516759B1 (ko) | 질화알루미늄소결체 및 그로부터 제조된 금속화기판 | |
JP2007324301A (ja) | 窒化物セラミックス回路基板の製造方法。 | |
JP2009141292A (ja) | 外部端子電極具備電子部品、その搭載電子用品及び外部端子電極具備電子部品の製造方法 | |
JP4264091B2 (ja) | 配線基板の製造方法 | |
JP3792642B2 (ja) | 配線基板およびその製造方法 | |
JP3857219B2 (ja) | 配線基板およびその製造方法 | |
JP3866164B2 (ja) | 配線基板 | |
JP3208438B2 (ja) | 金属層を備えたセラミックス基板とその製造方法 | |
JP3929989B2 (ja) | 導電性ペースト及びその導電性ペーストを用いたセラミック多層回路基板。 | |
JP2003109838A (ja) | セラミック電子部品 | |
JP4761595B2 (ja) | メタライズ基板 | |
JP2002084051A (ja) | 銅メタライズ組成物、低温焼結セラミック配線基板、及びその製造方法 | |
JP4570190B2 (ja) | 配線基板 | |
JP2008112786A (ja) | 多層セラミックス基板及びその製造方法 | |
JP2006203163A (ja) | 配線基板 | |
JP2004281426A (ja) | ガラスセラミック配線基板 | |
JPH1065294A (ja) | セラミックス配線基板およびその製造方法 | |
JP3652184B2 (ja) | 導体ペースト、ガラスセラミック配線基板並びにその製法 | |
JP3631572B2 (ja) | 配線基板およびその製造方法 | |
JP2005268515A (ja) | セラミック配線基板およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080715 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080722 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080922 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081014 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081212 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090120 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090213 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120220 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120220 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130220 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140220 Year of fee payment: 5 |
|
LAPS | Cancellation because of no payment of annual fees |