JP2006179798A - Printed-wiring board and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed-wiring board which has excellent adhesiveness, electrical connection and reliability by providing a solder pad structure having excellent strength and adhesiveness. <P>SOLUTION: On a solder pad 77U, a composite layer composed of an Ni layer 72 and a Pd layer 73 is formed, and solder 76α is provided on the composite layer. A structure of Ni layer 72, to Ni, to Sn alloy layer 75, to solder bump 76U results through reflow, where adhesiveness with the solder layer is improved by the Ni-Sn alloy layer 75 so as to enhance resistance to tensile and improving peeling strength. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a printed wiring board for mounting a semiconductor on which a semiconductor element is mounted and a method for manufacturing the same.

Generally, the outermost layer of the printed wiring board is provided with a solder resist layer in order to protect the conductor circuit. When forming a solder bump, a solder pad is formed by opening and exposing a part of the solder resist layer for connection to a conductor circuit. A solder bump is formed by printing a solder paste on a nickel layer and a gold layer on a portion to be a solder pad and performing reflow. As those prior arts, Japanese Patent Laid-Open No. 10-154876 has been proposed.
Japanese Patent Laid-Open No. 10-154876

However, as the opening diameter of the solder pad becomes smaller (for example, the opening diameter of the solder pad is 200 μm or less), the contact area between the solder pad and the solder bump becomes smaller, so that the adhesion is lowered. Therefore, it becomes easy to cause peeling of solder bumps.
Further, it is required to buffer the thermal stress rather than the conventional solder pad structure (nickel-gold). In the first place, when the thermal stress accompanying the expansion and contraction of the material due to heat is generated, the thermal stress is also applied to the solder bump. As the opening diameter of the solder pad becomes smaller, the thermal stress tends to concentrate on the solder bump. For this reason, when the thermal stress cannot be buffered at the solder bump and the solder pad, problems such as breakage or cracking of the solder bump (or solder layer) occur. As a result, electrical connectivity and reliability as a printed wiring board are degraded. In particular, in reliability tests under heat cycle conditions and under high temperature and high humidity, it has been difficult to ensure reliability as a long-term printed wiring board.

Furthermore, when lead-less solder is used for the solder bump, the toughness is lower than that of lead solder and stress is not absorbed inside, so that the tendency of the defect tends to become remarkable.

  The present invention has been made to solve the above-described problems, and the object of the present invention is to provide a print having excellent adhesion, electrical connectivity, and reliability by using a solder pad structure having excellent strength and adhesion. It is to propose a wiring board and a manufacturing method thereof.

As a result of inventor's earnest research, a solder pad in which a part of the solder resist layer is opened is formed, a composite layer is applied to the surface layer of the conductor circuit exposed from the solder pad, and the external connection is provided on the composite layer. A printed wiring board on which a solder bump or a solder layer is formed,
The composite layer is technically characterized by comprising a Ni layer (nickel layer) and a Pd layer (palladium layer).

Also, a solder pad in which a part of the solder resist layer is opened is formed, a composite layer is applied to the surface layer of the conductor circuit exposed from the solder pad, and a solder bump or solder layer for external connection is provided on the composite layer A printed wiring board on which is formed,
The composite layer includes a Ni layer and a Pd layer,
The solder bump or the solder layer is technically characterized by being made of solder containing no lead.

  The composite layer in the present invention is formed by laminating a Ni layer and a Pd layer in order from the conductor circuit side. That is, a composite layer composed of a Ni layer and a Pd layer is laminated on a conductor circuit from a solder pad, and a solder pad or a solder layer is formed thereon.

  The Pd layer (palladium layer) can reduce soldering phenomenon and the like. Therefore, as a result, the adhesiveness with the solder can be improved as compared with the conventional solder pad structure.

  The reason for this is that palladium formed by plating is less likely to cause defects such as non-deposition, and the surface ratio of the palladium layer is smaller than that of the Au layer (gold layer). For this reason, even when solder is mounted, it is less likely to cause inconvenience such as soldering. Also, solder bumps or solder layers of a desired size can be formed in the solder pads. Therefore, the desired size is obtained, and as a result, the adhesion between the solder bump or solder layer and the conductor circuit is hardly lowered.

  In addition, by using a palladium layer, it becomes easy to buffer thermal stress, and as a result, defects to solder bumps or solder layers can be reduced, so that electrical connectivity and reliability can be improved. is there.

  The reason is that the palladium layer is more rigid than gold. Therefore, thermal stress is absorbed in the Pd layer and buffered. Therefore, transmission of stress to the solder bump or solder layer by thermal stress is reduced. Therefore, it becomes difficult to cause damage to the solder bump or the solder layer. Therefore, the electrical connection caused by the solder bump or the solder layer hardly causes a problem, and reliability in a long period is ensured even if a reliability test is performed.

  By adopting this composite layer structure, electrical connectivity and reliability can be improved as compared with the conventional solder pad structure (nickel layer-gold layer).

  Further, when solder containing no lead (lead-free) is used in the solder bump or solder layer, the effect becomes remarkable. Lead-free solder is inferior to buffering thermal stress compared to lead-containing solder. In the first place, in lead-containing solder (for example, Sn / Pd = 6: 4), the stress in the solder is buffered against the generated thermal stress. This is because the contained lead absorbs stress. However, lead-free solder has a poor ability to buffer stress compared to lead-containing solder. Therefore, by providing a composite layer composed of a Ni layer and a Pd layer on the solder pad, the stress is buffered in the entire solder pad structure. Therefore, compared with the conventional solder pad structure (Ni layer-Au layer), the adhesiveness of the solder itself is better, the stress against thermal stress is easily buffered, and the formed solder bump or solder layer is damaged or cracked. It is possible to suppress such troubles. Therefore, electrical connectivity and reliability can be ensured as compared with a conventional solder pad structure in which lead-free solder is mounted.

  Also, a composite layer composed of a Ni layer and a Pd layer is provided on the conductor circuit on the solder pad, and a solder bump or solder layer is formed on the composite layer through reflow or the like. At that time, a structure of Ni layer- (Ni-Sn) alloy layer-solder layer or solder bump is formed on the conductor circuit as the solder pad. Here, the Ni—Sn alloy layer can improve the adhesion to the solder layer. That is, since the Ni—Sn alloy layer increases the rigidity, the resistance to tension is increased. As a result, the peel strength can be improved.

  This Ni—Sn alloy layer has an increased resistance to tension regardless of its size. That is, in this case, the Ni alloy layer can improve the peel strength regardless of the size of the solder pad.

A Ni layer, a Pd layer, or a noble metal layer may be formed as the composite layer. For example, nickel layer (Ni layer) -palladium layer (Pd layer) -gold layer (Au layer), nickel layer (Ni layer) -palladium layer (Pd layer)-, silver layer (Ag layer), etc. is there.
When these composite layers are provided and solder bumps are provided by reflowing on the composite layers, most of the Pd layer and the noble metal layer diffuse to the solder side. Therefore, a Ni—Sn alloy layer made of Ni and a solder composition metal is formed at the interface between the nickel layer and the solder bump.

Here, the Ni—Sn alloy layer can improve the adhesion to the solder layer. That is, since the Ni—Sn alloy layer increases the rigidity, the resistance to tension is increased. As a result, the peel strength can be improved.
This Ni—Sn alloy layer has an increased resistance to tension regardless of its size. That is, in this case, the Ni—Sn alloy layer can improve the peel strength regardless of the size of the solder pad.

  Examples of the Ni—Sn alloy layer include alloy layers containing Ni—Sn—Cu, Ni—Sn—Bi, and the like. These Ni—Sn alloy layers can improve the rigidity.

  By adjusting the thickness of the Ni—Sn alloy layer, the bonding strength between the nickel layer and the solder bump can be further increased, and the tensile strength can be further improved.

  The average thickness of the Ni—Sn alloy layer is more preferably 1.0 to 2.5 μm. It is because the rigidity of a Ni-Sn alloy layer is raised by making it in this range, As a result, tensile strength can be improved. In addition, the tensile strength can be improved regardless of the combination of metals other than Ni and Sn.

  Here, the average thickness is less than 1.0 μm. Alternatively, when the average thickness exceeds 2.5 μm, rigidity is secured as the Ni—Sn alloy layer, but since the rigidity is inferior to that within the range of the thickness of the Ni—Sn alloy layer, the tensile strength is reduced. The strength is also inferior.

  In addition, experiments have shown that the average thickness of the Ni—Sn alloy layer can be adjusted to 1.0 to 2.5 μm by adjusting the thickness of the intermediate layer that is a composite layer. That is, when the solder bump is formed, if the composite layer is a Ni layer, Pd layer or Ni layer, Pd layer, or noble metal layer, the Pd layer, Pd layer, or noble metal layer diffuses to form a Ni-Sn alloy layer. However, at this time, the thickness of the Ni—Sn alloy layer is adjusted by the thickness of the Pd layer. Therefore, adjusting the thickness of the Pd layer changes the thickness of the Ni—Sn alloy layer, and as a result, the rigidity of the Ni—Sn alloy layer changes and the tensile strength also changes.

  The Ni—Sn alloy layer is composed of any of the shapes of the particles selected from plate-like bodies, columnar bodies, and granular bodies. These may be a single configuration (for example, a stacked body in which only plate-like bodies are stacked), or may be combined with each other (for example, a plate-like body and a columnar body are mixed). Laminate). Among these, an alloy layer mainly composed of a plate-like body is desirable. The plate-like bodies are difficult to form a gap between the respective plate-like bodies and are easy to stack. Therefore, rigidity of the alloy layer mainly composed of a plate-like body is easily ensured. The strength is easily secured even with respect to the tensile strength with the solder. It is particularly desirable that the alloy layer is composed only of a plate-like body.

The Ni—Sn alloy layer is preferably an alloy layer composed of a ternary system (for example, Ni, Sn, Cu). These ternary alloy layers are likely to be uniformly mixed and have a uniform shape. Therefore, it is difficult to cause peeling in the alloy layer, and it is easy to ensure rigidity. In addition, the alloy layer is likely to have a plate-like particle shape, and the rigidity is easily increased.
Moreover, if the alloy layer which consists of a ternary system exists in the range of Sn: Cu: Ni = 30-90: 10-50: 1-30, rigidity will not fall easily. In particular, when a solder containing no lead (lead-free) is used in the solder bump or the solder layer, the stress generated by the thermal stress is easily buffered. Therefore, it becomes difficult to cause damage and cracks in the lead-free solder, and electrical connectivity and reliability are improved. In particular, in a Ni—Cu—Sn alloy layer having Sn of 40 to 70 wt%, the rigidity is most easily increased.

If the thickness of the Pd layer is set to 0.01 to 1.0 μm, the average thickness of the Ni—Sn alloy layer can be easily set to 1.0 to 2.5 μm.
Here, the Pd layer has a function of suppressing Ni diffusion and inhibiting formation of the Ni—Sn alloy layer.
For this reason, when the thickness of the Pd layer is less than 0.01 μm, Ni diffusion cannot be sufficiently suppressed, and the thickness of the Ni—Sn alloy layer is easily increased. In this case, the average thickness of the Ni alloy layer is likely to exceed 2.5 μm, which makes it difficult to improve the rigidity of the Ni—Sn alloy layer.

  On the other hand, if the Pd layer thickness exceeds 1.0 μm, Ni diffusion is suppressed, and formation of the Ni—Sn alloy layer is hindered. Therefore, the thickness of the Ni alloy layer can be easily reduced. In this case, the average thickness of the Ni—Sn alloy layer tends to be less than 0.01 μm, which makes it difficult to improve the rigidity of the Ni—Sn alloy layer.

  In particular, the thickness of the Pd layer is more preferably 0.03 to 0.2 μm. This is because the thickness of the Pd layer is within the range of 0.01 to 1.0 μm even if there is a local variation in thickness by being within this range. Therefore, the formed Ni—Sn alloy layer is easy to be within the above-mentioned desired range, and therefore the rigidity as the Ni—Sn alloy layer is increased.

The thickness of the Ni alloy layer can be controlled by the content of phosphorus (P) in the Pd layer, and the rigidity of the Pd layer can be increased.
The P content in the Pd layer is preferably 2 to 7 wt%. As a result, the formed Pd layer is less likely to be porous, the film is likely to be uniform, and the surface oxide film is less likely to be formed. Furthermore, the formed Pd layer is easily secured. This is because the formed Ni—Sn alloy layer is easily formed, and thus the rigidity of the Ni—Sn alloy layer is easily secured.

  Here, if the P content in the Pd layer is less than 2% or the P content in the Pd layer exceeds 7%, the Pd layer cannot be uniformly coated on the Ni layer, and the Pd layer remains porous. An oxide film is likely to be formed on the surface layer of the Pd layer, and even if solder is formed, the adhesion tends to be lowered. Moreover, the rigidity of the Pd layer itself may be lowered, and it becomes difficult to buffer the thermal stress. For this reason, stress may be concentrated on the solder bumps or the solder layer, which easily causes problems such as breakage or cracks in the solder. Further, when a reliability test is performed, it may be difficult to ensure long-term reliability.

  In addition, the Ni—Sn alloy layer formed after the solder is reflowed is likely to be thick, and as a result, the Ni—Sn alloy layer formed can perform its function, but it is difficult to improve the rigidity. It is. As a straightforward example, the average thickness of the Ni—Sn alloy layer may exceed 2.5 μm.

Furthermore, it is particularly desirable that the P content in the Pd layer be 4 to 6 wt%. By making the P content within the range, even if local variation occurs, the P content does not deviate significantly from 2 to 7 wt%. On the surface layer of the formed Pd layer, it is difficult to form an oxide film, and inconveniences such as repelling hardly occur even when solder is formed, and adhesion is ensured. Furthermore, the rigidity of the Pd layer itself is ensured, and it becomes easy to buffer the stress against thermal stress. For this reason, it is difficult to cause defects such as breakage and cracks in the solder formed on the Pd layer, and electrical connectivity and reliability are not deteriorated. Even when reliability tests on heat such as heat cycle conditions and high-temperature and high-humidity conditions are performed, deterioration of functions occurs slowly and it is easy to ensure reliability over a long period of time.
Further, the thickness of the Ni—Sn alloy layer formed through the solder reflow is within a desired range. As a result, it becomes easier to improve the rigidity of the Ni—Sn alloy layer.

  Here, the reason why a porous Pd film can be formed when an appropriate amount of P is contained in the Pd layer will be described with reference to FIG.

FIG. 15A shows a case where an appropriate amount of P is contained. Here, the Pd film is formed by electroless plating, and a hypophosphorous acid-based chemical solution is used as a reducing agent for the plating solution. As an example, sodium hypophosphite (NaH ₂ PO ₂ ) is used. First, hypophosphite ions (H ₂ PO ₂ ⁻ ) 63 are adsorbed on the nickel layer ((1) in FIG. 15A). Next, Ni serves as a catalyst to cause dehydrogenolysis (H ₂ PO ₂ − + 2H → Pd + 2H ⁺ ) to hypophosphite ions. Hydrogen atoms 65 generated by this dehydrogenative decomposition are adsorbed and activated on the Ni surface ((2) in FIG. 15A). Pd ions (Pd ²⁺ ) in the plating bath receive electrons from hydrogen on the Ni surface and are reduced to Pd metal (Pd ²⁺ + 2H → Pd + 2H ⁺ ) ((3) in FIG. 15A). The deposited Pd metal becomes a catalyst, and Pd is deposited on the Ni surface by the same mechanism ((4) in FIG. 15A). Here, P in Pd—P is obtained by coprecipitation of hypophosphorous acid as a reducing agent. Since hypophosphorous acid has a function of catalytically activating Ni, plating can be performed on the Ni surface layer without selectivity, that is, a dense Pd layer can be formed. Furthermore, at this time, by adjusting the concentration of hypophosphorous acid, the content of P can be adjusted in the film which is the Pd layer.

FIG. 15B shows a case of pure Pd not containing P. Here, the Pd film is formed by electroless plating treatment, and formic acid (HCOOH) containing no P as a reducing agent is used for the plating solution. First, hydrogen atoms 65 generated during the Ni plating reaction are adsorbed on the Ni surface ((1) in FIG. 15B). Next, when Pd ions in the plating bath come into contact with hydrogen on the Ni surface, the Pd ions are reduced to metal ((2) in FIG. 15B). Formic acid is decomposed into H ₂ and CO _{2 by} the influence of the Pd precipitation reaction ((3) in FIG. 15B). Pd ions are reduced to metal by scavenging electrons from hydrogen generated by the decomposition of formic acid ((4) in FIG. 15B). The Pd layer formed at this time uses formic acid as a reducing agent. However, during initial precipitation, formic acid cannot act as a reducing agent, so hydrogen on the Ni surface layer becomes a reducing agent. However, since a large amount of hydrogen does not exist in the Ni surface layer, a Pd plating layer that becomes a selective plating film, that is, a porous shape is formed.

  The quantification of each metal described above was performed by the energy dispersion method (EDS). In this method, various signals are generated by irradiating the surface of the material with an electron beam which is an excitation source of SEM (scanning electron microscope) or TEM (transmission electron microscope). Among them, the characteristic X-rays are mainly detected by a Si (Li) semiconductor detector, the number of electron-hole pairs proportional to the energy is created in the semiconductor, an electric signal is generated, amplified, analog, digital After conversion, an X-ray spectrum is obtained by identifying using a multi-channel analyzer, and element identification is quantitatively analyzed from the peak amount based on the peak energy. An energy dispersive X-ray analyzer (model JED-2140 manufactured by JEOL Ltd.) was used for the measurement and quantification. The formed metal layer was directly irradiated to carry out quantitative measurement of the metal.

  An anticorrosion layer can also be provided on Pd of the composite layer. This is because the provision of the corrosion-resistant layer causes the intermediate layer to function to promote the formation of the Ni—Sn alloy layer on the Ni layer described above.

  Here, the corrosion resistant layer is preferably formed of at least one kind of noble metals such as Au, Ag, Pt, or Sn. This is because the use of these metals facilitates the formation of the Ni alloy layer.

  Moreover, you may form a corrosion-resistant layer through two steps by displacement plating, electroless plating, displacement plating, or electroless plating with the same metal. As a result, a metal film that is not affected by the lower Ni layer can be formed, the corrosion resistance is improved, and the influence of a decrease in the shape and function of the solder bumps can be suppressed.

  It was also found that the corrosion-resistant layer, especially made of Au, has different solder pads formed depending on the ratio, which also improves the solder pad's corrosion resistance, adhesion, solder bump shape, and function.

  The thickness of the Pd layer is preferably in the range of 0.01 to 1.0 μm. In particular, it is good to form in the range of 0.03-0.7 micrometer. When the thickness of the Pd layer is less than 0.01 μm, formation of the Ni—Sn alloy layer is not promoted. For this reason, there are places where the Ni—Sn alloy layer is not formed even locally, so that it is difficult to improve the rigidity of the Ni—Sn alloy layer, and as a result, the peel strength of the Ni—Sn alloy layer is also difficult to improve. Because. Conversely, if the thickness of the Pd layer exceeds 1 μm, the thickness may impede the promotion of the formation of the Ni—Sn alloy layer. For this reason, there are places where the Ni—Sn alloy layer is not formed even locally, so that it is difficult to improve the rigidity of the Ni—Sn alloy layer, and as a result, the peel strength of the Ni—Sn alloy layer is also difficult to improve. Because.

The Ni layer constituting the composite layer in the present invention is preferably formed of an alloy metal containing Ni—Cu, Ni—P, Ni—Cu—P or the like.
In particular, it is good to form with the alloy metal of Ni-P and Ni-Cu-P. In other words, it is desirable that the Ni layer contains P (phosphorus). The reason for this is that even if irregularities are formed on the surface of the conductor circuit, the irregularities are offset and a film having a flat surface layer can be formed. In addition, when formed by plating, the formed Ni layer is unlikely to cause formation abnormality due to non-precipitation, reaction stoppage, and the like. In addition, the formation of the Pd layer formed on the Ni layer can be promoted, and the Pd layer is not formed or abnormally formed. Therefore, the formed Pd layer becomes a desired one, and rigidity can be ensured even as a composite layer.

  The thickness of the Ni layer is desirably formed in the range of 2 to 10 μm. When the thickness of the Ni layer is less than 2 μm, or the thickness of the Ni layer exceeds 10 μm, problems such as non-formation or formation abnormality of the Pd layer formed on the Ni layer may occur.

  It is particularly desirable that the content of P (phosphorus) in the Ni layer be 0.5 to 5.0 wt%. If the P content is less than 0.5 wt% or exceeds 5.0 wt%, the formation of the Ni layer tends to be hindered. Moreover, it may be difficult to promote the formation of the Pd layer on the Ni layer. As a result, the formed Pd layer may not be formed or abnormally formed, and the rigidity of the Pd layer may not be ensured. is there. For this reason, electrical connectivity and reliability may not be ensured.

  Further, it is more preferable that the content of P (phosphorus) in the Ni layer is lower than the content of P (phosphorus) in the Pd layer. As a result, the Pd layer covers the Ni layer, and peeling at the interface between the Pd layer and the Ni layer is less likely to occur. As a result, the electrical connectivity and reliability due to defects at the solder pad interface are not reduced.

  As the solder used in the present invention, two-component solder, three-component solder, or four-component or more multi-component solder can be used. As the metal contained in these compositions, Sn, Ag, Cu, Pb, Sb, Bi, Zn, In, or the like can be used.

  Examples of the two-component solder include Sn / Pb, Sn / Sb, Sn / Ag, Sn / Cu, and Sn / Zn. Also, as the ternary solder, Sn / Ag / Cu, Sn / Ag / Sb, Sn / Cu / Pb, Sn / Sb / Cu, Sn / Ag / In, Sn / Sb / In, Sn / Ag / Bi Sn / Sb / Bi or the like can be used. These three-component solders may be those in which the three components are 10 wt% or more, or may be solder in which the main two components occupy 95 wt% or more and the remaining is one component. (For example, a three-component solder in which the total of Sn and Ag is 97.5 wt%, and the balance is Cu)

  Examples of the lead-free (lead-free) solder include Sn / Ag solder, Sn / Bi solder, Sn / Zn solder, and Sn / Cu solder. These solders are inferior in stress buffering in the solder against thermal stress compared to Sn / Pb. Therefore, stress tends to remain in the solder.

  In addition, a multi-component solder composed of four or more components may be used. Examples of the multi-component solder include Sn / Ag / Cu / Sb and Sn / Ag / Cu / Bi. You may use the solder which adjusted alpha dose.

  Any material that can form a Ni—Sn alloy layer at the interface between the solder component and the Ni layer can be used. This Ni—Sn alloy layer increases the rigidity, and as a result, the peel strength of the solder can be improved.

  Among these, a Ni—Sn alloy layer made of Ni—Sn—Cu is desirable. The rigidity is increased by using this alloy. The alloy layer may contain Ag, Sb, Bi, Zn, etc. in addition to the three types of Ni, Sn, and Cu. Even if these are contained, the rigidity of the Ni—Sn—Cu alloy layer itself is not deteriorated. However, when the content is increased as compared with any of Sn, Ni, and Cu, rigidity may be deteriorated.

  Moreover, as melting | fusing point of these solders, it is desirable that it is between 150-350 degreeC. Even if the melting point of the solder is lower than 150 ° C., conversely, even if the melting point of the solder is 350 ° C. or higher, it may be difficult to form the Ni—Sn alloy layer. That is, even if the temperature is low, it is difficult to form a Ni—Sn alloy, and if the temperature is high, Ni is separated, which makes it difficult to form a Ni—Sn alloy. Therefore, a Ni—Sn alloy is likely to be formed at the above temperature.

  In the printed wiring board of the present invention, a roughened layer can be formed on the conductor circuit on the surface layer of the printed wiring board subjected to the conductor circuit. The average roughness (Ra) is preferably 0.02 to 7 μm. The roughened layer improves the adhesion between the conductor circuit and the solder resist layer. In particular, the average roughness in a desirable range is 1 to 5 μm. If it is the range, desired adhesiveness will be obtained irrespective of a composition, thickness, etc. of a soldering resist layer.

  As a method of forming the roughened layer, there are a method of forming an electroless plating such as an alloy layer made of Cu-Ni-P, a method of forming by etching with a cupric complex and an organic acid salt, and a method of forming by oxidation and reduction. . In some cases, the roughened layer may be covered with Sn, Zn, or the like.

The outermost conductor circuit is covered and protected with a solder resist layer.
As the solder resist layer, various resins can be used, and a thermosetting resin, a thermoplastic resin, a photocurable resin, a resin (meth) acrylated in a part of the thermosetting resin, or two or more of these were used. It may be a resin composite. Examples of the resin include an epoxy resin, a phenol resin, a polyimide resin, a phenoxy resin, and an olefin resin.

  For the formation of the solder resist layer, a solution whose viscosity is adjusted in advance and applied onto the varnish is applied. Or what was made into the film-form made into the semi-hardened state (B stage) is affixed. Or after apply | coating, you may carry out by the method of sticking a film. Moreover, you may form in multiple layers by two or more types of different resin.

  A part of the solder resist layer is opened to provide a solder pad. At this time, as an opening method, a method in which a mask on which an opening pad is drawn is placed on a solder resist layer and exposed and developed (photoresist method), carbon dioxide laser, excimer laser, YAG laser, etc. Any of the methods of opening with a laser can be used. Alternatively, the solder pad opening may be formed by direct drawing.

For solder resists formed through exposure and development, for example, bisphenol A type epoxy resin, bisphenol A type epoxy resin acrylate, novolac type epoxy resin, and novolak type epoxy resin acrylate are cured with amine curing agents or imidazole curing agents. Can be used.
In particular, when forming solder bumps by providing openings in the solder resist layer, it is preferable that the solder resist layer is made of “novolac type epoxy resin or acrylate of novolac type epoxy resin” and contains “imidazole curing agent” as a curing agent.

  Next, a solder-resist layer is formed on the conductor circuit. The thickness of the solder resist layer in the present invention is preferably 5 to 40 μm. If it is too thin, it will not function as a solder dam, and if it is too thick, it will be difficult to open, and it will contact the solder body and cause cracks in the solder body.

  The solder resist layer having such a configuration has an advantage that lead migration (a phenomenon in which lead ions diffuse in the solder resist layer) is small. In addition, this solder resist layer is a resin layer obtained by curing an acrylate of a novolak type epoxy resin with an imidazole curing agent, has excellent heat resistance and alkali resistance, and does not deteriorate even at a temperature at which the solder melts (around 200 ° C). It is not decomposed by a strongly basic plating solution such as plating, palladium plating or gold plating.

  However, since such a solder resist layer is made of a resin having a rigid skeleton, peeling is likely to occur. The roughened layer is effective for preventing such peeling.

As the acrylate of the novolac type epoxy resin, an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolac with acrylic acid, methacrylic acid or the like can be used.
The imidazole curing agent is desirably liquid at 25 ° C. This is because uniform mixing is possible if it is liquid.

  Examples of such liquid imidazole curing agents include 1-benzyl-2-methylimidazole (product name: 1B2MZ), 1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN), 4-methyl-2- Ethylimidazole (product name: 2E4MZ) can be used.

  The amount of the imidazole curing agent added is desirably 1 to 10% by weight based on the total solid content of the solder resist composition. This is because it is easy to mix uniformly if the added amount is within this range.

It is desirable that the pre-curing composition of the solder resist uses a glycol ether solvent as a solvent.
The solder resist layer using such a composition does not generate free oxygen and does not oxidize the copper pad surface. In addition, it is less harmful to the human body.

As such a glycol ether solvent, at least one selected from the following structural formulas, particularly preferably diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG) is used. This is because these solvents can completely dissolve benzophenone and Michler's ketone as reaction initiators by heating at about 30 to 50 ° C.
_{CH 3 O- (CH 2 CH 2} O) n -CH 3 (n = 1~5)
The glycol ether solvent is preferably 10 to 40 wt% with respect to the total weight of the solder resist composition.

In addition to the solder resist composition described above, various antifoaming agents and leveling agents, thermosetting resins for improving heat resistance and base resistance and providing flexibility, and photosensitive for improving resolution. A monomer can be added.
For example, the leveling agent is preferably made of an acrylic ester polymer. Further, Irgacure I907 manufactured by Ciba Geigy is preferable as the initiator, and DETX-S manufactured by Nippon Kayaku is preferable as the photosensitizer.
Furthermore, you may add a pigment | dye and a pigment to a soldering resist composition. This is because the wiring pattern can be concealed. It is desirable to use phthalocyanine green as this dye.

  As the thermosetting resin as an additive component, a bisphenol type epoxy resin can be used. This bisphenol type epoxy resin includes a bisphenol A type epoxy resin and a bisphenol F type epoxy resin. When the basic resistance is important, the former is required when the viscosity is reduced (when the coating property is important). The latter is better.

  As the photosensitive monomer as an additive component, a polyvalent acrylic monomer can be used. This is because the polyvalent acrylic monomer can improve the resolution. For example, polyvalent acrylic monomers such as DPE-6A manufactured by Nippon Kayaku or R-604 manufactured by Kyoeisha Chemical are desirable.

  Moreover, these solder resist compositions are 0.5-10 Pa.s at 25 degreeC, More preferably, 1-10 Pa.s is good. This is because the viscosity is easy to apply with a roll coater. After forming the solder resist, an opening is formed. The opening is formed by exposure and development processing.

After forming the solder-resist layer, a composite layer composed of a Ni layer-Pd layer is formed in the opening of the solder resist layer.
As an example, a metal layer containing Ni is formed by electroless plating on a conductor circuit exposed from a solder pad. Examples of the composition of the plating solution are: nickel sulfate 4.5 g / l, sodium hypophosphite 25 g / l, sodium citrate 40 g / l, boric acid 12 g / l, thiourea 0.1 g / l (PH = 11). is there. The degreasing solution is used to clean the solder resist opening and the surface, and a catalyst such as palladium is applied to the conductor exposed in the opening, activated, and then immersed in a plating solution to form a nickel plating layer. It was.

After forming the nickel layer, a Pd layer is formed on the Ni layer.
If necessary, a corrosion resistant layer is formed on the Pd layer with a metal selected from Au, Ag, Pt, and Sn. In particular, it is preferable to form with gold. In some cases, the same metal may be formed in two layers through displacement plating and electroless plating. The thickness is desirably 0.01 to 2 μm.

  After the opening is provided with a corrosion-resistant layer to form a solder pad, the opening is filled with a solder paste which is a two-component solder, a three-component solder or a multi-component solder by printing. Thereafter, nitrogen reflow at a temperature of 250 to 350 ° C. is passed to fix the solder bumps to the solder pads in the openings. Solder that does not contain lead (lead-free) may be used.

[Example 1]
A. Preparation of resin film of interlayer resin insulation layer 30 parts by weight of bisphenol A type epoxy resin (epoxy equivalent 469, Epicoat 1001 manufactured by Yuka Shell Epoxy), cresol novolac type epoxy resin (epoxy equivalent 215, manufactured by Dainippon Ink and Chemicals, Inc.) N-673) 40 parts by weight, triazine structure-containing phenol novolac resin (phenolic hydroxyl group equivalent 120, Phenolite KA-7052 made by Dainippon Ink & Chemicals, Inc.), ethyl diglycol acetate 20 parts by weight, solvent naphtha 20 parts by weight The solution was dissolved by heating with stirring to 15 parts by weight, and 15 parts by weight of terminal epoxidized polybutadiene rubber (Danalex R-45EPT manufactured by Nagase Kasei Kogyo Co., Ltd.) and pulverized 2-phenyl-4,5-bis (hydroxymethyl) imidazole 1.5 Part by weight, fine Crushed silica 2 parts by weight, was added 0.5 part by weight of silicon antifoaming agent to prepare an epoxy resin composition.
The obtained epoxy resin composition was applied on a PET film having a thickness of 38 μm using a roll coater so that the thickness after drying was 50 μm, and then dried at 80 to 120 ° C. for 10 minutes, whereby an interlayer resin was obtained. A resin film for an insulating layer was produced.

B. Preparation of Resin Filler 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell Co., Ltd., molecular weight: 310YL983U), the average particle diameter coated with a silane coupling agent on the surface is 1.6 μm, and the maximum particle diameter is 15 μm The following SiO ₂ spherical particles (manufactured by Adtech, CRS 1101-CE) 170 parts by weight and leveling agent (San Nopco, Perenol S4) 1.5 parts by weight are placed in a container and mixed by stirring to give a viscosity of 23 ± 1. A resin filler having a viscosity of 44 to 49 Pa · s was prepared at ° C. As the curing agent, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) was used.

C. Production of multilayer printed wiring board (1) Copper-clad laminate 30A in which 18 μm copper foil 32 is laminated on both surfaces of an insulating substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.8 mm As a starting material (FIG. 2A). First, the copper-clad laminate 30A was drilled, subjected to electroless plating, and etched into a pattern, thereby forming lower layer conductor circuits 34 and through holes 36 on both sides of the substrate (FIG. 2B). ).

(2) The substrate on which the through hole and the lower conductor circuit are formed is washed with water and dried, and then an aqueous solution containing NaOH (10 g / l), NaClO ₂ (40 g / l), Na ₃ PO ₄ (6 g / l) is blackened. A lower layer conductor circuit including a through hole 36, which is subjected to a blackening treatment as an oxidation bath (oxidation bath) and a reduction treatment using an aqueous solution containing NaOH (10 g / l) and NaBH ₄ (6 g / l) as a reduction bath Roughened surfaces 36α and 34α were formed on the entire surface of 34 (FIG. 2C).

(3) After preparing the resin filler described in the above B, within 24 hours after preparation by the following method, within the through hole 36 and the lower conductor circuit non-formed part on one side of the substrate and the outer edge of the lower conductor circuit A layer of the resin filler 40 was formed on the part. That is, a resin filling mask having a plate having an opening corresponding to a non-formation portion of the through hole 36 and the lower conductor circuit 34 is placed on the substrate, and a squeegee is used to form a concave portion in the through hole. The resin filler 40 was filled in the conductor circuit non-formation part and the outer edge part of the lower layer conductor circuit, and dried under conditions of 100 ° C./20 minutes (FIG. 2D).

(4) One side of the substrate after the processing of (3) is subjected to belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku), and the outer edge of the lower conductor circuit 34 and the land of the through hole 36 are removed. Polishing was performed so that the resin filler 40 did not remain on the outer edge, and then buffing was performed on the entire surface (including the land surface of the through hole) of the lower layer conductor circuit in order to remove scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate. Next, heat treatment was performed at 100 ° C. for 1 hour and 150 ° C. for 1 hour to cure the resin filler 40 (FIG. 3A).
In this way, the surface layer portion of the resin filler 40 and the surface of the lower conductor circuit 34 formed in the through hole 36 and the lower conductor circuit non-forming portion are flattened, and the resin filler and the side surface of the lower conductor circuit are roughened. A substrate in which the inner wall surface of the through hole 36 and the resin filler 40 were firmly adhered to each other through the roughened surface was obtained. That is, by this step, the surface of the resin filler and the surface of the lower conductor circuit become substantially flush.

(5) After washing the substrate with water and acid degreasing, soft etching is performed, and then an etching solution is sprayed on both surfaces of the substrate to spray the surface of the lower conductor circuit 34, the land surface of the through hole 36, and the inner wall. As a result, a roughened surface 36β was formed on the entire surface of the lower conductor circuit 34 (FIG. 3B). As an etchant, an etchant (MEC Etch Bond, manufactured by MEC Co.) consisting of 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride was used.

(6) A resin film for an interlayer resin insulation layer slightly larger than the substrate prepared in A is placed on both sides of the substrate on the substrate, and temporarily bonded under the conditions of pressure 0.4 MPa, temperature 80 ° C., and pressure bonding time 10 seconds. After cutting, the interlayer resin insulation layer 50 was further formed by sticking using a vacuum laminator apparatus by the following method (FIG. 3C). That is, a resin film for an interlayer resin insulation layer was subjected to main pressure bonding on a substrate under conditions of a degree of vacuum of 67 Pa, a pressure of 0.4 MPa, a temperature of 80 ° C., and a pressure bonding time of 60 seconds, and then thermally cured at 170 ° C. for 30 minutes.

(7) Next, with a CO ₂ gas laser with a wavelength of 10.4 μm, a top hat mode with a beam diameter of 4.0 mm through a mask in which a 1.2 mm thick through hole is formed on the interlayer resin insulation layer A via hole opening 50a having a diameter of 80 μm was formed in the interlayer resin insulating layer 50 under the conditions of a pulse width of 8.0 μsec, a mask through-hole diameter of 1.0 mm, and one shot (FIG. 3D).

(8) The substrate on which the via hole opening (50a) is formed is immersed in an 80 ° C. solution containing 60 g / l permanganic acid for 10 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer (50). Thus, the surface of the interlayer resin insulating layer 50 including the inner wall of the via hole opening 50a was roughened (FIG. 3E).

(9) Next, the substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water. Furthermore, a catalyst catalyst was attached to the surface of the interlayer resin insulating layer 2 and the inner wall surface of the via hole opening by applying a palladium catalyst to the surface of the substrate that had been roughened (roughening depth: 3 μm). (Not shown). That is, the substrate was immersed in a catalyst solution containing palladium chloride (PbCl ₂ ) and stannous chloride (SnCl ₂ ), and the catalyst was applied by depositing palladium metal.

(10) Next, a substrate provided with a catalyst is immersed in an electroless copper plating aqueous solution having the following composition to form an electroless copper plating film having a thickness of 0.6 to 3.0 μm on the entire rough surface. A substrate having an electroless copper plating film 52 formed on the surface of the interlayer resin insulation layer 50 including the inner wall of the via hole opening (50a) was obtained (FIG. 4A).
[Electroless plating aqueous solution]
NiSO ₄ 0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 100 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at a liquid temperature of 34 ° C

(11) A commercially available photosensitive dry film is attached to the substrate on which the electroless copper plating film 52 is formed, a mask is placed, exposed at 100 mJ / cm ² , and developed with a 0.8% aqueous sodium carbonate solution. Thus, a plating resist 54 having a thickness of 20 μm was provided (FIG. 4B).

(12) Next, the substrate was washed with 50 ° C. water and degreased, washed with 25 ° C. water, further washed with sulfuric acid, and then subjected to electrolytic plating under the following conditions.
[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
(Manufactured by Atotech Japan, Kaparaside GL)
[Electrolytic plating conditions]
Current density 1 A / dm ²
Time 65 minutes Temperature 22 ± 2 ℃
An electrolytic copper plating film 56 having a thickness of 20 μm was formed on a portion where the plating resist 54 was not formed (FIG. 4C).

(13) Further, after the plating resist 3 is peeled and removed with 5% KOH, the electroless copper plating film 52 under the plating resist 54 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. The upper layer conductor circuit 58 (including the via hole 60) was formed (FIG. 4D).

(14) Next, the same processing as in the above (5) was performed to form roughened surfaces 60α and 58α on the surfaces of the via hole 60 and the upper conductor circuit 58 (FIG. 5A).
(15) By repeating the steps (6) to (14) above, an upper-layer conductor circuit 158 and an interlayer insulating layer 150 having a via hole 160 were formed to obtain a multilayer wiring board (FIG. 5B). ).

(16) Next, a photosensitizing agent obtained by acrylating 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight: 4000), 80% by weight of bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) dissolved in methyl ethyl ketone, 15.0 parts by weight, imidazole curing agent (Shikoku Kasei Co., Ltd., trade name: 2E4MZ-CN) 1.6 parts by weight, photofunctional monomer bifunctional acrylic monomer (Nippon Kayaku Co., Ltd., trade name: R604) 4.5 parts by weight, also polyvalent acrylic monomer ( Kyoei Chemical Co., Ltd., trade name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (San Nopco, S-65) Take 1 part by weight in a container, stir and mix to prepare a mixed composition. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photopolymerization initiator for this mixed composition, as a photosensitizer A solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C. was obtained by adding 0.2 parts by weight of Michler ketone (manufactured by Kanto Chemical Co., Inc.). The viscosity measurements, B-type viscometer (Tokyo Keiki Co., DVL-B type) when at 60min ^-1 rotor No. In the case of 4, 6 min ⁻¹ , the rotor No. 3 according.

(17) Next, the solder resist composition 70 is applied to both surfaces of the multilayer wiring board in a thickness of 30 μm (FIG. 5C), and dried under conditions of 70 ° C. for 20 minutes and 70 ° C. for 30 minutes. After the treatment, a photomask having a thickness of 5 mm on which the pattern of the opening of the solder resist was drawn was brought into close contact with the solder resist layer, exposed to 800 mJ / cm ² of ultraviolet light, developed with a DMTG solution, and a diameter of 150 μm. The opening 71 was formed (FIG. 6A).
Further, heat treatment was performed under conditions of 100 ° C. for 1 hour and 150 ° C. for 3 hours to cure the solder resist layer, thereby forming a solder resist layer 14 having an opening and a thickness of 20 μm. A commercially available solder resist composition can also be used as the solder resist composition.

(18) Next, the substrate on which the solder resist layer 14 is formed is made of nickel chloride (2.3 × 10 ⁻¹ mol / l), sodium hypophosphite (2.8 × 10 ⁻¹ mol / l), A nickel plating layer 72 was formed in the opening 71 by dipping in an electroless nickel plating solution containing sodium acid (1.6 × 10 ⁻¹ mol / l) at pH = 4.5 for 20 minutes (FIG. 6B )). In Example 1, the thickness of the nickel plating layer 72 was set to be 2 to 10 μm, and P was contained in an amount of 0.5 to 5 wt%.

(19) Next, the substrate was palladium chloride 1.0 × 10 ⁻² mol / l, ethylenediamine 8.0 × 10 ⁻² mol / l, sodium hypophosphite 6.0 × 10 ⁻² mol / l, A 0.08 μm thick palladium layer 73 was formed on the nickel plating layer 72 by immersing in an electroless palladium plating solution having a pH of 8 and a temperature of 55 ° C. with 30 mg / l of thiodiglycolic acid (FIG. 7). (A)). In Example 1, the thickness of the palladium layer 73 was set to be 0.01 to 1.0 μm, and P was contained in an amount of 2 to 7 wt%.

(20) The solder paste 76α was printed on the solder pads 77U and 77D in the opening 71 of the solder resist layer 70 (FIG. 7B). FIG. 8A shows an enlarged view of the solder pad 77U surrounded by a circle A in FIG. 7B. The solder pad 77U is composed of two composite layers of a nickel plating layer 72 and a palladium layer 73 that are sequentially formed on the conductor circuit 158.

(21) Next, solder bumps 76U and 76D were formed by reflowing in a nitrogen atmosphere at 250 ° C. (FIG. 1). FIG. 8B shows an enlarged view of the solder pad 77U surrounded by a circle B in FIG. During this reflow, most of the palladium layer 73 is diffused toward the solder bumps 76U and 76D, and as shown in FIGS. 1 and 8B, at the interface between the nickel plating layer 72 and the solder bumps 76U and 76D, A Cu—Ni—Sn alloy layer 75 which is a Ni layer alloy layer is formed. Here, in Example 1, the thickness of the nickel plating layer 72 is set to be 2 to 10 μm, P is contained in an amount of 0.5 to 5 wt% lower than the P concentration of the palladium layer, and the palladium layer 73 is set to 0 The average thickness of the Cu—Ni—Sn alloy layer 75 was adjusted within the range of 1.0 to 2.5 μm by setting it to be 0.01 μm to 1.0 μm and containing 2 to 7 wt% of P.

[Example 1-1-1]
In Example 1-1-1, Cu: 0.5 wt%, Ag: 3.5 wt%, Sn: 95 wt% alloy was used as the solder constituting the solder bump. The Ni layer was set to 5 μm in thickness and the P content was 1.2 wt%, and the Pd layer was set to 0.5 μm in thickness and the P content was 5 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.5 μm. Electron micrographs of the nickel layer, the Cu—Ni—Sn alloy layer, and the solder of Example 1-1-1 are shown in FIGS. The left side electron micrograph (× 20K) in FIG. 16 is Example 1-1-1. In the electron micrographs on the left side in FIG. 17 and the left side in FIG. 18, the magnification (× 100K) is further enlarged. Here, the right side in FIGS. 16, 17, and 18 is an electron micrograph of Comparative Example 1-1-1 of a Pd layer that does not contain P, which will be described later. Here, the lower side is the nickel layer, the upper side is the solder, and the Cu—Ni—Sn alloy layer is present at the interface between the nickel layer and the solder layer. From the electron micrograph on the left side of FIG. 16, it can be seen that in Example 1, the Cu—Ni—Sn alloy layer is continuous, that is, has a small undulation and is formed on the surface of the Ni layer. Further, it can be seen from the electron micrographs on the left side of FIGS. 17 and 18 that the magnification is increased that Ag particles are uniformly arranged on the surface of the Cu—Ni—Sn alloy layer via the Sn skin layer. The left side of FIG. 19 is a transmission electron micrograph of Example 1-1-1. From this electron micrograph, it can be seen that the Cu—Ni—Sn alloy layer is plate-shaped, that is, formed in parallel along the nickel layer.

[Example 1-1-2]
In Example 1-1-2, Cu: 0.5 wt%, Ag: 3.5 wt%, and Sn: 95 wt% alloy were used as the solder constituting the solder bump, as in Example 1-1-1. And Ni layer was set to the same thickness as Example 1-1-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.01 μm and a P content of 2 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.8 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1 with reference to the electron micrograph on the left side of FIG.

[Example 1-1-3]
In Example 1-1-3, Cu: 0.5 wt%, Ag: 3.5 wt%, and Sn: 95 wt% alloy were used as the solder constituting the solder bump, as in Example 1-1-1. And Ni layer was set to the same thickness as Example 1-1-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.01 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.8 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1 with reference to the electron micrograph on the left side of FIG.

[Example 1-1-4]
In Example 1-1-4, Cu: 0.5 wt%, Ag: 3.5 wt%, and Sn: 95 wt% alloy were used as the solder constituting the solder bump, as in Example 1-1-1. And Ni layer was set to the same thickness as Example 1-1-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 1.0 μm and a P content of 2 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1 with reference to the electron micrograph on the left side of FIG.

[Example 1-1-5]
In Example 1-1-3, Cu: 0.5 wt%, Ag: 3.5 wt%, and Sn: 95 wt% alloy were used as the solder constituting the solder bump, as in Example 1-1-1. The Ni layer was set to a thickness of 10 μm and a P content of 0.5 wt%. On the other hand, the Pd layer was set to a thickness of 1.0 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1 with reference to the electron micrograph on the left side of FIG.

[Example 1-1-6]
In Example 1-1-6, Cu: 0.5 wt%, Ag: 3.5 wt%, and Sn: 95 wt% alloy were used as the solder constituting the solder bump, as in Example 1-1-1. The Ni layer was set to a thickness of 10 μm and a P content of 5 wt%. On the other hand, the Pd layer was set to a thickness of 0.01 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.7 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1 with reference to the electron micrograph on the left side of FIG.

[Example 1-2-1]
In Example 1-1-1 to Example 1-1-6, leadless Cu / Ag / Sn solder was used as the solder constituting the solder bump. In contrast, in Example 1-2-1 to Example 1-2-6, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder bump. The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.5 μm and a P content of 5 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1 with reference to the electron micrograph on the left side of FIG.

[Example 1-2-2]
In Example 1-2-2, as the solder constituting the solder bump, lead solder of Sn: Pb = 63: 37 (wt%) was used as in Example 1-2-1. And the Ni layer was set to the same thickness of 5 μm and P content 1.2 wt% as in Example 1-2-1. On the other hand, the Pd layer was set to a thickness of 0.01 μm and a P content of 2 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.8 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1 with reference to the electron micrograph on the left side of FIG.

[Example 1-2-3]
In Example 1-2-3, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder bump, as in Example 1-2-1. And the Ni layer was set to the same thickness of 5 μm and P content 1.2 wt% as in Example 1-2-1. On the other hand, the Pd layer was set to a thickness of 0.01 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.8 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1 with reference to the electron micrograph on the left side of FIG.

[Example 1-2-4]
In Example 1-2-4, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder bump, as in Example 1-2-1. And the Ni layer was set to the same thickness of 5 μm and P content 1.2 wt% as in Example 1-2-1. On the other hand, the Pd layer was set to a thickness of 1.0 μm and a P content of 2 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1 with reference to the electron micrograph on the left side of FIG.

[Example 1-2-5]
In Example 1-2-5, as the solder constituting the solder bump, lead solder of Sn: Pb = 63: 37 (wt%) was used as in Example 1-2-1. The Ni layer was set to a thickness of 10 μm and a P content of 0.5 wt%. On the other hand, the Pd layer was set to a thickness of 1.0 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1 with reference to the electron micrograph on the left side of FIG.

[Example 1-2-6]
In Example 1-2-6, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder bump, as in Example 1-2-1. The Ni layer was set to a thickness of 10 μm and a P content of 5 wt%. On the other hand, the Pd layer was set to a thickness of 0.01 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33, and the thickness was adjusted to 1.7 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1 with reference to the electron micrograph on the left side of FIG.

[Example 1-3-1]
In Example 1-3-1 to Example 1-3-6, as in the case of Example 1-1-1 to Example 1-1-6, as the solder constituting the solder bump, Cu: 0.5 wt%, An alloy of Ag: 3.5 wt% and Sn: 95 wt% was used. And Ni layer was set to the same thickness as Example 1-1-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.009 μm and a P content of 8 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 45: 13, and the thickness was adjusted to 2.5 μm. In Example 1-3-1, the Cu—Ni—Sn alloy layer is columnar, that is, along the nickel layer, as shown in the electron micrograph on the right side of FIG. Columnar alloy crystals are formed vertically.

[Example 1-3-2]
In Example 1-3-2, Cu: 0.5 wt%, Ag: 3.5 wt%, and Sn: 95 wt% alloy were used as the solder constituting the solder bump, as in Example 1-3-1. And Ni layer was set to the same thickness as Example 1-3-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.008 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 45: 13, and the thickness was adjusted to 2.5 μm. The Ni—Sn alloy layer was formed in a columnar shape as in Example 1-3-1.

[Example 1-3-3]
In Example 1-3-3, Cu: 0.5 wt%, Ag: 3.5 wt%, Sn: 95 wt% alloy was used as the solder constituting the solder bump, as in Example 1-3-1. And Ni layer was set to the same thickness as Example 1-3-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.009 μm and a P content of 1 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 45: 13, and the thickness was adjusted to 2.5 μm. The Ni—Sn alloy layer was formed in a columnar shape as in Example 1-3-1.

[Example 1-3-4]
In Example 1-3-4, Cu: 0.5 wt%, Ag: 3.5 wt%, and Sn: 95 wt% alloy were used as the solder constituting the solder bump, as in Example 1-3-1. And Ni layer was set to the same thickness as Example 1-3-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 2.0 μm and a P content of 2 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 66: 29: 5, and the thickness was adjusted to 1.3 μm. The Ni—Sn alloy layer was formed as a granular body at the interface of the nickel layer.

[Example 1-3-5]
In Example 1-3-5, Cu: 0.5 wt%, Ag: 3.5 wt%, and Sn: 95 wt% alloy were used as the solder constituting the solder bump, as in Example 1-3-1. The Ni layer was set to a thickness of 10 μm and a P content of 0.5 wt%. On the other hand, the Pd layer was set to a thickness of 2.0 μm and a P content of 5 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 66: 29: 5, and the thickness was adjusted to 1.3 μm. The Ni—Sn alloy layer was formed as a granular body (granular crystal) at the interface of the nickel layer.

[Example 1-3-6]
In Example 1-3-6, Cu: 0.5 wt%, Ag: 3.5 wt%, and Sn: 95 wt% alloy were used as the solder constituting the solder bump, as in Example 1-3-1. The Ni layer was set to a thickness of 10 μm and a P content of 5 wt%. On the other hand, the Pd layer was set to a thickness of 2.0 μm and a P content of 9 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 66: 29: 5, and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed as a granular body at the interface of the nickel layer.

[Example 1-4-1]
In Example 1-4-1 to Example 1-4-6, as in Example 1-2-1 to Example 1-2-6, Sn: Pb = 63: 37 (as the solder constituting the solder bump) wt%) lead solder. And the Ni layer was set to the same thickness of 5 μm and P content 1.2 wt% as in Example 1-2-1. On the other hand, the Pd layer was set to a thickness of 0.009 μm and a P content of 8 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 2.5 μm. The Ni—Sn alloy layer was formed in a columnar shape as in Example 1-3-1.

[Example 1-4-2]
In Example 1-4-2, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder bump, as in Example 1-4-1. And the Ni layer was set to the same thickness of 5 μm and P content 1.2 wt% as in Example 1-4-1. On the other hand, the Pd layer was set to a thickness of 0.008 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 2.5 μm. The Ni—Sn alloy layer was formed in a columnar shape as in Example 1-4-1.

[Example 1-4-3]
In Example 1-4-3, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder bump, as in Example 1-4-1. And the Ni layer was set to the same thickness of 5 μm and P content 1.2 wt% as in Example 1-4-1. On the other hand, the Pd layer was set to a thickness of 0.009 μm and a P content of 1 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 2.5 μm. The Ni—Sn alloy layer was formed in a columnar shape as in Example 1-4-1.

[Example 1-4-4]
In Example 1-4-4, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder bump, as in Example 1-4-1. And the Ni layer was set to the same thickness of 5 μm and P content 1.2 wt% as in Example 1-4-1. On the other hand, the Pd layer was set to a thickness of 2.0 μm and a P content of 2 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.3 μm. The Ni—Sn alloy layer was formed as a granular body at the interface of the nickel layer.

[Example 1-4-5]
In Example 1-4-5, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder bump, as in Example 1-4-1. The Ni layer was set to a thickness of 10 μm and a P content of 0.5 wt%. On the other hand, the Pd layer was set to a thickness of 2.0 μm and a P content of 5 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.3 μm. The Ni—Sn alloy layer was formed as a granular body at the interface of the nickel layer.

[Example 1-4-6]
In Example 1-4-6, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder bump, as in Example 1-4-1. The Ni layer was set to a thickness of 10 μm and a P content of 5 wt%. On the other hand, the Pd layer was set to a thickness of 2.0 μm and a P content of 9 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed as a granular body at the interface of the nickel layer.

[Example 1-5-1]
In Example 1-5-1, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder bump. The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. On the other hand, the Pd layer was set to have a thickness of 0.03 μm and a P content of 5 wt% (a microphotograph of this Pd layer is shown in FIG. 20. As can be seen from the photograph, Pb partially precipitates and is porous and underlying) Ni layer is visible). Here, when reflowing the solder, a flux containing copper was used. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1 with reference to the electron micrograph on the left side of FIG.

[Example 1-5-2]
In Example 1-5-2, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder bump. The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. On the other hand, the Pd layer was set to have a thickness of 0.07 μm and a P content of 5 wt% (a micrograph of this Pd layer is shown in FIG. 21. As can be seen from the photograph, the Pb layer can be formed uniformly). Here, when reflowing the solder, a flux containing copper was used. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1 with reference to the electron micrograph on the left side of FIG.

[Example 2]
In the first embodiment described above with reference to FIGS. 1 to 7, the build-up multilayer wiring board is targeted, but in the second embodiment, the multilayer multilayer printed wiring board is targeted.
The manufacturing process of the printed wiring board of Example 2 is demonstrated with reference to FIGS.
FIG. 9 shows a cross-sectional view of the printed wiring board 30 of the second embodiment. The multilayer printed wiring board 30 is a printed wiring board for mounting a semiconductor on which the IC chip 80 is mounted. The multilayer printed wiring board 30 is formed by laminating a plurality of substrates 31, and each substrate 31 is provided with a through hole 36, a via hole 38, and a conductor circuit 34. A conductor circuit 34U is provided on the upper surface side of the multilayer printed wiring board 30, and a conductor circuit 34D is provided on the lower surface side. A solder resist layer 70 is provided on the upper surface side of the conductor circuit 34 </ b> U, and a part of the conductor circuit 34 </ b> U is exposed through the opening 71 of the solder resist layer 70 to form a bonding pad 42. On the other hand, a solder resist layer 70 is provided on the surface side of the conductor circuit 34D on the lower surface side, and a part of the conductor circuit 34D is exposed through the opening 71 of the solder resist layer 70, thereby constituting a solder pad 44. A solder layer 46 for connection to an external printed wiring board is formed on the solder pad 44. An IC chip 80 is disposed on the upper surface of the multilayer printed wiring board via an adhesive 84, and the terminals 86 of the IC chip 80 and the bonding pads 42 on the multilayer printed wiring board side are bonded and connected by wires 82.

  Next, solder pads will be described with reference to FIG. FIG. 14B is an enlarged view of a portion surrounded by a circle B of the multilayer printed wiring board 30 in FIG. A nickel plating layer 72 is provided on the conductor circuit 34 </ b> D, and the solder layer 46 is connected via a Ni—Sn alloy layer 75 on the nickel plating layer 72. Here, in Example 2, lead-less solder of Cu 1 wt%, Ag 2 wt%, and Sn 97 wt% is used as the solder constituting the solder (solder layer). The Ni—Sn alloy layer 75 is made of Cu—Ni—Sn. In the second embodiment, the average thickness of the Cu—Ni—Sn alloy layer 75 is adjusted so that breakage hardly occurs at the interface between the nickel plating layer 72 and the solder layer 46. Thereby, the strength and adhesion of the solder layer 46 are improved.

Next, a method for manufacturing the multilayer printed wiring board 30 will be described with reference to FIGS.
A printed wiring board 31 having a circuit pattern 34 and a via hole 38 is prepared (FIG. 10A). The printed wiring board 31 is bonded through an adhesive 33 (FIG. 10B). Through holes 36 are formed by drilling through holes in a multilayer printed wiring board formed by laminating printed wiring boards 31 (FIG. 10C). Thereafter, a solder resist layer 70 having an opening 71 is formed (FIG. 11A).

  As shown in FIG. 11A, the multilayer printed wiring board 30 is provided with a conductor circuit 34 </ b> U on the upper surface side, and a part of the conductor circuit 34 </ b> U is exposed through the opening 71 of the solder resist layer 70. Similarly, a conductor circuit 34D is provided on the lower surface side. Part of the conductor circuit 34 </ b> D is exposed through the opening 71 of the solder resist layer 70. A roughening layer is preferably provided on the surfaces of the conductor circuit 34U and the conductor circuit 34D, and the adhesion to the solder resist layer 70 is enhanced.

(1) First, electroless nickel having pH = 4.5 comprising nickel chloride 2.3 × 10 −1 mol / l, sodium hypophosphite 2.8 × 10 −1 mol / l, sodium citrate 1.6 × 10 −1 mol / l It was immersed in a plating solution for 20 minutes to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71 (FIG. 11B). Thereby, even if the conductor circuit 34U and the conductor circuit 34D are provided with the roughened layer, the uneven portions thereof can be completely covered, and the surface state of the nickel plating layer 72 can be made uniform.

(2) Next, the substrate was palladium chloride 1.0 × 10 ⁻² mol / l, ethylenediamine 8.0 × 10 ⁻² mol / l, sodium hypophosphite 6.0 × 10 ⁻² mol / l, A palladium layer 73 having a thickness of 0.01 to 1.0 μm is formed on the nickel plating layer 72 by immersing in an electroless palladium plating solution having a pH of 8 and a temperature of 55 ° C. with 30 mg / l of thiodiglycolic acid. (FIG. 12A). As a result, the bonding pad 42 was formed on the conductor circuit 34U side of the upper surface, and the solder pad 44 was formed on the conductor circuit 34D side of the lower surface. Here, an Au layer can also be formed as a corrosion resistant layer. In Example 2, the thickness of the palladium layer 73 was set to be 0.01 to 1.0 μm, and P was contained in an amount of 2 to 7 wt%.

(3) Then, the solder paste 46α was printed on the solder pad 44 in the opening 71 of the solder resist layer 70 (FIG. 12B). FIG. 14A shows an enlarged view of the solder pad 44 in FIG. The solder pad 44 is composed of two composite layers of a nickel plating layer 72 and a palladium layer 73 that are sequentially formed on the conductor circuit 34D.

(4) Next, the solder layer 46 was formed by reflowing in a nitrogen atmosphere at 250 ° C. (FIG. 13A). During this reflow, most of the palladium layer 73 and the Au layer 64 diffuse to the solder layer 46 side, and as described above with reference to FIGS. 9 and 14B, the nickel plating layer 72, the solder layer 46, and the like. A Cu—Ni—Sn alloy layer 75 of the Ni layer and the solder composition metal is formed at the interface. Here, in Example 2, the palladium layer 73 is set to be 0.01 μm to 1.0 μm, and P is contained in 2 to 7 wt%, whereby the average thickness of the Cu—Ni—Sn alloy layer 75 is increased. It was adjusted. As a result, as described above, breakage hardly occurs at the interface between the nickel plating layer 72 and the solder layer 46.

(5) An IC chip 80 was mounted on the upper surface of the completed multilayer printed wiring board 30 via an adhesive 84 (FIG. 13B). Thereafter, bonding wires 82 were bonded between the terminals 86 of the IC chip 80 and the bonding pads 42 on the multilayer printed wiring board 30 side (see FIG. 9).

[Example 2-1-1]
In Example 2-1-1, Cu: 0.5 wt%, Ag: 3.5 wt%, and Sn: 95 wt% alloy were used as the solder constituting the solder (solder layer). The Ni layer was set to a thickness of 5 μm and the P content was 1.2 wt%, and the Pd layer was set to a thickness of 0.5 μm and the P content was 5 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.5 μm. In Example 2-1-1, the Cu—Ni—Sn alloy layer is plate-shaped, that is, along the nickel layer, as in Example 1-1-1 described above with reference to the electron micrograph on the left side of FIG. They are formed in parallel.

[Example 2-1-2]
In Example 2-1-2, as the solder constituting the solder (solder layer), Cu: 0.5 wt%, Ag: 3.5 wt%, Sn: 95 wt% alloy as in Example 2-1-1 Using. And Ni layer was set to the same thickness as Example 2-1-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.01 μm and a P content of 2 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.8 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 2-1-1.

[Example 2-1-3]
In Example 2-1-3, as the solder constituting the solder (solder layer), Cu: 0.5 wt%, Ag: 3.5 wt%, Sn: 95 wt% alloy as in Example 2-1-1 Using. And Ni layer was set to the same thickness as Example 2-1-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.01 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.8 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 2-1-1.

[Example 2-1-4]
In Example 2-1-4, as the solder constituting the solder (solder layer), Cu: 0.5 wt%, Ag: 3.5 wt%, Sn: 95 wt% alloy as in Example 2-1-1 Using. And Ni layer was set to the same thickness as Example 2-1-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 1.0 μm and a P content of 2 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 2-1-1.

[Example 2-1-5]
In Example 2-1-3, as the solder constituting the solder (solder layer), Cu: 0.5 wt%, Ag: 3.5 wt%, Sn: 95 wt% alloy as in Example 2-1-1 Using. The Ni layer was set to a thickness of 10 μm and a P content of 0.5 wt%. On the other hand, the Pd layer was set to a thickness of 1.0 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 2-1-1.

[Example 2-1-6]
In Example 2-1-6, as the solder constituting the solder (solder layer), Cu: 0.5 wt%, Ag: 3.5 wt%, Sn: 95 wt% alloy was used in the same manner as in Example 2-1-1. Using. The Ni layer was set to a thickness of 10 μm and a P content of 5 wt%. On the other hand, the Pd layer was set to a thickness of 0.01 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.7 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 2-1-1.

[Example 2-2-1]
In Example 2-1-1 to Example 2-1-6, lead-free Cu / Ag / Sn solder was used as the solder constituting the solder (solder layer). On the other hand, in Example 2-2-1 to Example 2-2-6, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder (solder layer). . The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.5 μm and a P content of 5 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 2-1-1.

[Example 2-2-2]
In Example 2-2-2, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder (solder layer) as in Example 2-2-1. And Ni layer was set to the same thickness as Example 2-2-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.01 μm and a P content of 2 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.8 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 2-1-1.

[Example 2-2-3]
In Example 2-2-3, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder (solder layer) as in Example 2-2-1. And Ni layer was set to the same thickness as Example 2-2-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.01 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.8 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 2-1-1.

[Example 2-2-4]
In Example 2-2-4, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder (solder layer) as in Example 2-2-1. And Ni layer was set to the same thickness as Example 2-2-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 1.0 μm and a P content of 2 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 2-1-1.

[Example 2-2-5]
In Example 2-2-5, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder (solder layer) as in Example 2-2-1. The Ni layer was set to a thickness of 10 μm and a P content of 0.5 wt%. On the other hand, the Pd layer was set to a thickness of 1.0 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 2-1-1.

[Example 2-2-6]
In Example 2-2-6, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder (solder layer) as in Example 2-2-1. And Ni layer was set to thickness 10m and P content 5wt%. On the other hand, the Pd layer was set to a thickness of 0.01 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33, and the thickness was adjusted to 1.7 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 2-1-1.

[Example 2-3-1]
In Example 2-3-1 to Example 2-3-6, as in the case of Example 2-1-1 to Example 2-1-6, the solder constituting the solder (solder layer) is Cu: 0. An alloy of 5 wt%, Ag: 3.5 wt%, and Sn: 95 wt% was used. And Ni layer was set to the same thickness as Example 2-1-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.009 μm and a P content of 8 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 45: 13, and the thickness was adjusted to 2.5 μm. In Example 2-3-1, as in Example 1-3-1-1, the Cu—Ni—Sn alloy layer is columnar, that is, columnar alloy crystals are formed vertically along the nickel layer.

[Example 2-3-2]
In Example 2-3-2, Cu: 0.5 wt%, Ag: 3.5 wt%, Sn: 95 wt% alloy was used as the solder constituting the solder (solder layer) as in Example 2-3-1. Using. And Ni layer was set to the same thickness as Example 2-3-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.008 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 45: 13, and the thickness was adjusted to 2.5 μm. The Ni—Sn alloy layer was formed in a columnar shape as in Example 2-3-1.

[Example 2-3-3]
In Example 2-3-3, as the solder constituting the solder (solder layer), Cu: 0.5 wt%, Ag: 3.5 wt%, Sn: 95 wt% alloy as in Example 2-3-1. Using. And Ni layer was set to the same thickness as Example 2-3-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.009 μm and a P content of 1 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 45: 13, and the thickness was adjusted to 2.5 μm. The Ni—Sn alloy layer was formed in a columnar shape as in Example 2-3-1.

[Example 2-3-4]
In Example 2-3-4, as the solder constituting the solder (solder layer), Cu: 0.5 wt%, Ag: 3.5 wt%, Sn: 95 wt% alloy as in Example 2-3-1. Using. And Ni layer was set to the same thickness as Example 2-3-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 2.0 μm and a P content of 2 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 66: 29: 5, and the thickness was adjusted to 1.3 μm. The Ni—Sn alloy layer was formed as a granular body at the interface of the nickel layer.

[Example 2-3-5]
In Example 2-3-5, as the solder constituting the solder (solder layer), Cu: 0.5 wt%, Ag: 3.5 wt%, Sn: 95 wt% alloy as in Example 2-3-1. Using. The Ni layer was set to a thickness of 10 μm and a P content of 0.5 wt%. On the other hand, the Pd layer was set to a thickness of 2.0 μm and a P content of 5 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 66: 29: 5, and the thickness was adjusted to 1.3 μm. The Ni—Sn alloy layer was formed as a granular body (granular crystal) at the interface of the nickel layer.

[Example 2-3-6]
In Example 2-3-6, Cu: 0.5 wt%, Ag: 3.5 wt%, Sn: 95 wt% alloy were used as the solder constituting the solder (solder layer) as in Example 2-3-1. Using. The Ni layer was set to a thickness of 10 μm and a P content of 5 wt%. On the other hand, the Pd layer was set to a thickness of 2.0 μm and a P content of 9 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 66: 29: 5, and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed as a granular body at the interface of the nickel layer.

[Example 2-4-1]
In Example 2-4-1 to Example 2-4-6, Sn: Pb = 63 as solder constituting the solder (solder layer) as in Example 2-2-1 to Example 2-2-6. : 37 (wt%) lead solder was used. And Ni layer was set to the same thickness as Example 2-2-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.009 μm and a P content of 8 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 2.5 μm. The Ni—Sn alloy layer was formed in a columnar shape as in Example 2-3-1.

[Example 2-4-2]
In Example 2-4-2, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder (solder layer) as in Example 2-4-1. And Ni layer was set to the same thickness as Example 2-4-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.008 μm and a P content of 7 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 2.5 μm. The Ni—Sn alloy layer was formed in a columnar shape as in Example 2-4-1.

[Example 2-4-3]
In Example 2-4-3, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder (solder layer) as in Example 2-4-1. And Ni layer was set to the same thickness as Example 2-4-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.009 μm and a P content of 1 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 2.5 μm. The Ni—Sn alloy layer was formed in a columnar shape as in Example 2-4-1.

[Example 2-4-4]
In Example 2-4-4, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder (solder layer) as in Example 2-4-1. And Ni layer was set to the same thickness as Example 2-4-1, 5 micrometers, and P content 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 2.0 μm and a P content of 2 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.3 μm. The Ni—Sn alloy layer was formed as a granular body at the interface of the nickel layer.

[Example 2-4-5]
In Example 2-4-5, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder (solder layer) as in Example 2-4-1. The Ni layer was set to a thickness of 10 μm and a P content of 0.5 wt%. On the other hand, the Pd layer was set to a thickness of 2.0 μm and a P content of 5 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.3 μm. The Ni—Sn alloy layer was formed as a granular body at the interface of the nickel layer.

[Example 2-4-6]
In Example 2-4-6, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder (solder layer) as in Example 2-4-1. The Ni layer was set to a thickness of 10 μm and a P content of 5 wt%. On the other hand, the Pd layer was set to a thickness of 2.0 μm and a P content of 9 wt%. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Ni = 67: 33 and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed as a granular body at the interface of the nickel layer.

[Example 2-5-1]
In Example 2-5-1, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder (solder layer). The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.03 μm and a P content of 5 wt%. Here, when reflowing the solder, a flux containing copper was used. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1.

[Example 2-5-2]
In Example 2-5-2, lead solder of Sn: Pb = 63: 37 (wt%) was used as the solder constituting the solder (solder layer). The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. On the other hand, the Pd layer was set to a thickness of 0.07 μm and a P content of 5 wt%. Here, when reflowing the solder, a flux containing copper was used. Thereby, the composition of the Ni—Sn alloy layer was adjusted to Sn: Cu: Ni = 42: 37: 21, and the thickness was adjusted to 1.5 μm. The Ni—Sn alloy layer was formed in a plate shape as in Example 1-1-1.

[Reference Example 1-1-1]
In Reference Example 1-1-1 to Reference Example 1-1-3 and Reference Example 1-2-1 to Reference Example 1-2-3, as in Example 1 described above with reference to FIGS. A build-up multilayer wiring board was formed, and solder bumps were formed.
And as a solder which comprises a solder bump, Cu: 2 wt%, Ag: 1 wt%, Sn: 97 wt% alloy was used. The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. However, the Pd layer was formed with a thickness of 0.5 μm so as not to contain P (P content = approximately 0%). Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 0.8 μm. 16 to 19 show electron micrographs of the nickel layer, the Cu—Ni—Sn alloy layer, and the solder of Reference Example 1-1-1. The right side electron micrograph (× 20K) in FIG. 16 is Reference Example 1-1-1. The magnification (× 100K) is further enlarged in the electron micrographs on the right side in FIG. 17 and on the right side in FIG. Here, the lower side is the nickel layer, the upper side is the solder, and the Cu—Ni—Sn alloy layer is present at the interface between the nickel layer and the solder layer. From the electron micrograph on the right side of FIG. 16, it can be seen that in Reference Example 1-1-1, the Cu—Ni—Sn alloy layer is discontinuous, that is, has a large undulation and is formed on the surface of the Ni layer. Further, from the electron micrographs on the right side of FIGS. 17 and 18 where the magnification is increased, it can be seen that Ag particles are scattered unevenly on the surface of the Cu—Ni—Sn alloy layer via the Sn skin layer. . In Reference Example 1-1-1, the Cu—Ni—Sn alloy layer is columnar as shown in the electron micrograph on the right side of FIG. 19, that is, columnar alloy crystals are formed vertically along the nickel layer.

[Reference Example 1-1-2]
In Reference Example 1-1-2, Cu: 2 wt%, Ag: 1 wt%, and Sn: 97 wt% alloy were used as the solder constituting the solder bump, as in Reference Example 1-1-1. The Ni layer was set to a thickness of 5 μm and a P content of 4 wt%. On the other hand, the Pd layer had a thickness of 1.0 μm and the P content was set to 2 wt%, which was smaller than that of the Ni layer. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 0.9 μm.

[Reference Example 1-1-3]
In Reference Example 1-1-3, Cu: 2 wt%, Ag: 1 wt%, and Sn: 97 wt% alloy were used as the solder constituting the solder bump, as in Reference Example 1-1-1. The Ni layer was set to a thickness of 5 μm and a P content of 4 wt%. On the other hand, the Pd layer had a thickness of 1.0 μm and a P content of 9 wt%. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 2.7 μm.

[Reference Example 1-1-4]
In Reference Example 1-1-4, Cu: 2 wt%, Ag: 1 wt%, and Sn: 97 wt% alloy were used as the solder constituting the solder bump, as in Reference Example 1-1-1. The Ni layer was set to a thickness of 5 μm and a P content of 4 wt%. On the other hand, the Pd layer had a thickness of 1.5 μm and a P content of 9 wt%. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 2.9 μm.

[Reference Example 1-2-1]
In Reference Example 1-1-1 to Reference Example 1-1-3, leadless Cu / Ag / Sn solder was used as the solder constituting the solder bump. On the other hand, in Reference Example 1-2-1 to Reference Example 1-2-3, lead solder of Sn: Pb = 64: 36 (wt%) was used as the solder constituting the solder bump. The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. On the other hand, the Pd layer was formed with a thickness of 0.5 μm so as not to contain P (P content = approximately 0%). Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 0.9 μm.

[Reference Example 1-2-2]
In Reference Example 1-2-2, lead solder of Sn: Pb = 64: 36 (wt%) was used as the solder constituting the solder bump, as in Reference Example 1-2-1. The Ni layer was set to a thickness of 5 μm and a P content of 4 wt%. On the other hand, the Pd layer had a thickness of 1.0 μm and the P content was set to 2 wt%, which was smaller than that of the Ni layer. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 0.9 μm.

[Reference Example 1-2-3]
In Reference Example 1-2-3, lead solder of Sn: Pb = 64: 36 (wt%) was used as the solder constituting the solder bump, as in Reference Example 1-2-1. The Ni layer was set to a thickness of 5 μm and a P content of 4 wt%. On the other hand, the Pd layer had a thickness of 1.0 μm and a P content of 9 wt%. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 2.6 μm.

[Reference Example 1-2-4]
In Reference Example 1-2-4, lead solder of Sn: Pb = 64: 36 (wt%) was used as the solder constituting the solder bump, as in Reference Example 1-2-1. The Ni layer was set to a thickness of 5 μm and a P content of 4 wt%. On the other hand, the Pd layer had a thickness of 1.5 μm and a P content of 9 wt%. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 2.7 μm.

[Reference Example 2-1-1]
In Reference Example 2-1-1 to Reference Example 2-1-3 and Reference Example 2-2-1 to Reference Example 2-2-3, similar to Example 2 described above with reference to FIGS. A laminated printed wiring board was formed, and a solder layer was formed. And as a solder which comprises solder (solder layer), Cu: 2 wt%, Ag: 1 wt%, Sn: 97 wt% alloy was used. The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. However, the Pd layer was formed so as not to contain P with a thickness of 0.5 μm. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 0.9 μm.

[Reference Example 2-1-2]
In Reference Example 2-1-2, Cu: 2 wt%, Ag: 1 wt%, and Sn: 97 wt% alloy were used as the solder constituting the solder (solder layer) as in Reference Example 2-1-1. The Ni layer was set to a thickness of 5 μm and a P content of 4 wt%. On the other hand, the Pd layer had a thickness of 1.0 μm and the P content was set to 2 wt%, which was smaller than that of the Ni layer. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 0.9 μm.

[Reference Example 2-1-3]
In Reference Example 2-1-3, Cu: 2 wt%, Ag: 1 wt%, and Sn: 97 wt% alloy were used as the solder constituting the solder (solder layer) as in Reference Example 2-1-1. The Ni layer was set to a thickness of 5 μm and a P content of 4 wt%. On the other hand, the Pd layer had a thickness of 1.0 μm and a P content of 9 wt%. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 2.6 μm.

[Reference Example 2-1-4]
In Reference Example 2-1-4, Cu: 2 wt%, Ag: 1 wt%, and Sn: 97 wt% alloy were used as the solder constituting the solder (solder layer) as in Reference Example 2-1-1. The Ni layer was set to a thickness of 5 μm and a P content of 4 wt%. On the other hand, the Pd layer had a thickness of 1.5 μm and a P content of 9 wt%. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 2.7 μm.

[Reference Example 2-2-1]
In Reference Example 2-1-1 to Reference Example 2-1-3, lead-less Cu / Ag / Sn solder was used as the solder constituting the solder (solder layer). On the other hand, in Reference Example 2-2-1 to Reference Example 2-2-3, Sn: Pb = 64: 36 (wt%) lead solder was used as the solder constituting the solder (solder layer). . The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. On the other hand, the Pd layer was formed so as not to contain P with a thickness of 0.5 μm. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 0.8 μm.

[Reference Example 2-2-2]
In Reference Example 2-2-2, lead solder of Sn: Pb = 64: 36 (wt%) was used as the solder constituting the solder (solder layer) as in Reference Example 2-2-1. The Ni layer was set to a thickness of 5 μm and a P content of 4 wt%. On the other hand, the Pd layer had a thickness of 1.0 μm and the P content was set to 2 wt%, which was smaller than that of the Ni layer. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 0.9 μm.

[Reference Example 2-2-3]
In Reference Example 2-2-3, lead solder of Sn: Pb = 64: 36 (wt%) was used as the solder constituting the solder (solder layer) as in Reference Example 2-2-1. The Ni layer was set to a thickness of 5 μm and a P content of 4 wt%. On the other hand, the Pd layer had a thickness of 1.0 μm and a P content of 9 wt%. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 2.7 μm.

[Reference Example 2-2-4]
In Reference Example 2-2-4, lead solder of Sn: Pb = 64: 36 (wt%) was used as the solder constituting the solder (solder layer) as in Reference Example 2-2-1. The Ni layer was set to a thickness of 5 μm and a P content of 4 wt%. On the other hand, the Pd layer had a thickness of 1.5 μm and a P content of 9 wt%. Thereby, the thickness of the Ni—Sn alloy layer was adjusted to 2.7 μm.

As a comparative example, nickel (Ni layer) -gold (Au layer) in the prior art was formed on the conductor layer in the solder pad portion.
[Comparative Example 1-1-1]
In Comparative Example 1-1-1, Cu: 2 wt%, Ag: 1 wt%, and Sn: 97 wt% alloy were used as the solder constituting the solder bump, as in Reference Example 1-1-1. The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. On the other hand, an Au layer having a thickness of 0.03 μm was provided on the Ni layer instead of the Pd layer. After the reflow, the Ni—Sn alloy layer was not formed.

[Comparative Example 1-2-1]
In Comparative Example 1-2-1, lead solder of Sn: Pb = 64: 36 (wt%) was used as the solder constituting the solder bump, as in Reference Example 1-2-1. The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. On the other hand, an Au layer having a thickness of 0.03 μm was provided on the Ni layer instead of the Pd layer. After the reflow, the Ni—Sn alloy layer was not formed.

[Comparative Example 2-1-1]
In Comparative Example 2-1-1, Cu: 2 wt%, Ag: 1 wt%, and Sn: 97 wt% alloy were used as the solder constituting the solder (solder layer) as in Reference Example 2-1-1. The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. On the other hand, an Au layer having a thickness of 0.03 μm was provided on the Ni layer instead of the Pd layer. After the reflow, the Ni—Sn alloy layer was not formed.

[Comparative Example 2-2-1]
In Comparative Example 2-2-1, lead solder of Sn: Pb = 64: 36 (wt%) was used as the solder constituting the solder (solder layer) as in Reference Example 2-2-1. The Ni layer was set to a thickness of 5 μm and a P content of 1.2 wt%. On the other hand, an Au layer having a thickness of 0.03 μm was provided on the Ni layer instead of the Pd layer. After the reflow, the Ni—Sn alloy layer was not formed.

(Evaluation item)
The substrate was formed using 10 pieces obtained by processing individual pieces for each piece. The evaluation results of Example 1 are shown in FIG. 22, the evaluation results of Example 2 are shown in FIG. 23, and the evaluation results of the reference example and the comparative example are shown in FIG.
1. Solder Peel Test After the solder paste was mounted, a solder paste peel test was performed. Here, the case where a numerical value exceeding 4.0 Kg / pin (solder bump or solder layer) in the tensile strength is obtained is ◎, and the case where a numerical value of 2.0 to 4.0 Kg / pin is obtained in the tensile strength. The case where a numerical value of 1.0 to 2.0 Kg / pin was obtained was indicated by Δ, and the case where a numerical value of less than 1.0 Kg / pin was obtained was indicated by ×.

2. Reliability test Example 1 group: resistance measurement after mounting IC chip Example 2 group: resistance measurement after mounting on motherboard Motherboard under heat cycle conditions (135 ° C / 3min.-55 ° C / 3min. A reliability test was performed from 2500 cycles to 5000 cycles every 500 cycles.
At this time, the substrate was taken out from the reliability tester and allowed to stand for 2 hours, and then the presence / absence of conduction and the resistance value of the substrate were measured. Here, 導 通 indicates that there is continuity and the change in resistance value is less than 2%, ◯ indicates that there is continuity and the change in resistance value exceeds 2% and less than 5%, and ◯ indicates that the change in resistance value is 5%. A value exceeding Δ is indicated by Δ, and a case where conduction is lost is indicated by ×.

3. 3. Peel test with chip / motherboard after reliability test A tensile strength measurement was performed on the substrate after the completion of the mounting and the completion of 5000 cycles in the reliability test. Here, the case where a numerical value of 1.0 to 2.0 kg / pin (solder bump or solder layer) is obtained in the tensile strength is indicated by ◯, and the case where a numerical value less than 1.0 kg / pin is obtained is indicated by x. did.

  From the above test results, it became clear that the Pd layer is more reliable than the Au layer. And it turned out that it is good to form the thickness of Pd layer in the range of 0.01-1.0 micrometer, and it is especially good to form in the range of 0.03-0.7 micrometer especially. It has also been found that the P content in the Pd layer is preferably 4 to 6 wt% so as not to deviate significantly from 2 to 7 wt%. The thickness of the Ni layer is desirably formed in a range of 2 to 10 μm, and the content of P (phosphorus) in the Ni layer is 0.5 to 5.0 wt%, which is more than the P content in the Pd layer. It became clear that lowering was more desirable.

It is sectional drawing of the multilayer printed wiring board which concerns on Example 1 of this invention. It is a manufacturing-process figure of the multilayer printed wiring board which concerns on Example 1 of this invention. It is a manufacturing-process figure of the multilayer printed wiring board which concerns on Example 1 of this invention. It is a manufacturing-process figure of the multilayer printed wiring board which concerns on Example 1 of this invention. It is a manufacturing-process figure of the multilayer printed wiring board which concerns on Example 1 of this invention. It is a manufacturing-process figure of the multilayer printed wiring board which concerns on Example 1 of this invention. It is a manufacturing-process figure of the multilayer printed wiring board which concerns on Example 1 of this invention. FIG. 8A is a schematic diagram showing an enlarged circle A portion in FIG. 7B, and FIG. 8B is a schematic diagram showing an enlarged circle B portion in FIG. . It is sectional drawing of the multilayer printed wiring board which concerns on Example 2 of this invention. 6 is a manufacturing process diagram of a printed wiring board according to Embodiment 2. FIG. 6 is a manufacturing process diagram of a printed wiring board according to Embodiment 2. FIG. 6 is a manufacturing process diagram of a printed wiring board according to Embodiment 2. FIG. 6 is a manufacturing process diagram of a printed wiring board according to Embodiment 2. FIG. FIG. 14A is a schematic diagram showing an enlarged circle A portion in FIG. 12B, and FIG. 14B is a schematic diagram showing an enlarged circle B portion in FIG. . FIGS. 15A and 15B are schematic diagrams for explaining the Pd film formation. FIG. 15A shows a case where P is included, and FIG. 15B shows a case where P is not included. Show. It is an electron micrograph of a nickel layer, a Cu-Ni-Sn alloy layer, and solder. It is an electron micrograph of a Cu-Ni-Sn alloy layer. It is an electron micrograph of a Cu-Ni-Sn alloy layer. It is a transmission electron micrograph of a Cu-Ni-Sn alloy layer. It is an electron micrograph of a Pd layer having a thickness of 0.7 μm. It is an electron micrograph of a Pd layer having a thickness of 0.3 μm. 6 is a chart showing test results of Example 1. 10 is a chart showing test results of Example 2. It is a graph which shows the test result of a reference example and a comparative example.

Explanation of symbols

30 multilayer printed wiring board 70 solder resist layer 70a opening 72 nickel layer 73 palladium layer 75 Ni-Sn alloy layer 76U, 76D solder bump

Claims (12)

A solder pad in which a part of the solder resist layer is opened is formed, a composite layer is applied to the surface layer of the conductor circuit exposed from the solder pad, and a solder bump or solder layer for external connection is formed on the composite layer Printed wiring board,
The printed wiring board, wherein the composite layer is a Ni layer or a Ni—Sn alloy layer. A solder pad in which a part of the solder resist layer is opened is formed, a composite layer is applied to the surface layer of the conductor circuit exposed from the solder pad, and a solder bump or solder layer for external connection is formed on the composite layer Printed wiring board,
The composite layer is a Ni layer, a Ni-Sn alloy layer,
The printed wiring board, wherein the solder bump or the solder layer is made of solder containing no lead. The multilayer printed wiring board according to claim 1, wherein the Ni—Sn alloy layer is a three-component composed of Ni—Sn—Cu. The printed wiring board according to claim 1, wherein the Ni—Sn alloy layer has a plate-like body formed at least in part. The printed wiring board according to claim 3, wherein the solder layer contains Cu. The printed wiring board according to claim 5, wherein the solder layer contains Cu and Sn with 0.5 ≦ Cu / Sn ≦ 1.0. The multilayer printed wiring board according to claim 1, wherein the solder layer has undergone a heat treatment. A solder pad in which a part of the solder resist layer is opened is formed, a composite layer is applied to the surface layer of the conductor circuit exposed from the solder pad, and a solder pad structure having a solder for external connection on the composite layer Manufacturing method:
Providing a composite layer composed of at least a Ni layer and a Pd layer on the surface layer of the conductor circuit exposed from the opening of the solder resist layer;
Providing solder on the composite layer;
A method of manufacturing a printed wiring board comprising: reflowing solder to form solder bumps, and forming a Ni—Sn alloy layer at the interface between the Ni layer and the solder bumps. The method for manufacturing a printed wiring board according to claim 8, wherein the Pd layer is provided so that 2 to 7 wt% of P is contained. The printed wiring board according to claim 9, wherein the Ni layer is provided so that 0.5 to 5.0 wt% of P, which is smaller than the P content in the Pd layer, is contained. The method for producing a printed wiring board according to claim 8 or 9, wherein the Pd layer is provided to a thickness of 0.01 to 1.0 µm. The method of manufacturing a printed wiring board according to claim 8, wherein the solder is made of Cu—Sn—Ag, and the Ni—Sn alloy layer is made of Cu—Ni—Sn.