JPH09260536A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability on the junction between both of the junction between a lead part and an outer terminal and the junction between a bump land part and a bump electrode, in a semiconductor integrated circuit device which has a package structure where the lead part of the wiring board where a solder bump electrode is made is electrically connected to the outer terminal of a semiconductor chip. SOLUTION: In a BGA type of semiconductor integrated circuit device where a flexible wiring board 3 is provided through an elastomer 2 on the main surface of a semiconductor chip 1, the thickness of a gold plating layer at the junction face with the bonding pad 5 of a semiconductor chip 1, at the lead part 3L1 of the flexible wiring board, and the thickness of the gold plating layer at the junction face with the solder bump electrode 3b, at the bump land part 3L2 of the flexible wiring board 3, are varied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device technique, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having a BGA (Ball Grid Array) package structure.

[0002]

2. Description of the Related Art With the improvement of functions and performances of electronic devices, technological developments are being made to make the external appearance small and thin and to reduce the weight thereof. This is largely due to the rapid increase in the number of portable electronic devices such as portable telephones and portable computers in recent years.

In addition, the role of man-machine interface in electronic devices operated by individuals is becoming more important, and the ease of handling and operability of electronic devices are becoming more important. Furthermore, there is an increasing demand for high-speed processing of a large amount of information including complicated images in a small electronic device. These trends are expected to become even stronger with the advent of the full-fledged multimedia era.

Under these circumstances, the improvement in the degree of integration of the elements formed on the semiconductor chip cannot be stopped,
As the size of the semiconductor chip and the number of electrodes increase, the package for housing the semiconductor chip has become larger.

On the other hand, measures such as narrowing the lead pitch have been taken in order to reduce the package size.
Along with this, packaging of packages has become difficult rapidly.

Therefore, a BGA type package structure in which a large number of external electrodes can be pulled out from a small package and which can be mounted relatively easily is rapidly being used.

In this structure, the external electrode is connected to the QFP (Quad
It is structured such that it is not pulled out from the side of the package like Flat Package) but from the mounting surface of the package like PGA (Pin Grid Array). QFP
It has a feature that it can be pulled out with a margin more than that of the above, so that it is easy to mount.

There are various types of BGA type packages having different structures, materials and the like, and a so-called tape BGA (Tape BGA; hereinafter referred to as TBGA) which uses an insulating tape for a wiring board portion is one of them. You can say that. This T
The BGA type package structure has a feature that a pattern can be formed finer and thinner than other BGA type package structures.

Therefore, a TBGA type package structure has been developed which is applied to a so-called CSP (Chip Size Package) structure of a BGA package structure having substantially the same external dimensions as a semiconductor chip. BGA like this
For a semiconductor integrated circuit device having a rectangular package structure, for example, “Nikkei Microdevices” P98 to P102 issued on May 1, 1994 by Nikkei BP, and 1
"Nikkei Microdevice" P9, issued on February 1, 995
6-P97 and Industrial Research Institute Co., Ltd., April 1, 1995
There is a description in "Electronic Materials" P22-P28, etc. issued daily,
A CSP type BGA package structure is described here.

That is, in these documents, flexible wiring in which bump electrodes are arranged in an area array is provided on the main surface of a semiconductor chip through an elastomer, and leads of a wiring pattern formed on the flexible wiring board are provided. There is disclosed a package structure in which a substrate is bent and connected to a bonding pad on the main surface of a semiconductor chip. The wiring pattern of this flexible wiring board is formed of gold (Au) -plated copper (Cu) foil, and Cu is etched at the tip to become an Au lead.

The present inventor has also examined a semiconductor integrated circuit device having this type of package structure. Although the following is not a known technique, it is a technique studied by the present inventor, and its outline is as follows.

That is, according to the technique studied by the present inventor, the core material of the lead in the flexible wiring board having the above-mentioned package structure is made of Cu, and Au plating layers of the same thickness are formed on the upper and lower surfaces of the lead. It is what is done.

Regarding the TBGA type package structure, for example, "Electronic Material Technology Association of Japan, The Whereabouts of TBGA" J, issued by Japan Electronic Material Technology Association, July 1995.
EMS. VOL. 27, P14 to P19.

Here, a TAB tape which is formed in a plane frame shape so as to surround the LSI chip is arranged on the outer periphery of the LSI chip, and a TAB lead extended in a flat shape from the TAB tape and the main portion of the LSI chip. Typical structure of TBGA in which a bonding pad on the surface is electrically connected via a solder terminal or the like, and a spherical solder terminal connected to the pad of the mounting board is provided on the frame surface of the TAB tape. It is explained.

The back surface of this LSI chip is joined to a heat dissipation plate. LS is placed between the heat sink and the TAB tape.
A fixing plate formed in the shape of a plane frame is provided so as to surround the side surface of the I-chip. TAB tape is copper (Cu)
/ Polyimide / Cu.

[0016]

However, the above-mentioned B
The present inventors have found that the GA package technology has the following problems.

That is, in the technique of forming the leads of the flexible wiring board with Au, there is a problem that a large amount of expensive gold is required and the manufacturing cost of the semiconductor integrated circuit device increases.

In the technique studied by the present inventor, the core material of the wiring of the flexible wiring board is made of Cu, and the gold plating layers of the same thickness are provided on both sides of the lead of the wiring. It is not possible to optimize the joint conditions of the joint with the external terminal of the chip and the joint with the solder bump electrode and the wiring portion (bump land) to which it is joined, and it is sufficient at both joints. There is a problem that it is not possible to obtain high reliability in bonding.

An object of the present invention is to provide a semiconductor integrated circuit device having a package structure in which a lead portion of a wiring board on which solder bump electrodes are formed is electrically connected to an external terminal of a semiconductor chip. It is an object of the present invention to provide a technique capable of improving the reliability of bonding both a bonding part with a terminal and a bonding part with a bump land part and a bump electrode.

Another object of the present invention is a semiconductor integrated circuit device having a package structure in which a lead portion of a wiring board on which solder bump electrodes are formed is electrically connected to an external terminal of a semiconductor chip. It is to provide a technique capable of reducing the manufacturing cost.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0022]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In the semiconductor integrated circuit device of the present invention, the lead portion of the wiring formed on the wiring board is electrically connected to the external terminal on the main surface of the semiconductor chip, and the wiring formed on the wiring board is connected. A semiconductor integrated circuit device having a land portion electrically connected to a solder bump electrode, comprising: (a) a first surface formed on a joint surface between the lead portion and the external terminal;
And the thickness of the second gold layer formed on the bonding surface between the land portion and the solder bump electrode is changed.

Further, in the semiconductor integrated circuit device of the present invention, the constituent atom of the core material portion is between the core material portion of the wiring and the first gold layer and the second gold layer. And a barrier metal layer for suppressing movement to the second gold layer and the second gold layer.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings (note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments. , The repeated explanation is omitted).

(Embodiment 1) FIG. 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG.
II-II sectional view, FIG. 3 is a plan view of a main part of the semiconductor integrated circuit device of FIG. 1, FIG. 4 is a sectional view of IV-IV line of FIG. 3, and FIG. Graph diagram showing the relationship between the thickness of the formed gold layer and the joint strength deterioration rate in each joint,
6 to 15 are explanatory views for explaining an example of a plating structure in the lead portion of the semiconductor integrated circuit device of FIG. 1, and FIG. 16 is a view for explaining a plating treatment method on the wiring board of the semiconductor integrated circuit device of FIG. 1 is an explanatory view for explaining an assembly process of the semiconductor integrated circuit device of FIG.
8 is a plan view of a mask used in the step of forming the elastic structure of the semiconductor integrated circuit device of FIG. 1, FIG. 19 is an explanatory view of the step of forming the elastic structure of the semiconductor integrated circuit device of FIG.
22 is an explanatory diagram during a lead connecting step of the semiconductor integrated circuit device of FIG. 1, and FIGS. 23 and 24 are explanatory diagrams of application examples of the semiconductor integrated circuit device of FIG.

First, the structure of the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

The semiconductor integrated circuit device according to the first embodiment is
For example, it is a CSP (Chip Size Package) type semiconductor integrated circuit device, and has a semiconductor chip 1 and a flexible wiring board (wiring board) 3 provided on its main surface with an elastomer (elastic structure) 2 interposed therebetween. are doing.

The semiconductor chip 1 is made of, for example, a small piece of silicon (Si) single crystal having a planar rectangular shape, and a logic circuit such as a microprocessor or a static random access memory (SRAM) or the like is provided on its main surface. DRA
A predetermined integrated circuit such as a memory circuit such as an M (Dynamic Random Access Memory) is formed.

A passivation film 4 is formed on the uppermost layer of the main surface of the semiconductor chip 1. The passivation film 4 is an insulating film for protecting the above-mentioned elements and wirings for the integrated circuit configuration, and the semiconductor chip 1
A passivation film 4a made of, for example, an inorganic material and a passivation film 4b made of, for example, an organic material are deposited and formed in order from the main surface side.

The passivation film 4a is composed of, for example, silicon dioxide (SiO ₂ ) or silicon nitride deposited thereon. The passivation film 4b is made of, for example, a polyimide resin and has a thickness of, for example, about 2 to 10 μm.

In the center of the main surface of the semiconductor chip 1, a plurality of rectangular bonding pads (external terminals) 5 are arranged along a straight line. The bonding pad 5 is an extraction electrode for extracting the electrode of the integrated circuit to the outside of the semiconductor chip 1, and is made of, for example, aluminum (Al) or Al-Si-Cu alloy.

The upper surface of the bonding pad 5 is exposed through the openings 4a1 and 4b1 formed in the passivation films 4a and 4b. The opening 4a1 in the lower passivation film 4a is formed in such a size that the upper surface of each bonding pad 5 is exposed (see FIGS. 3 and 4). In FIG. 3, the passivation films 4a and 4b are shown to make the drawing easier to see.
Hatch.

The opening 4b1 in the upper passivation film 4b is formed to be larger than each bonding pad 5, and is an elongated opening region extending along the arrangement direction of the plurality of bonding pads 5. There is.

In FIG. 4, reference character Z indicates an interlayer insulating film, and a plurality of wiring layers and elements are formed in the lower layer (direction toward the semiconductor substrate of the semiconductor chip 1).

The elastomer 2 is provided with a semiconductor chip at a connection portion (solder bump electrode described later) between a CSP type semiconductor integrated circuit device and a printed wiring board on which the CSP type semiconductor integrated circuit device is mounted during heat treatment such as a temperature characteristic test. 1 has a function of absorbing stress applied due to a difference in thermal expansion coefficient between the printed circuit board and the printed wiring board.

The elastomers 2 are arranged on both sides (left and right in FIG. 1 etc.) of long sides in the arrangement area of the bonding pads 5 in the center of the main surface of the semiconductor chip 1. Each of the right and left elastomers 2 is formed in a flat plate shape extending along the longitudinal direction of the semiconductor chip 1, and has a thickness of, for example, about 100 μm to 200 μm, preferably 150 μm.
It is made of an elastic material such as a silicone resin having a thickness of about μm.

The right and left elastomers 2 are respectively adhered to the semiconductor chip 1 with an adhesive 6a.
The adhesive 6a is made of, for example, a silicone resin, and its thickness is set to, for example, about 10 μm to 30 μm, preferably about 20 μm.

The flexible wiring board 3 is a member for electrically connecting the integrated circuit of the semiconductor chip 1 and the wiring of the printed wiring board for mounting, and the pattern forming surface of the wiring 3L of the flexible wiring board 3. Elastomer 2
It is bonded to the elastomer 2 in a state of facing the side and incorporated in the semiconductor integrated circuit device.

The tape (substrate material) 3T that constitutes the flexible wiring board 3 is made of, for example, a polyimide resin,
A rectangular opening 3T1 is formed in the center of the semiconductor chip 1 so as to extend in the longitudinal direction of the semiconductor chip 1, and the arrangement area of the bonding pads 5 is exposed from the opening 3T1. The tape 3T has a thickness of, for example, about 50 μm to 125 μm, preferably 50 μm.
It is set to about μm.

The above-mentioned wiring 3L is patterned on the tape 3T. The wiring 3L is adhered to the tape 3T with an adhesive material 6b. The adhesive 6b is made of, for example, an epoxy resin and has a thickness of, for example, 1
The thickness is set to about 0 μm to 20 μm, preferably about 10 μm.

The core portion of this wiring 3L (the main constituent material portion of the wiring excluding the plating layer) is made of, for example, Cu or Cu alloy, and its thickness is, for example, about 12 μm to 30 μm, preferably, 18 μm. It is set to a degree.

One end of the wiring 3L, that is, the lead portion 3L1 is projected from both long side sides of the central opening 3T1 of the tape 3T, and the lead portions 3L1 protruding from both long side sides are meshed with each other. To the center of the semiconductor chip 1.

The lead portion 3L1 is bent toward the main surface side of the semiconductor chip 1 and has its tip electrically connected to the bonding pad 5 on the main surface of the semiconductor chip 1. Are electrically connected (see FIGS. 2 and 4 etc.). A plating layer is not shown on the lead portion 3L1 in FIG.

The bending of the lead portion 3L1 has a function of absorbing the stress generated in the lead portion 3L1 due to the difference in thermal expansion coefficient between the semiconductor chip 1 and the printed wiring board. That is, the lead portion 3L1 has a function as an elastic body due to its bending.

The width of the core portion of the lead portion 3L1 varies depending on the type of product and the like and cannot be generally stated, but is, for example, about 38 μm. The surface of the core portion of the lead portion 3L1 is plated. This plating structure will be described later in detail.

A bump land portion 3L2 is formed in the middle of the wiring 3L. This bump land 3L2
Are electrically connected to the solder bump electrodes 3B through the openings 3T2 formed in the tape 3T. In the bump land portion 3L2, the joint surface with the solder bump electrode 3B is plated. This plating structure will also be described later in detail.

In the wiring 3L, the bump land 3
A portion extending from L2 to the outer peripheral side of the flexible wiring board 3 is a wiring 3L3 for supplying a plating current. The wiring 3L3 for supplying the plating current is connected to the terminal for supplying the plating current of the plating device when the lead portion 3L1 and the bump land portion 3L2 are plated, and is connected to the lead portion 3L1 and the bump land portion 3L2. It serves as a wiring path for supplying a fixed amount of current.

The solder bump electrodes 3B are provided on both sides (left and right in FIG. 1) of the opening 3T1 on the main surface of the tape 3T.
Each of them is regularly arranged. However,
The solder bump electrode 3B is arranged in a region inside the outer periphery of the semiconductor chip 1.

Each solder bump electrode 3B is made of, for example, a lead (Pb) -tin (Sn) alloy or the like formed in a substantially spherical shape, and the diameter thereof varies depending on the type of product and the like, but cannot be generally stated. For example, it is set to about 0.5 mm to 0.7 mm, and in the first embodiment, it is set to about 0.6 mm, for example.

In such a CSP type semiconductor integrated circuit device, the side surface of the semiconductor chip 1 and the side surface of the elastomer 2 are covered with the sealing resin 7a (see FIG. 2). However, this sealing resin 7a may be omitted.

The opening 3 of the flexible wiring board 3
The sealing resin 7b is also filled in the groove exposed from T1, that is, in the groove formed by the main surface of the semiconductor chip 1 and the inner wall surfaces of the two elastomers 2 facing each other. The bonding pad 5 and the lead portion 3L1 are covered.

The sealing resin 7a, 7b sufficiently protects the CSP type semiconductor integrated circuit device from external impacts, moisture, etc., and the reliability of the semiconductor integrated circuit device can be improved. ing.

Next, the plating structure of the wiring 3L of the flexible wiring board 3 described above will be described after the results of examination by the present inventor, and then a specific structural example will be described.

First, the inventor of the present invention has made the lead portion 3 of the wiring 3L.
The strength of the joint between L1 and the bonding pad 5 (hereinafter referred to as the lead joint) and the strength of the joint between the bump land 3L2 of the wiring 3L and the solder bump electrode 3B (hereinafter referred to as the bump joint) were examined.

As a result, it has been found that the strength of each joint differs depending on the thickness of the gold (Au) plating applied to the lead portion 3L1 and the bump land portion 3L2.
The result is shown in FIG.

FIG. 5 shows each of the lead joint portion and the bump joint portion after the semiconductor integrated circuit device of the first embodiment is subjected to a high temperature storage (aging) test at 125 ° C. for about 48 hours. 5 is a graph showing the rate of deterioration of the bonding strength of the.

The abscissa of FIG. 5 shows the film thickness of the Au plating layer coated on the wiring 3L, and the ordinate shows the rate of deterioration of the bonding strength (the lower the level of FIG. 5, the less the bonding deterioration).

The curve drawn by the solid line shows the deterioration rate of the bonding strength of the lead joint (hereinafter referred to as the lead bonding strength), and the curve drawn by the broken line shows the bonding strength of the bump joint (hereinafter referred to as the bonding strength). This is referred to as bump bonding strength).

In the deterioration rate curve of the lead bonding strength (solid line), the deterioration rate decreases as the Au plating layer on the bonding surface on the bonding pad 5 side (hereinafter referred to as the pad side bonding surface) in the lead portion 3L1 becomes thicker. . That is, at the pad side joint surface of the lead portion 3L1,
It can be seen that it is better to make the u plating layer thicker.

Here, the reason why the lead bonding strength decreases when the Au plating layer is thin will be described.

The bonding pad 5 made of Al or the like and the lead portion 3L1 are set under a predetermined condition, for example, a load of 30 to 60 g,
When they are brought into contact with each other at a temperature of 200 to 230 ° C. and an ultrasonic wave of 0.15 to 0.30 W, Au atoms in the Au plating layer on the back surface of the lead portion 3L1 interdiffuse to bond the two.

In this state, left at high temperature, for example, 125 ° C.
When the treatment for 48 hours is performed, an intermetallic compound of Au and Al is generated at the bonding interface of the lead bonding part. The composition of this intermetallic compound has a property that the composition ratio of Au and Al differs depending on the amount of Au near the bonding interface.

That is, Au is bonded to the bonding interface of the lead bonding portion.
When the amount of Au is abundant, an Au ₅ Al ₂ alloy having a large mechanical strength is selectively formed. On the other hand, as the amount of Au decreases, an Au ₂ Al alloy having a slightly smaller mechanical strength is formed. When the amount of Au decreases, an AuAl ₂ alloy having lower mechanical strength is selectively produced.

As a result, the thinner the Au plated layer of the lead portion 3L1, the lower the lead bonding strength when left at high temperature.

Further, the Au plating layer also has a function of reducing the impact of the bonding tool during lead bonding. Therefore, if the thickness of this Au plating layer is made too thin, the impact of bonding is applied to the lead bonding surface via the relatively hard Ni, Cu, etc., so that the main surface of the semiconductor chip 1 under the bonding pad 5 is Damages. In this case, the lead bonding strength will be significantly reduced.

On the other hand, in the deterioration rate curve of the bump bonding strength (broken line), the deterioration rate increases as the Au plating layer on the bonding surface on the solder bump electrode 3B side (hereinafter referred to as the solder ball side bonding surface) in the bump land portion 3L2 increases. Is increasing. That is, it is understood that it is better to thin the Au plating layer on the solder ball side joint surface.

The reason why the bump bonding strength decreases when the gold plating layer is thick when left at high temperature will be described.

High temperature conditions at the time of bump bonding, for example, the maximum (M
ax) At 235 ° C. to 200 ° C. and under 45 seconds or more, Au atoms at the bonding interface forming the gold plating layer are, for example, 63% tin (Sn) -37 of the solder ball of the solder bump electrode 3B.
% Lead (Pb) is diffused almost uniformly.

When the concentration of Au diffused in the solder balls exceeds a predetermined concentration, the Au balls are left at a high temperature, for example, 125.
When the treatment is performed at 48 ° C. for 48 hours, the Au atoms diffused in the solder balls are selectively aggregated at the joint interface of the solder balls to bond with the Sn atoms in the solder balls to mainly form AuSn ₄ compound. To deposit.

The AuSn ₄ deposited here has a mechanically brittle property, and as a result, the bonding strength of the solder ball is lowered. Further, peeling of the solder bump electrode 3B may occur.

On the other hand, when the Au plating layer is thin and the concentration of Au diffused in the solder balls is smaller than the predetermined concentration, the above-mentioned high temperature treatment is carried out.
Since u and Sn have the property of not forming a compound even if they coexist, it is possible to prevent the formation of a mechanically brittle layer at the bonding interface of the solder ball, and to reduce the bonding strength of the solder bump electrode 3B. Do not invite.

Here, when the deterioration rates of both the lead bonding strength and the bump bonding strength are desired to be, for example, up to 30%, the thicknesses of the Au plating layers on the bonding surfaces of the lead bonding portion and the bump bonding portion are For example, it turns out that it is good to set as follows.

First, the thickness of the Au plating layer on the pad-side joint surface of the lead joint is, for example, 0.8 μm or more, preferably about 0.8 μm to 3.0 μm, which is practically suitable.
Here, the thickness of the Au plating layer is preferably 0.8 μm to 3.
The reason why 0 μm is set is for the following reason, for example.

That is, the thickness of the Au plating layer is 0.8 μm.
This is because if the thickness is made thinner, the deterioration rate of the bonding strength exceeds 30% as can be seen from FIG. Further, if the thickness of the Au plating layer is thinner than 0.8 μm, the bonding pad 5 and the semiconductor chip 1 below it may be damaged by the pressing force of the bonding tool at the time of lead bonding described later.

Further, if the thickness of the Au plating is thicker than 3.0 μm, it is preferable from the viewpoint of bonding strength, but it is expensive Au.
Is excessively used, which is unsuitable in terms of manufacturing cost.

On the other hand, the thickness of the Au plating layer on the solder ball side joint surface of the bump joint is, for example, 0.5 μm or less, preferably about 0.05 μm to 0.5 μm, which is practically suitable. Here, the thickness of the Au plating layer is preferably 0.
The reason why the thickness is set to 05 μm to 0.5 μm is for the following reason, for example.

That is, the lower limit of the thickness of the Au plated layer is not set to zero (0), because if Au plating is not applied at all, it easily oxidizes and corrodes, and the solder bump electrode 3B. This is because it was taken into consideration that a problem such as a decrease in solder wettability may occur. Also,
This is because if the thickness of this Au plating layer is thicker than 0.5 μm, the deterioration rate of the bonding strength will exceed 30%.

With this setting, the rate of deterioration of the bonding strength can be suppressed to less than 30% at both the lead bonding portion and the bump bonding portion, so that a highly reliable semiconductor integrated circuit device can be provided. Becomes

Further, since the minimum necessary Au plating layer can be formed on each of the lead bonding portion and the bump bonding portion, the amount of expensive Au used can be minimized, and the semiconductor integrated circuit device It is possible to reduce the manufacturing cost.

However, the thickness of the Au plating layer described here is for a product which is required to have a joint strength deterioration rate of both the lead joint portion and the bump joint portion not exceeding 30%. The thickness range of the Au plating layer is not limited, and the range of the thickness of the Au plating layer can be changed if the required deterioration rate of the bonding strength changes.

For example, depending on the product, the bump land portion 3L
In some cases, the bonding strength on the bump bonding side is not required as much as that of the lead bonding section having a small bonding area because the bonding area of 2 is large.

In this case, the deterioration rate of the bonding strength may not exceed 30% at the lead bonding portion, and the deterioration rate of the bonding strength may not exceed 35% at the bump bonding portion. In this case, the thickness of the Au plating layer on the pad side bonding surface of the lead bonding portion is, for example, about 0.8 μm or more, and the thickness of the Au plating layer on the solder ball side bonding surface in bump bonding is, for example, 0. It is about 7 μm or less.

When the bonding strength deterioration rate required for the lead bonding portion and the bump bonding portion is 50% or less, the Au plating layers on the pad side bonding surface and the bump side bonding surface are, for example, 0.6 μm to 1 μm. The shared thickness may be set within the range of 0.0 μm. That is, in this case, the thicknesses of the Au plating layers on the pad-side bonding surface and the bump-side bonding surface may be the same or may be different. However, in this case, even when the thickness of the Au plating layer on the pad-side bonding surface and the thickness of the Au plating layer on the bump-side bonding surface are equal, the required bonding strength is not limited to that of one bonding portion, but that of the lead bonding portion. It is possible to sufficiently obtain the joints at both the bump joint and the bump joint.

Next, the wiring 3L of the flexible wiring board 3
A specific example of the plating structure applied to the above will be described with reference to FIGS. Here, the deterioration rate of the joint strength of both the lead joint and the bump joint should not exceed 30%.
A case where the thickness of the u plating layer is set will be described.

Note that in FIGS. 6 to 15, the reference numeral 3Lb
Indicates the core portion of the wiring 3L. 7, FIG. 9, FIG. 11, FIG. 13, and FIG. 15 are schematic diagrams collectively showing the states of the plating layers on both the pad-side joint surface and the solder-ball-side joint surface of the wiring 3L. is there.

First, as shown in FIGS. 6 and 7, only the Au plating layers 3LmA1 and 3LmA2 are formed on the surface of the lead portion 3L1 and the solder ball side joint surface of the bump land portion 3L2.

For the above-mentioned reason, the core material portion 3Lb of the pad side joint surface of the lead portion 3L1 (the back surface of the lead portion 3L1) has a thickness of 0.8 μm to 3.0 μm (first gold layer). ) 3 LmA1 is coated. In the first embodiment, the thickness of the Au plated layer 3LmA1 is set to, for example, about 1.5 μm.

Further, the core portion 3L of the main surface side of the lead portion 3L1 and the solder ball side joint surface of the bump land portion 3L2
For the reason described above, b is coated with a gold plating layer (second gold layer) 3LmA2 having a thickness of 0.5 μm or less. In the first embodiment, the thickness of the Au plating layer 3LmA2 is set to about 0.3 μm, for example.

Second, as shown in FIGS. 8 and 9, nickel (Ni) plating layers (barrier metal layers) 3LmN1 and 3LmN2 are provided on the surface of the lead portion 3L1 and the solder ball side joint surface of the bump land portion 3L2. Au plating layer 3L
This is an example of the case where mA1 and 3LmA2 are formed.

The reason why the Ni plating layer is provided is that the core material portion 3L of the wiring 3L is used in the predetermined heat treatment of the semiconductor integrated circuit device.
This is because Cu that constitutes b is prevented from diffusing into the Au plating layers 3LmA1 and 3LmA2 and deteriorating the bonding strength of the lead bonding portion and the bump bonding portion.

The core material portion 3Lb on the pad side joint surface of the lead portion 3L1 is covered with the Au plating layer 3LmA1 via the Ni plating layer 3LmN1. This gold plating layer 3LmA1
For example, the thickness is set to 0.8 μm to 3.0 μm for the above reason, and is set to about 1.5 μm in the first embodiment.

Further, the core portion 3L of the main surface side of the lead portion 3L1 and the solder ball side joint surface of the bump land portion 3L2
b, the Au plating layer 3 via the Ni plating layer 3LmN2
LmA2 is coated. The thickness of the gold-plated layer 3LmA2 is 0.5 μm or less for the above-mentioned reason, and the first embodiment has the same thickness.
Then, for example, it is set to about 0.3 μm.

The Ni plating layers 3LmN1 and 3LmN2 both have a thickness of, for example, about 0 to 2.0 μm, preferably 0.5 μm.
Set to about. However, Ni plating layer 3LmN
The thicknesses of 1,3 LmN2 need not be equal.

Further, the Ni plating layer on the pad side bonding surface (back surface) of the lead bonding portion may be eliminated. Thereby, when the lead portion 3L1 is bonded to the bonding pad 5,
It is possible to avoid the problem that the semiconductor chip 1 is damaged due to the hard Ni plating layer in the lead portion 3L1.

Thirdly, as shown in FIGS. 10 and 11, an Au plating layer 3LmA1 is provided on the pad side bonding surface (back surface) of the lead portion 3L1 via a Ni plating layer 3LmN1.
Ni on the solder ball side joint surface of the bump land 3L2
This is an example in which only the plating layer 3LmN2 is provided.

The reason why the Ni plating layer 3LmN2 is provided on the solder ball side joint surface of the bump land portion 3L2 is that the core material portion 3Lb made of Cu is exposed without providing the Au plating layer on the solder ball side joint surface of the bump land 3L2. This is for preventing such problems as being easily oxidized, easily corroded, and reduced in wettability of solder if left to stand.

Bonding surface (back surface) of the lead portion 3L1 on the pad side
A core material portion 3Lb of the A through Ni plating layer 3LmN1
The u-plated layer 3LmA1 is covered. Gold plating layer 3L
For example, the thickness of mA1 is 0.8 μm to 3.0 μm for the above reason.
m, in the first embodiment, it is set to about 1.5 μm, for example.

Further, the core material portion 3Lb of the main surface side of the lead portion 3L1 and the solder ball side joint surface (main surface) of the bump land portion 3L2 is covered only with the Ni plating layer 3LmN2.

The thickness of each of the Ni plating layers 3LmN1 and 3LmN2 is, for example, about 0 to 2.0 μm, preferably 0.5.
It is set to about μm. However, Ni plating layer 3L
The thicknesses of mN1 and 3LmN2 may not be equal.

Also in this case, the Ni plating layer on the pad side joint surface of the lead joint portion may be omitted. This allows
When the lead portion 3L1 is bonded to the bonding pad 5, it is possible to avoid the problem that the semiconductor chip 1 is damaged due to the hard Ni plating layer on the lead portion 3L1.

Fourthly, as shown in FIGS. 12 and 13, an Au plating layer 3LmA1 is provided on the pad side joint surface (rear surface) of the lead portion 3L1, and palladium (Pd) is formed on the solder ball side joint surface of the bump land portion 3L2. ) Plating layer 3LmP1
This is an example of the case where is provided.

The reason why the Pd plating layer is provided on the upper surface of the bump land portion 3L2 is that if the core material portion 3Lb made of Cu is left exposed without providing the Au plating layer on the upper surface of the bump land 3L2, it is easily oxidized. This is to prevent problems such as easy corrosion and deterioration of solder wettability.

Bonding surface (back surface) of the lead portion 3L1 on the pad side
The side core member 3Lb is covered with an Au plating layer 3LmA1. The thickness of the gold plating layer 3LmA1 is, for example, 0.8 μm to 3.0 μm for the above reason, and in the first embodiment, for example,
It is set to about 1.5 μm.

Further, the core portion 3L of the main surface side of the lead portion 3L1 and the solder ball side joint surface of the bump land portion 3L2.
b is covered with a Pd plating layer 3LmP1. Pd
The thickness of the plating layer 3LmP1 is, for example, 0.05 μm to 1.0 μm.
m, preferably 0.1 μm to 0.2 μm.

Fifth, as shown in FIGS. 14 and 15, the Au plating layer 3LmA1 is provided on the pad side bonding surface (back surface) of the lead portion 3L1 via the Ni plating layer 3LmN1.
This is an example in which the Pd plating layer 3LmP1 is provided on the solder ball side bonding surface of the bump land portion 3L2 via the Ni plating layer 3LmN2.

The reason why the Ni plating layer is provided is that the core material portion 3L of the wiring 3L is used in the predetermined heat treatment of the semiconductor integrated circuit device.
This is because Cu that constitutes b is prevented from diffusing into the Au plating layer 3LmA1 and the Pd plating layer 3LmP1 and deteriorating the bonding strength of the lead bonding portion and the bump bonding portion.

Pad side bonding surface (back surface) of the lead portion 3L1
To the core material 3Lb of the Au via Ni plating layer 3LmN1
The plating layer 3LmA1 is covered. Gold plating layer 3Lm
The thickness of A1 is, for example, 0.8 μm to 3.0 μm for the above reason,
In the first embodiment, it is set to about 1.5 μm, for example.

Further, the core material portion 3L of the main surface side of the lead portion 3L1 and the solder ball side joint surface of the bump land portion 3L2
b, Pd plated layer 3L via Ni plated layer 3LmN2
mP1 is coated.

The thickness of the Pd plated layer 3LmP2 is, for example, 0.
05 μm to 1.0 μm, preferably, for example, 0.1 μm
It is set to about 0.2 μm. Ni plating layer 3Lm
The thicknesses of N1 and 3LmN2 are both set to, for example, about 0 to 2.0 μm, preferably about 0.5 μm. However, the thicknesses of the Ni plating layers 3LmN1 and 3LmN2 may not be equal.

Also in this case, the Ni plating layer on the pad side joint surface of the lead joint portion may be eliminated. This allows
When the lead portion 3L1 is bonded to the bonding pad 5, it is possible to avoid the problem that the semiconductor chip 1 is damaged due to the hard Ni plating layer on the lead portion 3L1.

Next, an example of the method of forming the Au plating layer as described above will be described with reference to FIG.

First, as shown in FIG. 16, a shield plate M is closely attached to the exposed surface side of the bump land portion 3L2 in the strip-shaped tape 3T having the wiring 3L formed in a pattern.

That is, in the wiring 3L of the flexible wiring board 3, the bump land portion 3L2 and the lead portion 3L.
The non-bonding surface side of 1 is covered with the shielding plate M, and the pad side bonding surface of the lead portion 3L1 of the flexible wiring board 3 is covered with the shielding plate M.
It is exposed from.

In this state, the flexible wiring 3 is placed in the plating bath. The plating method may be, for example, electrolytic plating or electroless plating. Then, the plating liquid does not come into contact with the bump land portion 3L2 covered with the shielding plate M so much, but efficiently comes into contact with the solder ball side joint surface of the lead portion 3L1 exposed from the shielding plate M. Therefore, the Au plating layer having a desired thickness can be formed on the lead joint surface of the lead portion 3L1.

Thereafter, the shield plate M is removed, and Au plating is similarly applied to the flexible wiring board 3. However, in this plating process, the Au plating layer is applied by the thickness required for the bump land portion 3L2 of the flexible wiring board 3.

By performing the Au plating treatment twice in this manner, the thickness of the lead portion 3L1 on the pad side joint surface is thick, and the thickness of the bump land portion 3L2 on the solder ball side joint surface is thin, whichever is suitable. It is possible to form the Au plating layer.

However, the method of forming the Au plated layer is not limited to this, and various modifications can be made. For example, first, a thin Au layer is formed on the surface of the lead portion 3L1 of the wiring 3L and the solder ball bonding surface of the bump land portion 3L2. After forming the plating layer, a shield plate M may be attached to the exposed surface side of the bump land portion 3L2 to form a thick Au plating layer on the pad side joint surface of the lead portion 3L1.

Next, a method of assembling the semiconductor integrated circuit device according to the first embodiment will be described along the process of FIG. 17 with reference to FIGS.

First, the elastomer 2 is formed on the flexible wiring board 3 by a printing method or the like (step 101).

The wiring 3L is already formed on the flexible wiring board 3 at this stage, and the lead portion 3L1 and the bump land portion 3L2 thereof are subjected to the above-described plating treatment.

However, at this stage, the lead portion 3L1 is not formed into a substantially S-shaped cross section but is flat.
Further, the tape 3T has a plurality of package forming regions integrated with each other and has a band shape.

The flexible wiring board 3 is formed, for example, as follows. First, a Cu foil is bonded to one entire surface of a strip tape made of, for example, a polyimide resin, for example, with an adhesive 6b. This Cu foil is
A rolled Cu foil or an electrolytic Cu foil may be used. continue,
The Cu foil is patterned by a photolithography technique and an etching technique to form the wiring 3L. Then, after forming an opening or the like in the tape 3T, the flexible wiring board 3 is formed by performing the above-described plating treatment on the exposed surface of the wiring 3L.

The printing method for forming the elastomer 2 is, for example, as follows. First, a metal mask 8m as shown in FIG. 18 is prepared. The metal mask 8m has two rectangular openings 8 arranged in parallel with each other.
m1 is perforated at a predetermined distance. The opening 8m1 is a printing area in which the elastomer 2 is formed.

Subsequently, as shown in FIG. 19, the metal mask 8m is arranged in a state of being aligned with the side of the flexible wiring board 3 on which the elastomer is formed, and then the silicone resin or the like supplied on the metal mask 8m is removed. The elastomer forming material 2A is stretched by the squeegee 9 in the printing direction of FIG. 19, and the opening 8m1 of the metal mask 8m
Pour through.

Then, the metal mask 8m is lifted.
As a result, the elastomer 2 formed in the shape of the opening 8m1 of the metal mask 8m is printed on the flexible wiring board 3.

However, the method of forming the elastomer 2 is not limited to the printing method, and various changes can be made. For example, the elastomer 2 which is desired to be a tape-shaped elastomer forming body.
Alternatively, the flexible wiring board 3 may be cut into the shape and size described above and bonded to the flexible wiring board 3 with an adhesive.

After the elastomer 2 is formed in this way, the adhesive 6a made of, for example, a silicone material is applied to the upper surface of the elastomer 2 by a printing method (step 10).
2) Then, the semiconductor chip 1 is adhered to the elastomer 2 via the adhesive 6a (step 103).

In this step, for example, the following is performed. First, the main surface of the semiconductor chip 1, that is, the surface on which the bonding pad 5 is formed is opposed to the surface of the elastomer 2 on which the adhesive 6a is applied.

Subsequently, the semiconductor chip 1 and the flexible wiring board 3 are planarly arranged so that the relative positions of the bonding pads 5 on the main surface of the semiconductor chip 1 and the lead portions 3L1 on the flexible wiring board 3 coincide with each other. The correct alignment.

After that, the semiconductor chip 1 is bonded to the elastomer 2 by the adhesive 6a by bringing the main surface of the semiconductor chip 1 into contact with the adhesive-coated surface of the elastomer 2 while maintaining such alignment.

In this way, the semiconductor chip 1 is attached to the elastomer 2
3L of flexible wiring board 3 after being adhered to
1 and the bonding pad 5 of the semiconductor chip 1 are bonded by a single bonding method or the like (step 104).

In this step, for example, the following is performed. First, after the main surface of the semiconductor chip 1 is turned to the bonding tool 10 side, the bonding tool 10 is arranged above the tip of the lead portion 3L1 as shown in FIG.

Then, the bonding tool 10 is vertically lowered to the main surface side of the semiconductor chip 1 (downward in FIG. 20) to bend the lead portion 3L1 as shown in FIG.

Further, as shown in FIG. 22, the bonding tool 10 is moved to the elastomer 2 to the extent that the tip of the lead portion 3L1 is located above the bonding pad 5.
Horizontally to the side (left in the figure) of the lead part 3
After the L1 is further bent, the L1 is lowered to the main surface side of the semiconductor chip 1, and the tip of the lead portion 3L1 and the bonding pad 5 are
And are joined by an ultrasonic thermocompression method or the like.

After the lead portion 3L1 of the flexible wiring board 3 and the bonding pad 5 of the semiconductor chip 1 are bonded in this manner, the groove exposed from the opening 3T1 of the tape 3T, that is, the side surfaces of the elastomer 2 facing each other. The sealing resin 7b is poured into the groove formed by the main surface of the semiconductor chip 1 by a dispenser method (step 10).
5).

As a result, the lead portion 3L1, the main surface of the semiconductor chip 1 and the bonding pad 5 are covered, and the reliability of the semiconductor integrated circuit device is improved.

Then, after such a sealing step, the strip-shaped tape 3 constituting the flexible wiring board 3 at this stage
The package outline of the CSP type semiconductor integrated circuit device is formed by cutting T at a position slightly outside the outer circumference of the semiconductor chip 1 (step 106).

At this stage, the side surface of the semiconductor chip 1 and the side surface of the elastomer 2 may be covered with the sealing resin 7a. This makes it possible to further improve the reliability of the semiconductor integrated circuit device.

The bump land portion 3L2 of the wiring board 3
To the bump land 3 without solder bump electrodes
In the case of a so-called land grid array type semiconductor integrated circuit device in which L2 is left exposed, a pass / fail test is performed at this stage and the assembly process is completed.

Then, after the above-mentioned tape cutting step, solder balls made of, for example, Pb-Sn alloy are bonded to the bump land portions 3L2 of the flexible wiring board 3 to form the solder bump electrodes 3B (step 10).
7).

Thereafter, the CSP type semiconductor integrated circuit device is subjected to a predetermined inspection to determine whether it is good or bad (step 108). Thus, the assembly process of the CSP type semiconductor integrated circuit device is completed.

Next, FIGS. 23 and 24 show the case where the CSP type semiconductor integrated circuit device of the first embodiment is applied to a memory card.

On the printed wiring board 12 which constitutes the memory card 11, a plurality of CSPs described in this embodiment are provided.
-Shaped semiconductor integrated circuit device 13 and, for example, one QFP
A (QuadFlat Package) type semiconductor integrated circuit device 14 is mounted.

Each CSP type semiconductor integrated circuit device 13 includes, for example, a DRAM, an SRAM, a mask ROM (Read O
nly Memory) or EEPROM (Electrically Erasa
ble Programmable ROM) and other memory circuits are formed. The solder bump electrodes 3B of the CSP type semiconductor integrated circuit device 13 are electrically connected to the lands of the printed wiring board 12.

In the case of the so-called land grid array type semiconductor integrated circuit device described above, a solder ball for forming the solder bump electrode 3B may be attached to the land side of the printed wiring board 12.

Further, a QFP type semiconductor integrated circuit device 14
For example, a control circuit for controlling the operation of each CSP type semiconductor integrated circuit device and the operation of the entire memory circuit of the memory card 11 is formed. The lead portion 14a of the QFP type semiconductor integrated circuit device 14 is electrically connected to the land of the printed wiring board 12. The control circuit may be provided on the side of the information processing device in which the memory card 11 is mounted.

Each CSP type semiconductor integrated circuit device 13 and Q
The FP type semiconductor integrated circuit device 14 is electrically connected to the lands and the wirings formed on the printed wiring board, whereby a memory circuit having a predetermined configuration is formed in the memory card.

The wiring of the printed wiring board 12 is electrically connected to a plurality of terminals 15 which are regularly arranged at a predetermined interval on one short side of the printed wiring board 12.
The terminal 15 is a connection terminal for electrically connecting the storage circuit of the predetermined configuration of the memory card 11 and the interface circuit of the information processing device in which the memory card 11 is mounted.

In this memory card 11, since the CSP type semiconductor integrated circuit device 13 as in the first embodiment is used as a memory, the memory card 11 can be made small, lightweight and thin, and the memory capacity can be reduced. It is possible to drive growth.

As described above, according to the first embodiment, the following effects can be obtained.

(1). Lead part 3 of flexible wiring board 3
The thickness of the Au plating layer on the pad side joint surface of L1 and
By changing the thickness of the Au plating layer on the solder ball side joint surface of the bump land portion 3L2, sufficient bonding is achieved on both the pad side joint surface and the solder ball side joint surface even after being left at a high temperature due to an aging test or the like. It becomes possible to obtain strength.

(2). Since the minimum necessary Au plating layer can be formed on each of the lead bonding portion and the bump bonding portion without lowering the bonding strength of each, the expensive Au plating layer is expensive.
It is possible to minimize the use amount of the semiconductor integrated circuit device and reduce the manufacturing cost of the semiconductor integrated circuit device.

(3). On the pad side joint surface of the lead portion 3L1, between the core material portion 3Lb and the Au plating layer 3LmA1 and on the solder ball side joint surface of the bump land portion 3L2, the core material portion 3Lb and the Au plating layer 3LmA2 are formed. By providing the Ni plating layers 3LmN1 and 3LmN2 between them, Cu of the core material portion 3Lb is changed to Au plating layers 3LmA1 and 3LmA2 during heat treatment such as manufacturing process and mounting process of the semiconductor integrated circuit device.
Since it can be suppressed from diffusing into the joint, it is possible to improve the reliability of joining of the respective joints.

(4) According to the above (1) to (3), it becomes possible to manufacture a highly reliable semiconductor integrated circuit device at low cost.

(Embodiment 2) FIG. 25 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention, FIG. 26 is a sectional view taken along line XXVI-XXVI of FIG. 25, and FIG. 27 is of FIG. FIG. 6 is an explanatory diagram for explaining a plating method for a wiring board of a semiconductor integrated circuit device.

In the semiconductor integrated circuit device according to the second embodiment, as shown in FIGS. 25 and 26, the tape 3T on which the wiring 3L of the flexible wiring board 3 is not formed is formed.
The surface is brought into contact with the elastomer 2 and the wiring 3L on the tape 3T is covered with a photosensitive insulating film 16 such as a solder resist. Other than this, the structure is the same as that of the first embodiment.

The photosensitive insulating film 16 is made of a material containing, for example, epoxy, polystyrene, polyimide or the like, has heat resistance and has a property of not getting wet with solder, and deterioration of the surface of the wiring board due to moisture or contamination. It is preferable to have the property of preventing the above-mentioned phenomenon and further withstanding the exposure to the flux and the cleaning liquid. The photosensitive insulating film 16
It also includes a polymer material whose chemical and physical properties are changed by irradiation with radiation such as electron beam.

In the structure in which the elastomer 2 is formed on the wiring forming surface side of the flexible wiring substrate 3, voids are formed in the gap between the wiring 3L and the wiring 3L when the elastomer 2 is formed on the wiring forming surface. It may be formed.

However, this void expands during the heat treatment in the manufacturing process or mounting process of this semiconductor integrated circuit device, which may cause deformation, peeling or destruction of the flexible wiring board 3.

Therefore, in the second embodiment, by forming the elastomer 2 on the flat tape 3T,
Since voids can be prevented from being formed between the flexible wiring board 3 and the elastomer 2 when the elastomer 2 is formed, C at the time of heat treatment such as manufacturing or mounting can be prevented.
It is possible to improve the reliability of the SP type semiconductor integrated circuit device.

Also, the opening 3T punched in the tape 3T.
In the case of the structure in which the solder bump electrode 3B and the bump land portion 3L2 of the wiring 3L are connected through 2 (see FIGS. 1 and 2), the opening 3T2 is formed by a mechanical processing method such as punching. There is a limit to the lower limit of the opening diameter, which hinders the size reduction of the solder bump electrode 3B, and the aspect ratio (ratio between the opening depth and the opening diameter) of the opening 3T2 increases as the solder bump electrode 3B becomes finer.
There is also a risk that the reliability of the joint between the solder bump electrode 3B and the bump land portion 3L2 may be reduced.

Therefore, in the second embodiment, the wiring 3L on the tape 3T is covered with the photosensitive insulating film 16 which can be formed thinner than the tape 3T, and the photosensitive insulating film 16 is formed by the photolithography technique. The opening 16a is bored, and the solder bump electrode 3B and the bump land 3L2 of the wiring 3L are bonded to each other through the opening 16a.

In this case, since the opening 16a for connecting the solder bump electrode 3B and the bump land 3L2 is formed by the photolithography technique capable of fine processing,
Opening 3T2 formed on the tape 3T (see FIGS. 1 and 2)
It is possible to form a smaller opening 16a.

Further, since the photosensitive insulating film 16 can be formed thinner than the tape 3T, it is possible to prevent the aspect ratio of the opening 16a from increasing, and the solder bump electrode 3 can be prevented.
It is also possible to improve the reliability of the connection between B and the bump land portion 3L2.

In the semiconductor integrated circuit device having such a structure, the plating method applied to the wiring 3L of the flexible wiring board 3 is basically the same as that described in the first embodiment.

That is, as shown in FIG. 27, the wiring 3L
The photosensitive insulating film 16 is applied on the wiring forming surface of the strip-shaped tape 3T on which the pattern is formed, the opening 16a is formed by the photolithography technique, and further cured.

Subsequently, in the strip-shaped tape 3T on which the wiring 3L is patterned, the photosensitive insulating film 16 is unwound on the exposed surface side of the bump land portion 3L2, and the shielding plate M is tightly covered.

That is, in the wiring 3L of the flexible wiring board 3, the bump land portion 3L2 and the lead portion 3L1.
The non-bonding surface side is covered with the shielding plate M, and the pad-side bonding surface of the lead portion 3L1 of the flexible wiring board 3 is exposed from the shielding plate M.

In this state, the flexible wiring 3 is put into the plating bath. The plating method may be, for example, electrolytic plating or electroless plating. Then, the plating liquid does not come into contact with the bump land portion 3L2 covered with the shielding plate M so much, but efficiently comes into contact with the solder ball side joint surface of the lead portion 3L1 exposed from the shielding plate M. Therefore, the Au plating layer having a desired thickness can be formed on the lead joint surface of the lead portion 3L1.

Thereafter, the shielding plate M is removed, and Au plating is similarly applied to the flexible wiring board 3. However, in this plating process, the Au plating layer is applied by the thickness required for the bump land portion 3L2 of the flexible wiring board 3.

By thus performing the Au plating treatment in two times, the lead side 3L1 has a thick bonding surface on the pad side and the bump land 3L2 has a small thickness on the bonding surface on the solder ball side. It is possible to form the Au plating layer.

However, the method of forming the Au plating layer is not limited to this, and various changes can be made. For example, first, a thin Au layer is formed on the surface of the lead portion 3L1 of the wiring 3L and the solder ball bonding surface of the bump land portion 3L2. After forming the plating layer, a shielding plate M may be attached to the exposed surface side of the bump land portion 3L2 to form a thick Au plating layer on the pad side joint surface of the lead portion 3L1.

As described above, according to the second embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

(1). By forming the elastomer 2 on the flat tape 3T, it is possible to prevent a void from being formed between the flexible wiring board 3 and the elastomer 2 when the elastomer 2 is formed. It is possible to prevent the semiconductor integrated circuit device from being broken during manufacturing and mounting.

(2). Wiring 3L on flexible wiring board 3
Since the insulating film 16 is covered with the photosensitive insulating film 16, the opening 16a for connecting the solder bump electrode 3B and the bump land 3L2 can be formed by a photolithography technique capable of fine processing.
It is possible to make a smaller than the opening of the tape 3T. Therefore, the size reduction of the solder bump electrode 3B can be promoted.

(3). Wiring 3L on flexible wiring board 3
Is covered with the photosensitive insulating film 16 that can be formed thinner than the tape 3T, the increase in the aspect ratio of the opening 16a can be prevented, and the solder bump electrode 3B and the bump land 3L2 can be joined together. It is possible to improve the reliability of.

(4). Due to the above (1) to (3), the reliability and yield of the CSP type semiconductor integrated circuit device can be improved.

(Embodiment 3) FIG. 28 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 29 is a sectional view taken along line XXIX-XXIX in FIG.

In the semiconductor integrated circuit device of the third embodiment, as shown in FIGS. 28 and 29, a plurality of bonding pads 5 are arranged near the outer periphery of the main surface of semiconductor chip 1. On the main surface of the semiconductor chip 1, a flexible wiring board 3 having an outer shape smaller than the outer shape of the semiconductor chip 1 is bonded via an elastomer 2 having a flat rectangular shape.

A plurality of lead portions 3L1 extending in the outer peripheral direction of the semiconductor chip 1 are projected from the outer periphery of the flexible wiring board 3, and the tips of the lead portions 3L1 form bonding pads 5 on the main surface of the semiconductor chip 1. It is electrically connected.

On the main surface of the flexible wiring board 3, a plurality of solder bump electrodes 3B are regularly arranged with a predetermined distance. Each solder bump electrode 3B is
It is electrically connected to the bump land portion 3L2 of the flexible wiring board 3 through the opening 3T1 formed in the tape 3T.

The outer peripheral side surfaces of the elastomer 2 and the flexible wiring board 3 are covered with a sealing resin 7a, which covers the main surface of the semiconductor chip 1, the bonding pads 5 and the lead portions 3L1. .

Except for such a constitution, it is the same as the first embodiment. Therefore, according to the third embodiment, it is possible to obtain the same effect as that obtained in the first embodiment.

(Embodiment 4) FIG. 30 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 31 is a sectional view taken along line XXXI-XXXI of FIG.

The semiconductor integrated circuit device according to the fourth embodiment is
As shown in FIGS. 30 and 31, the structure is basically the same as that described in the third embodiment. The difference is that the surface of the flexible wiring substrate 3 on which the wiring 3L is not formed is in contact with the elastomer 2.
That is, the wiring 3L on the tape 3T is covered with a photosensitive insulating film 16 such as a solder resist.

That is, in the fourth embodiment, the elastomer 2 is formed on the flat tape 3T of the flexible wiring board 3 as in the second embodiment.

Further, in the fourth embodiment, similarly to the second embodiment, the photosensitive insulating film 16 capable of forming the wiring 3L on the tape 3T thinner than the tape 3T.
The photosensitive insulating film 16 is covered with an opening 16a by photolithography, and the solder bump electrode 3B and the bump land 3L2 of the wiring 3L are bonded to each other through the opening 16a.

Therefore, in the fourth embodiment,
In addition to the effect obtained in the third embodiment, the effect obtained in the second embodiment can be obtained.

(Fifth Embodiment) FIG. 32 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 33 is a sectional view taken along line XXXIII-XXXIII of FIG.

The semiconductor integrated circuit device according to the fifth embodiment is
As shown in FIGS. 32 and 33, the protective member 17 is provided. The protection member 17 is made of a metal having a high thermal conductivity such as Cu, for example, and a recess having a concave cross section is formed in the center of one surface of the protection member 17, and the semiconductor chip 1 has the main surface in the recess. Is directed downward in FIG. 33.

The back surface of the semiconductor chip 1 is bonded to the bottom surface of the recess of the protection member 17 via the adhesive 6c. The four side surfaces of the semiconductor chip 1 are surrounded by the leg portions 17a on the outer circumference of the protection member 17 extending so as to surround the four side surfaces.

Therefore, the heat generated during the operation of the semiconductor chip 1 can be dissipated from the back surface and the side surface of the semiconductor chip 1 through the protective member 17.

The main surface of the semiconductor chip 1 is exposed from the protection member 17, and the height of the main surface is set to be substantially equal to the top surface height of the leg portion 17a on the outer periphery of the protection member 17. . In the vicinity of the outer periphery of the main surface of the semiconductor chip 1, a plurality of bonding pads 5 are formed along the outer periphery.
Is arranged.

On the main surface of the semiconductor chip 1, a planar quadrangular elastomer 2a formed so as to expose a bonding pad forming region is adhered via an adhesive 6a.

On the leg portion 17a of the protection member 17,
The planar frame-shaped elastomer 2b formed along the shape of the upper surface of the leg 17a is adhered via the adhesive 6d. The elastomers 2a and 2b are formed at the same time, for example, and the heights of the upper surfaces of the elastomers are substantially the same.

On such elastomers 2a, 2b,
The flexible wiring board 3 is joined with the surface of the wiring 3L formed on the tape 3T facing the elastomers 2a, 2b.

In this flexible wiring board 3, at a position on the four sides of the semiconductor chip 1, a relatively wide 4 is formed so that the bonding pads 5 on the outer periphery of the semiconductor chip 1 are exposed.
Two openings 3T1 are formed.

That is, the flexible wiring board 3 is composed of a rectangular portion arranged on the main surface of the semiconductor chip 1 and a frame-shaped portion arranged on the leg portions 17a of the protective member 17. The rectangular portions are connected and supported by tapes 3T extending from the four corners to the four inner peripheral corners of the frame-shaped portion.

The lead portion 3L1 of the wiring 3L projects from the outer periphery of the rectangular portion of the flexible wiring board 3. The lead portion 3L1 is electrically connected to the bonding pad 5 on the outer periphery of the main surface of the semiconductor chip 1 while being bent in a substantially S-shaped cross section, for example.

The bump land portion 3L2 of the wiring 3L in the rectangular portion of the flexible wiring board 3 is the tape 3
It is electrically connected to the solder bump electrode 3B through the opening 3T2 formed in the hole T. On the main surface of the rectangular portion of the flexible wiring board 3, the solder bump electrodes 3B are regularly arranged at a predetermined distance.

On the other hand, the lead portion 3L1 of the wiring 3L also projects from the inner periphery of the frame-shaped portion of the flexible wiring board 3. The lead portion 3L1 is electrically connected to the bonding pad 5 on the outer periphery of the main surface of the semiconductor chip 1 while being bent in a substantially S-shaped cross section, for example. Since the plating structure of the lead portion 3L1 is also the same as that of the first embodiment, its explanation is omitted.

Further, the bump land portion 3L2 of the wiring 3L in the frame-shaped portion of the flexible wiring substrate 3 is the tape 3T.
Through the opening 3T2 drilled in the solder bump electrode 3
It is electrically connected to B. The plating structure of the bump land portion 3L2 is also the same as that in the first embodiment, and therefore its explanation is omitted.

On the main surface of the frame-shaped portion of flexible wiring board 3, solder bump electrodes 3B are regularly arranged along the outer periphery of the frame-shaped portion. That is, the solder bump electrodes 3 are also formed on the main surface of the frame-shaped portion of the flexible wiring board 3 arranged outside the outer periphery of the semiconductor chip 1.
B is arranged.

As a result, the number of solder bump electrodes 3B that can be arranged can be increased as compared with the case where the solder bump electrodes 3B are provided only on the rectangular portion of the flexible wiring board 3. It has a structure that can meet pin requirements.

The groove portion exposed from the opening 3T1 of the flexible wiring board 3 is filled with the sealing resin 7c. As a result, the main surface of the semiconductor chip 1, the bonding pad 5 and the lead portion 3L1 are covered, so that the reliability of the semiconductor integrated circuit device can be improved.

As described above, according to the fifth embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

(1). Since the solder bump electrodes 3B can be arranged also on the frame-shaped portion of the flexible wiring board 3 arranged outside the outer periphery of the semiconductor chip 1, it is possible to meet the multi-pin requirement of the semiconductor integrated circuit device. It becomes possible to respond.

(2). A protective member 17 is provided on the outer periphery of the semiconductor chip 1.
By providing the above, it is possible to improve the transportability by being strong against external impact.

(3). The back surface of the semiconductor chip 1 is protected by the protective member 17
With the structure in which the side surface of the semiconductor chip 1 is surrounded by the protective member 17, the heat can be dissipated from the back surface and the side surface of the semiconductor chip 1, so that the heat dissipation performance of the semiconductor integrated circuit device can be improved. It will be possible. Therefore, it is possible to improve the operational reliability and life of the semiconductor integrated circuit device.

(Embodiment 6) FIG. 34 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 35 is a sectional view taken along line XXXV-XXXV of FIG.

The semiconductor integrated circuit device according to the sixth embodiment is
As shown in FIGS. 34 and 35, the structure is basically the same as that described in the fifth embodiment. The difference is that the surface of the flexible wiring substrate 3 on which the wiring 3L is not formed is in contact with the elastomer 2.
That is, the wiring 3L on the tape 3T is covered with a photosensitive insulating film 16 such as a solder resist.

That is, the sixth embodiment has a structure in which the elastomer 2 is formed on the flat tape 3T of the flexible wiring board 3 as in the second embodiment.

Further, in the sixth embodiment, similarly to the second embodiment, the photosensitive insulating film 16 capable of forming the wiring 3L on the tape 3T thinner than the tape 3T.
The photosensitive insulating film 16 is covered with an opening 16a by photolithography, and the solder bump electrode 3B and the bump land 3L2 of the wiring 3L are bonded to each other through the opening 16a.

Therefore, in the sixth embodiment,
In addition to the effect obtained in the fifth embodiment, the effect obtained in the second embodiment can be obtained.

(Embodiment 7) FIG. 36 is a plan view showing the principal part of a semiconductor integrated circuit device according to another embodiment of the present invention.
7 is a sectional view taken along the line XXXVII-XXXVII in FIG.

In the seventh embodiment, as shown in FIGS. 36 and 37, an opening 3T1 penetrating the upper and lower surfaces of the tape 3T is formed in the center of the flexible wiring board 3 and the opening is formed. The semiconductor chip 1 is arranged well in the portion 3T1 with its main surface exposed. The main surface of the semiconductor chip 1 is a tape 3
It is arranged so as to face the flat surface (non-wiring formation surface) of T.

[0218] The tape 3T of this flexible wiring board 3
A protective frame 18a extending along the outer periphery of the tape 3T is adhered to the vicinity of the outer periphery of the back surface of the tape 3T via an adhesive 6e. This prevents the flexible wiring board 3 from being deformed.

Further, the tape 3 of the flexible wiring board 3
The wiring 3L is adhered to the main surface of T with an adhesive 6b. Further, a photosensitive insulating film 16 such as a solder resist is deposited on the main surface of the tape 3T,
This covers the wiring 3L.

The lead portion 3L1 of the wiring 3L is projected from the inner circumference of the flexible wiring board 3 and is formed into, for example, a substantially S-shaped cross section and electrically connected to the bonding pad 5 near the outer circumference of the semiconductor chip 1. . This lead part 3
L1 is also plated as in the first embodiment.

The bump land portion 3L2 of the wiring 3L is electrically connected to the solder bump electrode 3B through a fine opening 16a formed in the photosensitive insulating film 16.
The bump bonding surface of the bump land portion 3L2 is also plated as in the first embodiment. The solder bump electrodes 3B are regularly arranged on the main surface of the flexible wiring board 3 along the outer periphery thereof.

The opening 3T of the flexible wiring board 3 is filled with the sealing resin 7d. As a result, the semiconductor chip 1 is relatively firmly fixed.
Further, the main surface and side surface of the semiconductor chip 1, the bonding pad 5 and the lead portion 3L1 are covered, so that the structure of the semiconductor integrated circuit device can be improved. Note that, in FIG. 36, the sealing resin 7d is not shown in order to make the drawing easy to see.

As described above, according to the seventh embodiment, it is possible to obtain the same effects as those obtained in the first and second embodiments.

(Embodiment 8) FIG. 38 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention.

The semiconductor integrated circuit device according to the eighth embodiment is
As shown in FIG. 38, the structure is basically the same as that described in the seventh embodiment. The plan view is the same as FIG. 36 used in the seventh embodiment.

The difference is that the height of the main surface of the semiconductor chip 1 and the height of the surface of the flexible wiring substrate 3 on which the wiring 3L is formed are set to be substantially the same, and the lead portion 3 of the wiring 3L is set.
That is, L1 is electrically connected to the bonding pad 5 on the main surface of the semiconductor chip 1 in a flat state.

That is, the lead portion 3L1 is not bent. However, the lead bonding surface of the lead portion 3L1 and the bump bonding surface of the bump land portion 3L2 are plated in the same manner as described in the first embodiment.

Therefore, also in the eighth embodiment, it is possible to obtain the same effects as those obtained in the first and second embodiments.

(Embodiment 9) FIG. 39 is a sectional view showing an essential portion of a semiconductor integrated circuit device according to another embodiment of the present invention.

The semiconductor integrated circuit device according to the ninth embodiment is
As shown in FIG. 39, the structure is basically the same as that described in the seventh embodiment. The plan view of the bump electrode formation surface side is the same as FIG. 36 used in the seventh embodiment. The differences are as follows.

First, the height of the main surface of the semiconductor chip 1 and
The height of the surface of the flexible wiring board 3 on which the wiring 3L is formed is set to be substantially the same, and the lead portion 3L1 of the wiring 3L is set.
Is electrically connected to the bonding pad 5 on the main surface of the semiconductor chip 1 in a flat state.

That is, the lead portion 3L1 is not bent. However, the lead bonding surface of the lead portion 3L1 and the bump bonding surface of the bump land portion 3L2 are plated in the same manner as described in the first embodiment.

Second, the back surface of the semiconductor chip 1 has the adhesive 6
It is joined to the heat dissipation plate 19 by f and has a structure capable of dissipating the heat generated in the semiconductor chip 1 from the back surface of the semiconductor chip 1.

The heat dissipation plate 19 is made of a metal having a high thermal conductivity such as Cu. The adhesive material 6f is made of an adhesive material having heat dissipation and heat resistance, for example.

Between the outer peripheral surface of the heat dissipation plate 19 and the non-bump electrode forming surface of the tape 3T, a protective frame 18b having substantially the same shape as that of the tape 3T is installed so as to surround the side surface of the semiconductor chip 1. There is. The protective frame 18b is joined to the heat dissipation plate 19 with an adhesive 6g.

The protective frame 18b is made of the same material as the heat dissipation plate 19, for example. This is because the semiconductor chip 1 has a function of dissipating the heat generated, the bondability with the heat dissipation plate 19 is taken into consideration, and the reliability of the connection with the heat dissipation plate 19 when heat is generated is taken into consideration. It is because of things. Also, 6 g of adhesive
Is also made of an adhesive material having heat dissipation and heat resistance, for example.

The main surface of the semiconductor chip 1 and the lead portion 3L1 are covered with the sealing resin 7d, which has a structure that improves the reliability of the semiconductor integrated circuit device.

As described above, in the ninth embodiment,
In addition to the effects obtained in the first and second embodiments, the following effects can be obtained.

(1) By having the structure in which the semiconductor chip 1 is surrounded by the protective frame 18b and the heat radiating plate 19, it is possible to improve impact resistance from the outside and improve transportability.

(2). Since the back surface of the semiconductor chip 1 is joined to the heat dissipation plate 19 and the side surface of the semiconductor chip 1 is surrounded by the protective frame 18b having a high heat dissipation property, Since heat can also be dissipated, it is possible to improve the heat dissipation performance of the semiconductor integrated circuit device. Therefore, it is possible to improve the operational reliability and life of the semiconductor integrated circuit device.

(Embodiment 10) FIG. 40 is a plan view of essential parts of a semiconductor integrated circuit device according to another embodiment of the present invention, FIG. 41 is a sectional view taken along line XXXXI-XXXXI of FIG. 40, and FIGS. 44 is a cross-sectional view of essential parts in the process of manufacturing the semiconductor integrated circuit device of FIG.

In the tenth preferred embodiment, as shown in FIGS. 40 and 41, in the opening 4b1 of the passivation film 4b formed in the uppermost layer of the main surface of the semiconductor chip 1, the tip side of the lead portion 3L1 is provided. The open end located is
It is formed so as to recede in a direction away from the bonding pad 5 as compared with the case of the first embodiment.

The other structure is the same as that of the first embodiment. Although the wiring 3L in FIG. 41 does not show a plating structure, it is subjected to the same plating process as in the first embodiment.

In this semiconductor integrated circuit device, the lead portion 3
When L1 and the bonding pad 5 are bonded by a bonding tool, as described in the first embodiment, the lead portion 3L1 is driven down to a position where it is in contact with the main surface of the semiconductor chip 1 and then the bonding is performed. It is shifted in a direction perpendicular to the lowering direction, and further, it is hit down on the bonding pad 5.

For this reason, the pad-side bonding surface of the lead portion 3L1 may come into contact with the main surface of the semiconductor chip 1 at the time of the first-down, and therefore the passivation film 4b and the semiconductor chip 1 are not exposed. Do damage,
The components of the passivation film 4b may adhere to the pad-side bonding surface of the lead portion 3L1 to deteriorate the bondability.

Therefore, in the tenth embodiment, the opening end on the front end side of the lead portion 3L1 in the opening 4b1 of the passivation film 4b formed in the uppermost layer of the main surface of the semiconductor chip 1 is formed in the lead bonding step. Lead part 3
It is formed by retreating in the direction away from the bonding pad 5 to the extent that the lead portion 3L1 does not come into contact with the passivation film 4b on the main surface of the semiconductor chip 1 when L1 is driven down to the main surface side of the semiconductor chip 1. ing.

Here, in the first embodiment, the length from the end of the opening 4a1 of the passivation film 4a to the end of the opening 4b1 of the passivation film 4b is
For example, it is about 25 μm.

The size of the pressing surface of the bonding tool is equal to or slightly smaller than that of the bonding pad 5. The size of the bonding pad 5 is, for example, 10
It is about 0 μm × 100 μm.

Therefore, the length L from the end of the opening 4a1 of the passivation film 4a to the end of the opening 4b1 of the passivation film 4b in the tenth embodiment is not defined because it depends on the product. For example, about 125 μm is preferable.

Next, a bonding process between the lead portion 3L1 and the bonding pad 5 in the semiconductor integrated circuit device of the tenth embodiment will be described with reference to FIGS. 42 to 44, although the wiring 3L does not show the plating structure, the same plating process as that of the first embodiment is applied.

First, after the main surface of the semiconductor chip 1 is turned to the bonding tool 10 side, the bonding tool 10 is placed above the tip of the lead portion 3L1 as shown in FIG.

Subsequently, the bonding tool 10 is vertically pushed down to the main surface side of the semiconductor chip 1 (downward in FIG. 42) to bend the lead portion 3L1 as shown in FIG.

At this time, since there is no passivation film 4b below the lead portion 3L1, for example, the passivation film 4 or the semiconductor chip 1 may be damaged, or the passivation film 4b on the pad side bonding surface of the lead portion 3L1.
Components may adhere and deteriorate the bondability.
There is no problem caused by the contact of the lead portion 3L1 with the passivation film 4b.

Next, the bonding tool 10 is
After the lead portion 3L1 is moved horizontally to the side surface of the elastomer 2 (to the left in FIG. 43) to the extent that the tip portion of the lead portion 3L1 is located above the bonding pad 5, the bonding tool 10
Is lowered to the main surface side of the semiconductor chip 1 and, as shown in FIG. 44, the tip of the lead portion 3L1 and the bonding pad 5 are bonded by ultrasonic thermocompression bonding or the like.

As described above, according to the tenth embodiment,
In addition to the effects obtained in the first embodiment, the following effects can be obtained.

(1). In the opening 4b1 of the passivation film 4b in the uppermost layer of the main surface of the semiconductor chip 1, the opening end on the tip side of the lead portion 3L1 is bonded to the bonding pad 5
It is possible to prevent the lead portion 3L1 from coming into contact with the passivation film 4b when the lead portion 3L1 is pushed down to the main surface side of the semiconductor chip 1 in the lead bonding step by retreating in the direction away from the lead chip 3L1. Become.

(2) According to the above (1), it is possible to avoid the problem that the lead portion 3L1 damages the main surface side of the semiconductor chip 1 during the lead joining process.

(3) Due to the above (1), it is possible to avoid the problem that the component of the passivation film 4b adheres to the pad side joint surface of the lead portion 3L1 during the lead joining process and deteriorates the bondability. It is possible to improve the reliability of bonding between 3L1 and the bonding pad 5.

(4). Due to the above (1) to (3), it is possible to improve the yield and reliability of the semiconductor integrated circuit device.

(Embodiment 11) FIG. 45 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention.

The structure of the semiconductor integrated circuit device of the eleventh embodiment shown in FIG. 45 is almost the same as the structure of the semiconductor integrated circuit device of the second embodiment. The difference is that the second layer wiring 3L is provided between the elastomer 2 and the back surface of the tape 3T of the flexible wiring substrate 3.

The second layer wiring 3L is a wiring for a reference voltage such as a power supply voltage or a ground voltage.
It is formed so as to cover the entire back surface of the tape 3T. Therefore, in the tape 3T, the second-layer wiring 3
No unevenness due to the second layer wiring 3L is formed on the surface on which L is formed. That is, the surface of the flexible wiring board 3 in contact with the elastomer 2 is flat.

Therefore, it is possible to prevent voids from being formed between the flexible wiring board 3 and the elastomer 2 when the elastomer 2 is formed, so that a CSP type semiconductor during heat treatment such as manufacturing and mounting. It is possible to prevent the destruction of the integrated circuit device.

The second-layer wiring 3L is electrically connected to the solder bump electrode 3B through the opening 3 formed in the tape 3T and the photosensitive insulating film 16.

An insulating film 21 is provided in a portion of the opening 20 in contact with the first layer wiring 3L, and the solder bump electrode 3B and the first layer wiring 3L are insulated from each other.

The core material portion of the second-layer wiring 3L is, for example, C
The same plating treatment as that in the first embodiment is applied to the surface of the lead portion and the bump bonding surface of the bump land portion which are made of u or the like and connect the wiring 3L of the second layer and the bonding pad 5. .

Therefore, in the eleventh embodiment, the following effects can be obtained in addition to the effects obtained in the first and second embodiments.

(1). The wiring layer of the flexible wiring board 3 is 2
By using the layer, the degree of freedom in routing the wiring can be improved, so that the ease of wiring design of the flexible wiring board 3 can be improved.

(2). The wiring layer of the flexible wiring board 3 is 2
Since one wiring layer is a solid wiring layer for a reference voltage such as a power supply voltage or a ground voltage, noise generated in the wiring 3L of the other wiring layer can be reduced. It is possible to improve the operational reliability of the integrated circuit device.

(Embodiment 12) FIG. 46 is a sectional view showing the principal part of a semiconductor integrated circuit device according to another embodiment of the present invention. FIGS. 47 (a) and 47 (b) are views showing the semiconductor integrated circuit device of FIG. FIG. 48 is an explanatory diagram schematically showing a cross-sectional state of the wiring in the flexible wiring, and FIG. 48 is an explanatory diagram for explaining cracks in the lead portion of the flexible wiring board.

In the twelfth embodiment, as shown in FIGS. 46 and 47, the Ni plating layer 3LmN1, is formed only on the surface portion of the lead portion 3L1 on the lead joint portion side and on the solder ball side joint surface of the bump land portion 3L2. 3LmN2 is formed. Other than this, the configuration is the same as that of the semiconductor integrated circuit device of the first embodiment.

In the structure in which the Ni plating layer is formed on the entire surface of the lead portion 3L1, since the Ni plating layer is hard and brittle, as shown in FIG. Becomes smaller, crack 2
3 may occur. Incidentally, in FIG.
Reference numeral 4 indicates a Ni plating layer, reference numeral 25 indicates an Au plating layer, and reference numeral 26 indicates a core material portion of the wiring.

However, if the Ni plating layer in the lead portion 3L1 is completely removed, the lead portion 3L1 is subjected to heat treatment during the manufacturing process and mounting process of the semiconductor integrated circuit device.
Of the core material 3Lb of Cu is Au plating layer 3LmA
As a result of diffusion to the 1, 3 LmA2 side, there may be a problem that the bonding strength of the lead bonding portion and the bump bonding portion is deteriorated.

Therefore, in the twelfth embodiment, the Ni plating layers 3LmN1, 3Lm are formed on the surface of the lead joint portion of the lead portion 3L1 and the upper surface of the bump land portion 3L2.
The N2 is formed, but the Ni plating layers 3LmN1 and 3LmN2 are not formed on the other lead portions 3L1.

47 (a) schematically shows the cross-sectional state of the lead joint portion of the lead portion 3L1, and FIG. 47 (b) schematically shows the cross-sectional state of the bent portion of the lead portion 3L1.

As a result, it is possible to prevent the problem of cracking at the bent portion of the lead portion 3L1, and
During the heat treatment, Cu forming the core material portion 3Lb in the lead joint portion or the bump joint portion is Au plating layer 3LmA1, 3Lm.
It has a structure that can prevent it from spreading to A2.

As described above, in the twelfth embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

(1). Since the Ni plating layers 3LmN1 and 3LmN2 are formed only on the surface of the lead joint portion of the lead portion 3L1 and the upper surface of the bump land portion 3L2, there is a problem that cracks occur at the bent portion of the lead portion 3L1. In addition to being able to prevent it, Cu of the core material portion 3Lb at the lead bonding portion or the bump bonding portion during the heat treatment is Au plating layer 3L.
It becomes possible to prevent the diffusion to mA1 and 3LmA2.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned first to twelfth embodiments, and does not depart from the scope of the invention. It goes without saying that various changes can be made.

For example, in the seventh embodiment, the case where the present invention is applied to the structure in which the bonding pad is provided in the vicinity of the outer periphery of the semiconductor chip has been described. However, the present invention is not limited to this, and the bonding pad is provided at the center of the main surface of the semiconductor chip. It can also be applied to a structure in which is arranged.

In the eighth and ninth embodiments,
Cover the wiring of the flexible wiring board with a photosensitive insulating film,
The case where the structure in which the bump land portion of the wiring and the solder bump electrode are joined to each other through the opening formed in the photosensitive insulating film has been described, but the present invention is not limited to this and, for example, in the first embodiment described above. As described above, in the flexible wiring board, the wiring is formed on one surface of the tape, the solder bump electrode is provided on the other surface of the tape facing the tape, and the bump land portion of the wiring and the solder bump electrode are taped. The structure may be such that it is electrically connected through an opening formed in the. In this case, the semiconductor chip is arranged such that its main surface faces the direction in which it faces the wiring formation surface of the tape.

Further, in the above-mentioned first to twelfth embodiments, the case where the metal layer such as the gold plating layer and the Ni plating layer is formed by the electrolytic plating method or the electroless plating method has been described, but the present invention is not limited to this. However, it may be deposited on the core material portion of the wiring by, for example, a sputtering method or a vapor deposition method.

In the above description, the case where the invention made by the present inventor is mainly applied to the BGA type semiconductor integrated circuit device has been described, but the invention is not limited to this. For example, a solder bump electrode is provided on a wiring substrate. Instead, it can be applied to a so-called land grid array type semiconductor integrated circuit device in which the bump land portion is exposed.

Also, the case where the semiconductor integrated circuit device having the present invention is applied to a memory card has been described, but the present invention is not limited to this and can be applied to, for example, a mobile phone, a portable computer, a large computer, or the like.

[0285]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, in the lead portion of the wiring of the wiring board, the thickness of the Au layer at the joint surface with the external terminal of the semiconductor chip and the solder bump electrode in the land portion of the wiring of the wiring board By changing the thickness of the Au layer on the joint surface, both the joint surface of the lead portion and the joint surface of the land portion can be maintained even after high temperature standing.
Sufficient bonding strength can be obtained, and reliability in bonding can be improved. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved.

(2) According to the present invention, in each of the joint surface with the external terminal of the semiconductor chip in the lead portion of the wiring of the wiring board and the joint surface with the solder bump electrode in the land portion of the wiring of the wiring board, Since the minimum necessary Au layer can be formed without lowering the bonding strength of each of them, the amount of expensive Au used can be minimized,
It is possible to reduce the manufacturing cost of the semiconductor integrated circuit device. Therefore, a highly reliable semiconductor integrated circuit device can be manufactured at low cost.

(3). In the lead portion of the wiring of the wiring board, the joint surface with the external terminal of the semiconductor chip and the joint surface with the solder bump electrode in the land portion of the wiring of the wiring board Since the barrier metal layer is provided between the Au layer and the Au layer, it is possible to prevent the constituent atoms of the core material from diffusing into the Au layer during heat treatment such as a manufacturing process or a mounting process of the semiconductor integrated circuit device. It is possible to improve the reliability of the joining of the respective joining portions. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line II-II in FIG.

3 is a plan view of an essential part of the semiconductor integrated circuit device of FIG.

4 is a sectional view taken along line IV-IV in FIG.

FIG. 5 is a graph showing the relationship between the thickness of the gold layer formed on each joint surface of the wiring of the wiring board and the joint strength deterioration rate at each joint.

6 is a cross-sectional view of essential parts of a semiconductor integrated circuit device showing an example of a wiring plating structure on a wiring board of the semiconductor integrated circuit device of FIG.

7 is an explanatory view schematically showing a plating structure of a bonding surface of a lead portion and a bonding surface of a bump electrode in the wiring of the semiconductor integrated circuit device of FIG.

8 is a cross-sectional view of essential parts of a semiconductor integrated circuit device showing another example of the plating structure in the lead portion of the semiconductor integrated circuit device of FIG.

9 is an explanatory view schematically showing a plating structure of a bonding surface of a lead portion and a bonding surface of a bump electrode in the wiring of the semiconductor integrated circuit device of FIG.

10 is a cross-sectional view of essential parts of a semiconductor integrated circuit device showing another example of the plating structure in the lead portion of the semiconductor integrated circuit device of FIG.

11 is an explanatory diagram schematically showing a plating structure of a bonding surface of a lead portion and a bonding surface of a bump electrode in the wiring of the semiconductor integrated circuit device of FIG.

12 is a main-portion cross-sectional view of a semiconductor integrated circuit device showing another example of a plating structure in a lead portion of the semiconductor integrated circuit device of FIG. 1;

13 is an explanatory diagram schematically showing a plating structure of a bonding surface of a lead portion and a bonding surface of a bump electrode in the wiring of the semiconductor integrated circuit device of FIG.

14 is a cross-sectional view of essential parts of a semiconductor integrated circuit device showing another example of the plating structure in the lead portion of the semiconductor integrated circuit device of FIG.

15 is an explanatory diagram schematically showing a plating structure of a bonding surface of a lead portion and a bonding surface of a bump electrode in the wiring of the semiconductor integrated circuit device of FIG.

16 is an explanatory diagram for explaining a plating method for a wiring board of the semiconductor integrated circuit device of FIG.

17 is an explanatory diagram for explaining an assembling process of the semiconductor integrated circuit device of FIG. 1. FIG.

18 is a plan view of a mask used in a step of forming an elastic structure of the semiconductor integrated circuit device of FIG.

FIG. 19 is an explanatory diagram of a process of forming an elastic structure of the semiconductor integrated circuit device of FIG.

20 is an explanatory diagram of a lead connecting process of the semiconductor integrated circuit device of FIG. 1;

FIG. 21 is an explanatory diagram of the lead connecting step following FIG. 20 of the semiconductor integrated circuit device of FIG. 1;

22 is an explanatory diagram of the lead connecting step following FIG. 21 of the semiconductor integrated circuit device of FIG. 1. FIG.

23 is an explanatory diagram of an application example of the semiconductor integrated circuit device of FIG.

24 is an explanatory diagram of an application example of the semiconductor integrated circuit device of FIG.

FIG. 25 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention.

26 is a sectional view taken along line XXVI-XXVI of FIG. 25.

27 is an explanatory diagram for explaining a plating method for a wiring board of the semiconductor integrated circuit device of FIG. 25.

FIG. 28 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention.

29 is a sectional view taken along line XXIX-XXIX in FIG. 28.

FIG. 30 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 31 is a sectional view taken along line XXXI-XXXI of FIG. 30;

FIG. 32 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 33 is a sectional view taken along the line XXXIII-XXXIII in FIG. 32.

FIG. 34 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention.

35 is a cross-sectional view taken along the line XXXV-XXXV in FIG. 34.

FIG. 36 is a plan view of relevant parts of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 37 is a sectional view taken along line XXXVII-XXXVII in FIG. 36.

FIG. 38 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 39 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 40 is a plan view of a principal portion of a semiconductor integrated circuit device which is another embodiment of the present invention.

41 is a cross-sectional view taken along the line XXXXI-XXXXI of FIG. 40.

42 is a cross-sectional view of essential parts in the process of manufacturing the semiconductor integrated circuit device of FIG. 40.

43 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 40 during the manufacturing process following FIG. 42;

44 is a main-portion cross-sectional view of the semiconductor integrated circuit device of FIG. 40 in the manufacturing process following that of FIG. 43;

FIG. 45 is a main-portion cross-sectional view of a semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 46 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention.

47 (a) and 47 (b) are explanatory views schematically showing the cross-sectional state of the wiring in the flexible wiring of the semiconductor integrated circuit device of FIG. 46.

FIG. 48 is an explanatory diagram for explaining a crack in a lead portion of a flexible wiring board.

[Explanation of symbols]

 1 Semiconductor Chip 2, 2a, 2b Elastomer (Elastic Structure) 2A Elastomer Forming Material 3 Flexible Wiring Board (Wiring Board) 3T Tape (Substrate Base Material) 3L Wiring 3L1 Lead Part 3L2 Bump Land Part 3L3 Wiring for Plating Current 3LmA1 Gold plating layer (first gold layer) 3LmA2 Gold plating layer (second gold layer) 3LmN1 Nickel plating layer 3LmN2 Nickel plating layer 3LmP1 Palladium plating layer 3B Solder bump electrode 4 Passivation film 4a Passivation film 4a1 Opening part 4b 4b Opening part 5 Bonding Pad (External Terminal) 6a-6g Adhesive 7a-7d Sealing Resin 8m Metal Mask 8m1 Opening 9 Squeegee 10 Bonding Tool 11 Memory Card 12 Printed Wiring Board 13 CSP Type Semiconductor Integrated Circuit Device 14 QFP type semiconductor integrated circuit device 15 Terminal 16 Photosensitive insulating film (insulating film) 16a Opening 17 Protective member 17a Legs 18a, 18b Protective frame 19 Heat sink 20 Opening 21 Insulating film 22 Lead part 23 Crack 24 Nickel Plating layer 25 Gold plating layer 26 Core material M Shielding plate Z Insulating film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Setsuji Akiyama 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside the Semiconductor Business Division, Hitachi, Ltd. (72) Inventor Tadashi Miyazaki, Kamimizumoto-cho, Kodaira-shi, Tokyo 5-20-1 Incorporated company Hitachi, Ltd. Semiconductor Division (72) Inventor Masanori Shibamoto 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division (72) Inventor Tomoaki Shimoishi 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Within Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Ichiro Yasue 5-20-1 Mizukamihoncho, Kodaira-shi, Tokyo Hitachi Ltd. In-house Semiconductor Division (72) Inventor Kunihiko Nishi 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division (72) Asahi Nishimura 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Within the Semiconductor Division, Hitachi, Ltd. (72) Inventor Hideki Tanaka 5-20-1 Kamimizumoto-cho, Kodaira, Tokyo Hitachi Ltd. Semiconductor (72) Inventor Ryosuke Kimoto 5-22-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd. (72) Inventor Kunihiro Tsubozaki 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Business Division

Claims (41)

[Claims] A lead portion of a wiring formed on a wiring board is electrically connected to an external terminal on a main surface of a semiconductor chip;
A semiconductor integrated circuit device in which a land portion of a wiring formed on the wiring board is electrically connected to a solder bump electrode, and (a) is formed on a joint surface between the lead portion and the external terminal. The semiconductor integrated circuit device according to claim 1, wherein the thickness of the first gold layer is different from the thickness of the second gold layer formed on the joint surface between the land portion and the solder bump electrode. 2. The semiconductor integrated circuit device according to claim 1, wherein the thickness of the first gold layer is thicker than the thickness of the second gold layer. 3. The semiconductor integrated circuit device according to claim 1, wherein an elastic structure is provided between the main surface of the semiconductor chip and the wiring board, and the lead portion of the wiring board is bent. A semiconductor integrated circuit device, which is electrically connected to an external terminal on a main surface of a semiconductor chip. 4. The semiconductor integrated circuit device according to claim 1, wherein the first gold layer has a thickness of 0.8 μm or more, and the second gold layer has a thickness of 0.5 μm or less. A characteristic semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 4, wherein the thickness of the first gold layer is 0.8 μm to 3 μm,
A semiconductor integrated circuit device, wherein the thickness of the second gold layer is 0 to 0.5 μm. 6. The semiconductor integrated circuit device according to claim 1, wherein the core portion of the wiring, the first gold layer and the second gold layer are provided.
And a gold metal layer, the barrier metal layer for suppressing constituent atoms of the core material from moving to the first gold layer and the second gold layer is provided. . 7. The semiconductor integrated circuit device according to claim 6, wherein the barrier metal layer is a nickel layer. 8. The semiconductor integrated circuit device according to claim 1, wherein the core member of the wiring is made of a material containing copper as a main component, and the external terminal is made of a material containing aluminum as a main component. Integrated circuit device. 9. A lead portion of a wiring formed on a wiring board is electrically connected to an external terminal on a main surface of a semiconductor chip,
A semiconductor integrated circuit device in which a land portion of a wiring formed on the wiring board is electrically connected to a solder bump electrode, wherein (a) the lead portion comprises a nickel layer and a first gold layer in this order. A semiconductor integrated circuit device characterized by being joined to the external terminal via the metal layer formed in (1) and (b) being joined to the solder bump electrode via the nickel layer. 10. The semiconductor integrated circuit device according to claim 9, wherein an elastic structure is provided between the main surface of the semiconductor chip and the wiring board, and the lead portion of the wiring board is bent. A semiconductor integrated circuit device, which is electrically connected to an external terminal on a main surface of a semiconductor chip. 11. A lead portion of a wiring formed on a wiring board is electrically connected to an external terminal on a main surface of a semiconductor chip, and a land portion of the wiring formed on the wiring board serves as a solder bump electrode. A semiconductor integrated circuit device electrically connected, wherein (a) the lead portion is bonded to the external terminal via a first gold layer, and (b) the land portion is interposed via a palladium layer. A semiconductor integrated circuit device joined to the solder bump electrode. 12. The semiconductor integrated circuit device according to claim 11, wherein an elastic structure is provided between the main surface of the semiconductor chip and the wiring board, and the lead portion of the wiring board is bent. A semiconductor integrated circuit device, which is electrically connected to an external terminal on a main surface of a semiconductor chip. 13. A lead portion of a wiring formed on a wiring board is electrically connected to an external terminal on a main surface of a semiconductor chip, and a land portion of the wiring formed on the wiring board serves as a solder bump electrode. A semiconductor integrated circuit device electrically connected, wherein (a) the wiring board is provided so that a wiring formation surface thereof faces a main surface of the semiconductor chip, and the land portion is a substrate of the wiring board. A structure for electrically connecting to a solder bump electrode through an opening formed in a base material, and (b) a thickness of a first gold layer formed on a joint surface between the lead portion and the external terminal, (C) A semiconductor integrated circuit device characterized in that a thickness of a second gold layer formed on a bonding surface between the land portion and the solder bump electrode is changed. 14. The semiconductor integrated circuit device according to claim 13, wherein the thickness of the first gold layer is thicker than the thickness of the second gold layer. 15. The semiconductor integrated circuit device according to claim 13, wherein an elastic structure is provided between the main surface of the semiconductor chip and the wiring formation surface of the wiring board to bend the lead portion of the wiring board. A semiconductor integrated circuit device, wherein the semiconductor chip is electrically connected to an external terminal on the main surface of the semiconductor chip in a closed state. 16. The semiconductor integrated circuit device according to claim 13, wherein the external terminal is arranged at the center of the main surface of the semiconductor chip. 17. The semiconductor integrated circuit device according to claim 16, wherein the solder bump electrode is provided in a region inside an outer periphery of the semiconductor chip. 18. The semiconductor integrated circuit device according to claim 13, wherein the external terminal is arranged on an outer periphery of a semiconductor chip. 19. The semiconductor integrated circuit device according to claim 18, wherein the solder bump electrode is provided in a region outside an outer periphery of the semiconductor chip. 20. A wiring board is provided on a main surface of a semiconductor chip via an elastic structure, and external terminals are provided on the main surface of the semiconductor chip in a state in which lead portions of wiring formed on the wiring board are bent. A semiconductor integrated circuit device electrically connected to a solder bump electrode and a land portion of a wiring formed on the wiring board.
A structure in which the wiring substrate is provided such that its wiring forming surface faces the elastic structure, and the land portion is electrically connected to a solder bump electrode through an opening formed in a substrate of the wiring substrate. And (b) the semiconductor chip has a structure in which a plurality of the external terminals are arranged in the center of the main surface of the semiconductor chip, and (c) a first gold layer formed on a joint surface between the lead portion and the external terminal. And (d) the thickness of the second gold layer formed on the joint surface between the land portion and the solder bump electrode are changed. 21. The semiconductor integrated circuit device according to claim 20, wherein the solder bump electrode is provided in a region inside an outer periphery of the semiconductor chip. 22. A wiring board is provided on a main surface of a semiconductor chip via an elastic structure, and external terminals on the main surface of the semiconductor chip are provided in a state in which lead portions of wiring formed on the wiring board are bent. A semiconductor integrated circuit device electrically connected to a solder bump electrode and a land portion of a wiring formed on the wiring board.
A structure in which the wiring substrate is provided such that its wiring forming surface faces the elastic structure, and the land portion is electrically connected to a solder bump electrode through an opening formed in a substrate of the wiring substrate. (B) the semiconductor chip has a structure in which a plurality of the external terminals are arranged in the vicinity of the outer periphery thereof, and (c) the thickness of the first gold layer formed on the joint surface between the lead portion and the external terminal. And (d) the thickness of the second gold layer formed on the joint surface between the land portion and the solder bump electrode is changed. 23. The semiconductor integrated circuit device according to claim 22, wherein the solder bump electrode is provided in a region inside an outer periphery of the semiconductor chip. 24. The semiconductor integrated circuit device according to claim 22, wherein the solder bump electrodes are provided in both regions inside and outside the outer periphery of the semiconductor chip. 25. A wiring lead portion of a wiring board is electrically connected to an external terminal on a main surface of a semiconductor chip, and a land portion of the wiring board wiring is electrically connected to a solder bump electrode. A semiconductor integrated circuit device comprising:
(A) The wiring board is provided such that its flat surface faces the main surface of the semiconductor chip, an insulating film for covering the wiring is provided on the wiring formation surface of the wiring board, and the land portion is provided. Has a structure that is electrically connected to a solder bump electrode through an opening formed in the insulating film,
(B) the thickness of the first gold layer formed on the joint surface between the lead portion and the external terminal, and (c) the second gold layer formed on the joint surface between the land portion and the solder bump electrode. A semiconductor integrated circuit device characterized in that a layer thickness is changed. 26. The semiconductor integrated circuit device according to claim 25, wherein the thickness of the first gold layer is thicker than the thickness of the second gold layer. 27. The semiconductor integrated circuit device according to claim 25, wherein an elastic structure is provided between the main surface of the semiconductor chip and the wiring formation surface of the wiring board to bend the lead portion of the wiring board. A semiconductor integrated circuit device, wherein the semiconductor chip is electrically connected to an external terminal on the main surface of the semiconductor chip in a closed state. 28. The semiconductor integrated circuit device according to claim 25, wherein the external terminal is arranged at the center of the main surface of the semiconductor chip. 29. The semiconductor integrated circuit device according to claim 28, wherein the solder bump electrode is provided in a region inside an outer periphery of the semiconductor chip. 30. The semiconductor integrated circuit device according to claim 25, wherein the external terminal is arranged on an outer periphery of a semiconductor chip. 31. The semiconductor integrated circuit device according to claim 30, wherein the solder bump electrode is provided in a region outside an outer periphery of the semiconductor chip. 32. The semiconductor integrated circuit device according to claim 25, wherein a wiring for a reference voltage is formed on a surface of the wiring board facing the main surface of the semiconductor chip so as to cover substantially the entire surface. A semiconductor integrated circuit device characterized by being formed. 33. A wiring board is provided on a main surface of a semiconductor chip via an elastic structure, and lead terminals of wiring formed on the wiring board are bent, and external terminals are provided on the main surface of the semiconductor chip. A semiconductor integrated circuit device electrically connected to a solder bump electrode and a land portion of a wiring formed on the wiring board.
The wiring board is provided such that its flat surface faces the elastic structure, an insulating film for covering the wiring is provided on the wiring forming surface of the wiring board, and the land portion is formed on the insulating film. The semiconductor chip has a structure electrically connected to the solder bump electrode through a perforated opening. The thickness of the first gold layer formed on the joint surface with the external terminal and (d) the thickness of the second gold layer formed on the joint surface between the land portion and the solder bump electrode are changed. A semiconductor integrated circuit device characterized by the above. 34. The semiconductor integrated circuit device according to claim 33, wherein the solder bump electrode is provided in a region inside an outer periphery of the semiconductor chip. 35. A wiring board is provided on the main surface of a semiconductor chip via an elastic structure, and external terminals on the main surface of the semiconductor chip are provided in a state in which lead portions of wiring formed on the wiring board are bent. A semiconductor integrated circuit device electrically connected to a solder bump electrode and a land portion of a wiring formed on the wiring board.
The wiring board is provided so that its flat surface faces the elastic structure, an insulating film covering the wiring is provided on the wiring forming surface of the wiring board, and the land portion is formed on the insulating film. The semiconductor chip has a structure electrically connected to the solder bump electrode through a perforated opening, (b) the semiconductor chip has a structure in which a plurality of the external terminals are arranged in the vicinity of the outer periphery, and (c) the lead part and the The thickness of the first gold layer formed on the joint surface with the external terminal and (d) the thickness of the second gold layer formed on the joint surface between the land portion and the solder bump electrode are changed. A semiconductor integrated circuit device. 36. The semiconductor integrated circuit device according to claim 35, wherein the solder bump electrode is provided in a region inside an outer periphery of the semiconductor chip. 37. The semiconductor integrated circuit device according to claim 35, wherein the solder bump electrodes are provided in both regions inside and outside the outer periphery of the semiconductor chip. 38. A wiring board provided with a wiring having a lead portion for electrically connecting an external terminal of a semiconductor chip and a land portion for electrically connecting a solder bump electrode. A semiconductor integrated circuit device comprising:
(A) a thickness of a first gold layer formed on a joint surface between the lead portion and the external terminal, and (b) a second gold layer formed on a joint surface between the land portion and the solder bump electrode. A semiconductor integrated circuit device characterized in that a layer thickness is changed. 39. The semiconductor integrated circuit device according to claim 38, wherein the thickness of the first gold layer is thicker than the thickness of the second gold layer. 40. The semiconductor integrated circuit device according to claim 38, wherein an elastic structure is provided between the main surface of the semiconductor chip and the wiring board, and the lead portion of the wiring board is bent. A semiconductor integrated circuit device, which is electrically connected to an external terminal on a main surface of a semiconductor chip. 41. A lead portion of a wiring formed on a wiring board is electrically connected to an external terminal on a main surface of a semiconductor chip, and a land portion of the wiring formed on the wiring board serves as a solder bump electrode. A semiconductor integrated circuit device electrically connected, wherein (a) a first gold layer is provided on a joint surface between the lead portion and the external terminal, and (b) the land portion and the solder bump electrode. The second gold layer is provided on the bonding surface of
(C) A semiconductor integrated circuit device characterized in that the thickness of the first gold layer and the thickness of the second gold layer are shared in the range of 0.6 μm to 1.0 μm.