JP2005322948A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability for joints between leads of a wiring board and external terminals of a semiconductor chip and between bump lands and bump electrodes in a semiconductor integrated circuit device which has a package structure, in which the leads of the wiring board having the solder bump electrodes are electrically connected to the external terminals of the semiconductor chip. <P>SOLUTION: The BGA semiconductor integrated circuit device is formed, by placing the flexible wiring board 3 on the main surface of the semiconductor chip 1 via an elastomer 2. In the semiconductor integrated circuit device, the leads 3L1 of the wiring board 3 are jointed to bonding pads 5 of the semiconductor chip 1 via metal layers consisting of a nickel layer and a first metal layer, formed in this order, and the bump lands 3L2 of the wiring board 3 are jointed to the solder bump electrodes 3B via the nickel layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device technology, and particularly to a technology effective when applied to a semiconductor integrated circuit device having a BGA (Ball Grid Array) package structure.

  Along with improvements in the functions and performance of electronic devices, technological developments are underway to reduce the appearance and size of the device to a small size and weight. This is largely due to the rapid increase in portable electronic devices such as portable telephones and portable computers in recent years.

  In addition, the importance of man-machine interface roles in electronic devices operated by individuals is increasing, and the ease of handling and operability of electronic devices are becoming more important. Furthermore, the need to process a large amount of information including complex images with a small electronic device at a high speed has been rapidly increasing. These trends are likely to become stronger with the advent of the full-fledged multimedia era.

  Under such circumstances, the improvement in the integration degree of elements formed on the semiconductor chip is not known, but the increase in the size of the semiconductor chip and the increase in the number of electrodes has progressed, and the package that accommodates the semiconductor chip has also increased in size. It has become to.

  On the other hand, in order to reduce the package size, measures such as narrowing the lead pitch have been taken, but with this, it has become difficult to mount the package rapidly.

  Therefore, a BGA type package structure in which a large number of external electrodes can be drawn out from a small package and can be mounted relatively easily is rapidly being used.

  In this structure, the external electrode is not drawn from the side of the package like QFP (Quad Flat Package), but is drawn from the mounting surface of the package like PGA (Pin Grid Array). Although the pitch of is smaller than that of PGA, the external electrode can be pulled out with a margin more than QFP or the like, so that the mounting is easy.

  There are various types of BGA type packages having different structures and materials, and so-called tape BGA (hereinafter referred to as TBGA) using an insulating tape for the wiring board portion is one of them. This TBGA type package structure has a feature that a pattern can be formed finer and thinner than other BGA type package structures.

  For this reason, a structure in which this TBGA type package structure is applied to a so-called CSP (Chip Size Package) structure of a BGA package structure having substantially the same external dimensions as a semiconductor chip has been developed. As for the semiconductor integrated circuit device having such a BGA type package structure, for example, “Nikkei Microdevices” P98 to P102 (Non-patent Document 1) issued on May 1, 1994, Nikkei BP, February 1995 “Nikkei Microdevices” issued on the 1st, P96 to P97 (Non-patent Document 2) and “Electrical Materials” P22 to P28 (Non-patent Document 3) issued on April 1, 1995, etc. Here, a CSP type BGA package structure is described.

  That is, in these documents, flexible wiring in which bump electrodes are arranged in an area array is provided via an elastomer on the main surface of a semiconductor chip, and the leads of the wiring pattern formed on the flexible wiring substrate are bent. A package structure connected to bonding pads on the main surface of a semiconductor chip is disclosed. The wiring pattern of this flexible wiring board is formed of gold (Au) plated copper (Cu) foil, and the tip portion thereof is etched by Cu to form an Au lead.

  For the package structure of the TBGA type, see, for example, the Japan Electronic Materials Technology Association, issued in July 1995, “The Japan Electronics Material Technology Association Bulletin, Whereabouts of TBGA” JEMS. VOL. 27, P14 to P19 (Non-Patent Document 4).

  Here, a TAB tape formed in a planar frame shape is disposed on the outer periphery of the LSI chip so as to surround the LSI chip, a TAB lead extending flat from the TAB tape, and a main surface of the LSI chip. A typical structure of a TBGA is described in which a bonding pad is electrically connected via a solder terminal or the like, and a spherical solder terminal connected to a pad of a mounting board is provided on a frame surface of a TAB tape. Yes.

The back surface of this LSI chip is joined to a heat sink. A fixing plate formed in a planar frame shape is interposed between the heat radiating plate and the TAB tape so as to surround the side surface of the LSI chip. The TAB tape is made of copper (Cu) / polyimide / Cu.
Nikkei Business Publications, May 1, 1994 "Nikkei Microdevice" P98-P102 Nikkei Business Publications, Nikkei Microdevice issued on February 1, 1995, P96-P97 Industrial Research Co., Ltd., “Electronic Materials” issued on April 1, 1995, P22 to P28 Japan Electronic Materials Technology Association, published in July 1995, “The Japan Electronics Materials Technology Association Bulletin, Whereabouts of TBGA” JEMS. VOL. 27, P14-P19

  However, the present inventors have found that the above-described BGA package technology has the following problems.

  That is, in the above-described technology for forming the leads of the flexible wiring board with Au, a large amount of expensive gold is required, and there is a problem that the manufacturing cost of the semiconductor integrated circuit device increases.

  The inventor has also studied a semiconductor integrated circuit device having this type of package structure. The following is not a known technique, but is a technique examined by the present inventor, and the outline thereof is as follows. That is, the technique examined by the present inventors is that the lead core material of the flexible wiring board having the above-described package structure is made of Cu, and Au plating layers having the same thickness are formed on the upper and lower surfaces of the lead. It is. However, in the technique studied by the present inventor in which the core material of the wiring of the flexible wiring board is made of Cu and the gold plating layer having the same film thickness is provided on both surfaces of the lead of the wiring, the lead and the external terminal of the semiconductor chip It is not possible to optimize the bonding state of each of the bonding portion between the solder bump electrode and the wiring portion (bump land portion) to which the solder bump electrode is bonded. There is a problem that reliability cannot be obtained.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device having a package structure in which a lead portion of a wiring board on which solder bump electrodes are formed is electrically connected to an external terminal of a semiconductor chip. It is an object of the present invention to provide a technique capable of improving the reliability of the bonding of the bonding portion between the bump land portion and the bump land portion and the bump electrode.

  Another object of the present invention is to reduce the manufacturing cost of a semiconductor integrated circuit device having a package structure in which lead portions of a wiring board on which solder bump electrodes are formed are electrically connected to external terminals of a semiconductor chip. It is to provide a technique that can be reduced.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

That is, according to the present invention, the lead portion of the wiring formed on the wiring substrate is electrically connected to the external terminal on the main surface of the semiconductor chip, and the land portion of the wiring formed on the wiring substrate is connected to the solder bump electrode. A semiconductor integrated circuit device electrically connected to
(A) While joining the lead portion to the external terminal through a metal layer formed in the order of a nickel layer and a first gold layer,
(B) The land portion is bonded to the solder bump electrode through a nickel layer.

In addition, the present invention electrically connects a lead portion of a wiring formed on a wiring board to an external terminal on a main surface of a semiconductor chip, and connects a land portion of the wiring formed on the wiring board to a solder bump electrode. A semiconductor integrated circuit device electrically connected to
(A) While joining the lead part to the external terminal through a first gold layer,
(B) The land portion is joined to the solder bump electrode through a palladium layer.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, in a semiconductor integrated circuit device having a package structure in which a lead portion of a wiring board on which a solder bump electrode is formed is electrically connected to an external terminal of a semiconductor chip, a joint portion and a bump between the lead portion and the external terminal It is possible to improve the reliability of bonding at both the land portion and the bonding portion between the bump electrodes.

  Further, in the semiconductor integrated circuit device having a package structure in which the lead portion of the wiring board on which the solder bump electrodes are formed is electrically connected to the external terminal of the semiconductor chip, the manufacturing cost can be reduced.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail below with reference to the drawings. To do).

(Embodiment 1)
1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 1, and FIG. 3 is a plan view of the main part of the semiconductor integrated circuit device in FIG. 4 is a cross-sectional view taken along the line IV-IV in FIG. 3, and FIG. 5 is a graph showing the relationship between the thickness of the gold layer formed on each joint surface of the wiring of the wiring board and the joint strength deterioration rate at each joint. 6 to 15 are explanatory views for explaining an example of the plating structure in the lead portion of the semiconductor integrated circuit device of FIG. 1, and FIG. 16 is for explaining the plating method for the wiring substrate of the semiconductor integrated circuit device of FIG. FIG. 17 is an explanatory diagram for explaining the assembly process of the semiconductor integrated circuit device of FIG. 1, FIG. 18 is a plan view of a mask used in the process of forming the elastic structure of the semiconductor integrated circuit device of FIG. FIG. 2 is an explanatory view of the elastic structure of the semiconductor integrated circuit device of FIG. 0 Figure 22 is an explanatory view of a connecting process of the lead of a semiconductor integrated circuit device of FIG. 1, 23 and 24 is an explanatory view of an application example of the semiconductor integrated circuit device of FIG.

  First, the structure of the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

  The semiconductor integrated circuit device according to the first embodiment is, for example, a CSP (Chip Size Package) type semiconductor integrated circuit device, which is provided on a semiconductor chip 1 and an elastomer (elastic structure) 2 on its main surface. And a flexible wiring board (wiring board) 3.

  The semiconductor chip 1 is made of a small piece of, for example, a planar rectangular silicon (Si) single crystal, and on its main surface, for example, a logic circuit such as a microprocessor, SRAM (Static Random Access Memory), DRAM (Dynamic A predetermined integrated circuit such as a memory circuit such as a random access memory is formed.

  A passivation film 4 is formed on the uppermost layer of the main surface of the semiconductor chip 1. The passivation film 4 is an insulating film for protecting the above-described integrated circuit configuration elements, wirings, and the like, and is made of, for example, a passivation film 4 a made of an inorganic material and an organic material in order from the main surface side of the semiconductor chip 1. A passivation film 4b is deposited and formed.

The passivation film 4a is configured, for example, by depositing silicon dioxide (SiO ₂ ) or silicon nitride thereon. The passivation film 4b is made of, for example, a polyimide resin, and the thickness thereof is, for example, about 2 to 10 μm.

  In the center of the main surface of the semiconductor chip 1, a plurality of rectangular bonding pads (external terminals) 5 are arranged along a straight line. The bonding pad 5 is a lead electrode for leading out the electrode of the integrated circuit to the outside of the semiconductor chip 1 and is made of, for example, aluminum (Al) or an Al—Si—Cu alloy.

  The upper surface of the bonding pad 5 is exposed through the openings 4a1, 4b1 drilled in the passivation films 4a, 4b. The opening 4a1 in the lower passivation film 4a is formed with such a size that the upper surface of each bonding pad 5 is exposed (see FIGS. 3 and 4). In FIG. 3, the passivation films 4a and 4b are hatched to make the drawing easy to see.

  Further, the opening 4b1 in the upper passivation film 4b is formed to be larger than the individual bonding pads 5, and is an elongated opening region extending along the arrangement direction of the plurality of bonding pads 5.

  In FIG. 4, the symbol Z indicates an interlayer insulating film, and a plurality of wiring layers and elements are formed in this lower layer (in the direction toward the semiconductor substrate of the semiconductor chip 1).

  The elastomer 2 is printed on the connection part (a solder bump electrode described later) between the CSP type semiconductor integrated circuit device and a printed wiring board on which the CSP type semiconductor integrated circuit device is mounted in a process involving heat such as a temperature characteristic test. It has a function of absorbing stress applied due to a difference in thermal expansion coefficient from the wiring board.

  The elastomer 2 is disposed on both sides (left and right in FIG. 1 and the like) of the long side in the arrangement region of the bonding pads 5 in the center of the main surface of the semiconductor chip 1. Each of the left and right elastomers 2 is formed in a flat plate shape extending along the longitudinal direction of the semiconductor chip 1 and is made of an elastic material such as a silicone resin having a thickness of about 100 μm to 200 μm, preferably about 150 μm. It is configured.

  The left and right elastomers 2 are bonded to the semiconductor chip 1 by an adhesive 6a. The adhesive material 6a is made of, for example, a silicone-based resin, and the thickness thereof is set to, for example, about 10 μm to 30 μm, preferably about 20 μm.

  The flexible wiring board 3 is a member for electrically connecting the integrated circuit of the semiconductor chip 1 and the wiring of the printed wiring board for mounting, and the pattern formation surface of the wiring 3L of the flexible wiring board 3 is formed on the elastomer 2. It is bonded to the elastomer 2 in a state of being directed to the side, and is incorporated in the semiconductor integrated circuit device.

  A tape (substrate substrate) 3T constituting the flexible wiring board 3 is made of, for example, polyimide resin, and a rectangular opening 3T1 extending in the longitudinal direction of the semiconductor chip 1 is perforated at the center thereof. The arrangement area of the bonding pads 5 is exposed from the opening 3T1. The thickness of the tape 3T is set to, for example, about 50 μm to 125 μm, preferably about 50 μm.

  The wiring 3L is patterned on the tape 3T. The wiring 3L is bonded to the tape 3T with an adhesive 6b. The adhesive 6b is made of, for example, an epoxy resin, and the thickness thereof is set to, for example, about 10 μm to 20 μm, preferably about 10 μm.

  The core portion of the wiring 3L (the main constituent material portion of the wiring excluding the plating layer) is made of, for example, Cu or Cu alloy, and the thickness thereof is set to, for example, about 12 μm to 30 μm, and preferably about 18 μm, for example. Has been.

  One end of the wiring 3L, that is, the lead portion 3L1 is protruded from both long sides of the central opening 3T1 of the tape 3T, and the respective lead portions 3L1 protruding from both long sides engage with each other. The semiconductor chip 1 extends toward the center.

  The lead portion 3L1 is bent to the main surface side of the semiconductor chip 1, and is electrically connected to the bonding pad 5 on the main surface of the semiconductor chip 1 with the lead portion 3L1 bent in, for example, a substantially S-shaped cross section. (See FIG. 2 and FIG. 4). Note that a plating layer is not shown in the lead portion 3L1 of FIG.

  The bending of the lead portion 3L1 has a function of absorbing stress generated in the lead portion 3L1 due to a difference in thermal expansion coefficient between the semiconductor chip 1 and the printed wiring board. That is, the lead portion 3L1 has a function as an elastic body due to its bending.

  Since the width of the core portion of the lead portion 3L1 varies depending on the type of product and the like, it cannot be generally specified, but is about 38 μm, for example. The surface of the core portion in the lead portion 3L1 is plated. This plating structure will be described in detail later.

  A bump land 3L2 is formed in the middle of the wiring 3L. The bump land 3L2 is electrically connected to the solder bump electrode 3B through an opening 3T2 drilled in the tape 3T. In the bump land portion 3L2, the bonding surface with the solder bump electrode 3B is plated. This plating structure will be described in detail later.

  Further, the portion of the wiring 3L extending from the bump land portion 3L2 to the outer peripheral side of the flexible wiring board 3 is a wiring 3L3 for supplying a plating current. The plating current supply wiring 3L3 is connected to a plating current supply terminal of a plating apparatus when plating the lead portion 3L1, bump land portion 3L2, and the like, and is placed in the lead portion 3L1, bump land portion 3L2, etc. This is a wiring path for supplying a constant amount of current.

  A plurality of solder bump electrodes 3B are regularly arranged on both sides (left and right in FIG. 1) of the opening 3T1 on the main surface of the tape 3T. However, the solder bump electrode 3 </ b> B is disposed in an inner region than the outer periphery of the semiconductor chip 1.

  Each solder bump electrode 3B is made of, for example, a lead (Pb) -tin (Sn) alloy formed in a substantially spherical shape, and the diameter of the solder bump electrode 3B varies depending on the type of the product. In the first embodiment, for example, about 5 mm to 0.7 mm is set to about 0.6 mm.

  In such a CSP type semiconductor integrated circuit device, the side surface of the semiconductor chip 1 and the side surface of the elastomer 2 are covered with a sealing resin 7a (see FIG. 2). However, the sealing resin 7a may be omitted.

  Further, a sealing resin is also provided in a groove exposed from the opening 3T1 of the flexible wiring board 3, that is, a groove formed by the main surface of the semiconductor chip 1 and the inner wall surfaces facing each other in the two elastomers 2 thereon. 7b is filled, thereby covering the bonding pad 5, the lead portion 3L1, and the like.

  The sealing resins 7a and 7b sufficiently protect the CSP type semiconductor integrated circuit device from external impacts, moisture, and the like, and it is possible to improve the reliability of the semiconductor integrated circuit device.

  Next, a description will be given of a specific example of the structure after describing the result of the study by the inventor regarding the plating structure of the wiring 3L of the flexible wiring board 3 described above.

  First, the inventor determines the strength of the joint portion (hereinafter referred to as a lead joint portion) between the lead portion 3L1 of the wiring 3L and the bonding pad 5 and the joint portion between the bump land portion 3L2 of the wiring 3L and the solder bump electrode 3B (hereinafter referred to as the lead joint portion). The strength of the bump joints was examined.

  As a result, it has been found that the strength of each joint varies depending on the thickness of the gold (Au) plating applied to the lead portion 3L1 and the bump land portion 3L2. The result is shown in FIG.

  FIG. 5 shows the bonding strength of each of the lead bonding portion and the bump bonding portion after the high temperature storage (aging) test of, for example, 125 ° C. and 48 hours is performed on the semiconductor integrated circuit device of the first embodiment. It is the graph which showed the deterioration rate.

  The horizontal axis of FIG. 5 shows the film thickness of the Au plating layer coated on the wiring 3L, and the vertical axis shows the deterioration rate of the bonding strength (the lower the bonding is, the lower the bonding deterioration is).

  The curve drawn with a solid line indicates the deterioration rate of the bonding strength of the lead bonding portion (hereinafter referred to as lead bonding strength), and the curve drawn with a broken line indicates the bonding strength of the bump bonding portion (hereinafter referred to as bump bonding strength). Degradation rate).

  In the deterioration rate curve (solid line) of the lead bonding strength, the deterioration rate decreases as the Au plating layer on the bonding surface on the bonding pad 5 side (hereinafter referred to as the pad-side bonding surface) increases in the lead portion 3L1. That is, it can be seen that it is better to thicken the Au plating layer on the pad side bonding surface of the lead portion 3L1.

  Here, the reason why the lead bonding strength is lowered when the Au plating layer is thin is left at a high temperature.

  When the bonding pad 5 made of Al or the like and the lead portion 3L1 are brought into contact with each other under predetermined conditions, for example, a load of 30 to 60 g, a temperature of 200 to 230 ° C., and an ultrasonic wave of 0.15 to 0.30 W, Au plating on the back surface of the lead portion 3L1 The Au atoms in the layers are interdiffused to bond the two.

  In this state, when the substrate is left at a high temperature, for example, at a temperature of 125 ° C. for 48 hours, an intermetallic compound of Au and Al is generated at the bonding interface of the lead bonding portion. The composition of this intermetallic compound has the property that the composition ratio of Au and Al varies depending on the amount of Au in the vicinity of the bonding interface.

That is, when Au is abundant at the joint interface of the lead joint, an Au ₅ Al ₂ alloy having high mechanical strength is selectively generated. On the other hand, as the amount of Au decreases, the mechanical strength slightly increases. When a small Au ₂ Al alloy is produced and the amount of Au is further reduced, an AuAl ₂ alloy having a smaller mechanical strength is selectively produced.

  As a result, the thinner the Au plating layer of the lead portion 3L1, the lower the lead bonding strength when left at high temperatures.

  The Au plating layer also has a function of mitigating impact caused by a bonding tool during lead bonding. Therefore, if the thickness of the Au plating layer is made too thin, the impact of bonding is applied to the lead bonding surface through relatively hard Ni, Cu, etc., so the main surface of the semiconductor chip 1 under the bonding pad 5 Will be damaged. In this case, the lead bonding strength is significantly reduced.

  On the other hand, in the deterioration rate curve of the bump bonding strength (broken line), the deterioration rate increases as the Au plating layer on the solder bump electrode 3B side bonding surface (hereinafter referred to as the solder ball side bonding surface) becomes thicker in the bump land portion 3L2. ing. That is, it can be seen that it is better to make the Au plating layer thinner on the solder ball side joint surface.

  Here, the reason why the bump bonding strength decreases when left at high temperature when the gold plating layer is thick will be described.

  Under high temperature conditions at the time of bump bonding, for example, at a maximum (Max) of 235 ° C. to 200 ° C. for 45 seconds or more, Au atoms at the bonding interface forming the gold plating layer are, for example, 63% tin ( Sn) -37% almost uniformly diffused in lead (Pb).

When the concentration of Au diffused in the solder ball exceeds a predetermined concentration and left at a high temperature, for example, at a temperature of 125 ° C. for 48 hours, the Au atoms diffused in the solder ball are temporarily dispersed in the solder ball. It selectively agglomerates at the bonding interface and bonds with Sn atoms in the solder balls to mainly precipitate AuSn ₄ compounds.

The deposited AuSn ₄ has a mechanically brittle property, and as a result, the bonding strength of the solder ball is lowered. Further, the solder bump electrode 3B may be peeled off.

  On the other hand, when the above-mentioned high temperature standing treatment is performed in a state where the Au plating layer is thin and the concentration of Au diffused in the solder ball is lower than a predetermined concentration, Au and Sn coexist. Since it has the property of not forming a compound, it is possible to prevent a mechanically brittle layer from being formed at the bonding interface of the solder balls, and the bonding strength of the solder bump electrode 3B is not reduced.

  Here, when the deterioration rate of both the lead bonding strength and the bump bonding strength is desired to be, for example, up to 30%, the thickness of the Au plating layer on each bonding surface of the lead bonding portion and the bump bonding portion is set to, for example, It turns out that it is good to set it like this.

  First, the thickness of the Au plating layer on the pad side bonding surface of the lead bonding portion is practically suitable, for example, 0.8 μm or more, preferably about 0.8 μm to 3.0 μm. Here, the thickness of the Au plating layer is preferably set to 0.8 μm to 3.0 μm for the following reason, for example.

  That is, if the thickness of the Au plating layer is thinner than 0.8 μm, the deterioration rate of the bonding strength exceeds 30% as can be seen from FIG. Further, if the thickness of the Au plating layer is less than 0.8 μm, the bonding pad 5 and the underlying semiconductor chip 1 may be damaged by a pressing force by a bonding tool at the time of lead bonding described later.

  Further, if the thickness of the Au plating is thicker than 3.0 μm, it is preferable from the viewpoint of bonding strength, but expensive Au is excessively used, which is inappropriate from the viewpoint of manufacturing cost.

  On the other hand, the thickness of the Au plating layer on the solder ball side joint surface of the bump joint is, for example, 0.5 μm or less, and preferably about 0.05 μm to 0.5 μm. Here, the reason why the thickness of the Au plating layer is preferably set to 0.05 μm to 0.5 μm is, for example, for the following reason.

  That is, the lower limit of the thickness of the Au plating layer is not set to zero (0). If the Au plating is not applied at all, it is easy to oxidize and corrode, and the solder of the solder bump electrode 3B. This is because it has been considered that problems such as lowering of wettability occur. Moreover, if the thickness of the Au plating layer is greater than 0.5 μm, the deterioration rate of the bonding strength exceeds 30%.

  By setting in this way, the bonding strength deterioration rate can be suppressed to be lower than 30% in both the lead bonding portion and the bump bonding portion, so that a highly reliable semiconductor integrated circuit device can be provided.

  In addition, since the minimum necessary Au plating layer can be formed in each of the lead bonding portion and the bump bonding portion, the amount of expensive Au used can be minimized, and the manufacturing cost of the semiconductor integrated circuit device can be reduced. It is possible to lower.

  However, the thickness of the Au plating layer described here is for a product that requires that the joint strength deterioration rate of both the lead joint portion and the bump joint portion not exceed 30%, and is limited to this. However, the range of the thickness of the Au plating layer can be variously changed if the required deterioration rate of the bonding strength is changed.

  For example, depending on the product, the bonding strength on the bump bonding portion side may not be required as much as the lead bonding portion having a smaller bonding area because the bonding area of the bump land portion 3L2 is large.

  In this case, the deterioration rate of the bonding strength may not exceed 30% at the lead bonding portion, and the deterioration rate of the bonding strength may not exceed 35% at the bump bonding portion. In this case, the thickness of the Au plating layer on the pad side bonding surface of the lead bonding portion is, for example, about 0.8 μm or more, and the thickness of the Au plating layer on the solder ball side bonding surface in bump bonding is, for example, 0. The thickness is about 7 μm or less.

  Further, when the bonding strength deterioration rate required for the lead bonding portion and the bump bonding portion is 50% or less, the Au plating layer on the pad side bonding surface and the bump side bonding surface is, for example, 0.6 μm to 1.0 μm. You may set to the thickness shared in the range. That is, in this case, the thickness of the Au plating layer on the pad side bonding surface and the bump side bonding surface may be the same or may be changed. However, in this case, even if the thickness of the Au plating layer on the pad side bonding surface is equal to the thickness of the Au plating layer on the bump side bonding surface, the required bonding strength is not limited to one of the bonding portions, but the lead bonding portion. In addition, it is possible to obtain sufficient at both joints of bump joints.

  Next, a specific example of the plating structure applied to the wiring 3L of the flexible wiring board 3 will be described with reference to FIGS. Here, a case where the thickness of the Au plating layer is set so that the deterioration rate of the bonding strength of both the lead bonding portion and the bump bonding portion does not exceed 30% will be described.

  6 to 15, reference numeral 3Lb indicates the core part of the wiring 3L. FIG. 7, FIG. 9, FIG. 11, FIG. 13 and FIG. 15 are diagrams schematically showing the state of the plated layers on both the pad side joint surface and the solder ball side joint surface of the wiring 3L. is there.

  First, as shown in FIGS. 6 and 7, only the Au plating layers 3LmA1 and 3LmA2 are formed on the surface of the lead portion 3L1 and the solder ball side joint surface of the bump land portion 3L2.

  For the reason described above, a gold plating layer (first gold layer) 3LmA1 having a thickness of 0.8 μm to 3.0 μm is formed on the core portion 3Lb of the pad side bonding surface of the lead portion 3L1 (the back surface of the lead portion 3L1). It is covered. In the first embodiment, the thickness of the Au plating layer 3LmA1 is set to about 1.5 μm, for example.

  In addition, a gold plating layer (second gold layer) 3LmA2 having a thickness of 0.5 μm or less is formed on the core portion 3Lb on the main surface side of the lead portion 3L1 and the solder ball side bonding surface of the bump land portion 3L2 for the reason described above. It is covered. In the first embodiment, the thickness of the Au plating layer 3LmA2 is set to about 0.3 μm, for example.

  Second, as shown in FIGS. 8 and 9, the surface of the lead portion 3L1 and the solder ball side joint surface of the bump land portion 3L2 are Au plated via nickel (Ni) plating layers (barrier metal layers) 3LmN1, 3LmN2. In this example, the layers 3LmA1 and 3LmA2 are formed.

  The reason why the Ni plating layer is provided is that Cu constituting the core portion 3Lb of the wiring 3L diffuses into the Au plating layers 3LmA1 and 3LmA2 during the predetermined heat treatment of the semiconductor integrated circuit device, and leads bonding and bump bonding. It is for suppressing deteriorating the joint strength of a part.

  The core part 3Lb of the pad side joint surface of the lead part 3L1 is covered with an Au plating layer 3LmA1 via a Ni plating layer 3LmN1. For example, the thickness of the gold plating layer 3LmA1 is set to 0.8 μm to 3.0 μm, and in the first embodiment, the thickness is set to about 1.5 μm, for example.

  The core portion 3Lb on the main surface side of the lead portion 3L1 and the solder ball side joint surface of the bump land portion 3L2 is covered with an Au plating layer 3LmA2 via a Ni plating layer 3LmN2. The thickness of the gold plating layer 3LmA2 is set to 0.5 μm or less for the above reason, and is set to, for example, about 0.3 μm in the first embodiment.

  The thicknesses of the Ni plating layers 3LmN1 and 3LmN2 are both set to, for example, about 0 to 2.0 μm, and preferably about 0.5 μm. However, the thicknesses of the Ni plating layers 3LmN1, 3LmN2 do not have to be equal.

  Further, the Ni plating layer on the pad side bonding surface (back surface) of the lead bonding portion may be eliminated. Thus, when the lead portion 3L1 is bonded to the bonding pad 5, it is possible to avoid the problem that the semiconductor chip 1 is damaged due to the presence of the hard Ni plating layer in the lead portion 3L1.

  Third, as shown in FIGS. 10 and 11, an Au plating layer 3LmA1 is provided on the pad side bonding surface (back surface) of the lead portion 3L1 via the Ni plating layer 3LmN1, and the solder ball side bonding surface of the bump land portion 3L2 is provided. Is an example in which only the Ni plating layer 3LmN2 is provided.

  The reason why the Ni plating layer 3LmN2 is provided on the solder ball side bonding surface of the bump land portion 3L2 is that the core material portion 3Lb made of Cu is left exposed without providing the Au plating layer on the solder ball side bonding surface of the bump land 3L2. In order to prevent such problems, it tends to oxidize, corrode easily, and solder wettability decreases.

  The core part 3Lb on the pad side bonding surface (back surface) of the lead part 3L1 is covered with an Au plating layer 3LmA1 via a Ni plating layer 3LmN1. For example, the thickness of the gold plating layer 3LmA1 is set to 0.8 μm to 3.0 μm, and in the first embodiment, it is set to about 1.5 μm, for example.

  Further, only the Ni plating layer 3LmN2 is coated on the core portion 3Lb of the main surface side of the lead portion 3L1 and the solder ball side joining surface (main surface) of the bump land portion 3L2.

  The thicknesses of the Ni plating layers 3LmN1 and 3LmN2 are both set to, for example, about 0 to 2.0 μm, preferably about 0.5 μm. However, the thicknesses of the Ni plating layers 3LmN1, 3LmN2 do not have to be equal.

  Also in this case, the Ni plating layer on the pad side bonding surface of the lead bonding portion may be eliminated. Thus, when the lead portion 3L1 is bonded to the bonding pad 5, it is possible to avoid the problem that the semiconductor chip 1 is damaged due to the presence of the hard Ni plating layer in the lead portion 3L1.

  Fourth, as shown in FIGS. 12 and 13, an Au plating layer 3LmA1 is provided on the pad side bonding surface (back surface) of the lead portion 3L1, and a palladium (Pd) plating layer is provided on the solder ball side bonding surface of the bump land portion 3L2. In this example, 3LmP1 is provided.

  The reason why the Pd plating layer is provided on the upper surface of the bump land 3L2 is that if the core material portion 3Lb made of Cu is left exposed without providing the Au plating layer on the upper surface of the bump land 3L2, it is easy to oxidize and corrode easily. This is to prevent problems such as a decrease in solder wettability.

  An Au plating layer 3LmA1 is coated on the core portion 3Lb on the pad side bonding surface (back surface) side of the lead portion 3L1. For example, the thickness of the gold plating layer 3LmA1 is set to 0.8 μm to 3.0 μm, and in the first embodiment, it is set to about 1.5 μm, for example.

  The core part 3Lb on the main surface side of the lead part 3L1 and the solder ball side joining surface of the bump land part 3L2 is covered with a Pd plating layer 3LmP1. The thickness of the Pd plating layer 3LmP1 is set to, for example, about 0.05 μm to 1.0 μm, and preferably about 0.1 μm to 0.2 μm.

  Fifth, as shown in FIGS. 14 and 15, an Au plating layer 3LmA1 is provided on the pad side bonding surface (back surface) of the lead portion 3L1 via the Ni plating layer 3LmN1, and the solder ball side bonding surface of the bump land portion 3L2 is provided. This is an example in which a Pd plating layer 3LmP1 is provided through a Ni plating layer 3LmN2.

  The reason for providing the Ni plating layer is that the Cu constituting the core portion 3Lb of the wiring 3L diffuses into the Au plating layer 3LmA1 and the Pd plating layer 3LmP1 during the predetermined heat treatment of the semiconductor integrated circuit device. This is also for suppressing the deterioration of the bonding strength of the bump bonding portion.

  The core part 3Lb on the pad side bonding surface (back face) of the lead part 3L1 is covered with an Au plating layer 3LmA1 via a Ni plating layer 3LmN1. For example, the thickness of the gold plating layer 3LmA1 is set to 0.8 μm to 3.0 μm, and in the first embodiment, it is set to about 1.5 μm, for example.

  The core portion 3Lb on the main surface side of the lead portion 3L1 and the solder ball side joint surface of the bump land portion 3L2 is covered with a Pd plating layer 3LmP1 via a Ni plating layer 3LmN2.

  The thickness of the Pd plating layer 3LmP2 is set to, for example, about 0.05 μm to 1.0 μm, preferably, for example, about 0.1 μm to 0.2 μm. The thicknesses of the Ni plating layers 3LmN1 and 3LmN2 are both set to, for example, about 0 to 2.0 μm, and preferably about 0.5 μm. However, the thicknesses of the Ni plating layers 3LmN1, 3LmN2 do not have to be equal.

  Also in this case, the Ni plating layer on the pad side bonding surface of the lead bonding portion may be eliminated. Thus, when the lead portion 3L1 is bonded to the bonding pad 5, it is possible to avoid the problem that the semiconductor chip 1 is damaged due to the presence of the hard Ni plating layer in the lead portion 3L1.

  Next, an example of a method for forming the Au plating layer as described above will be described with reference to FIG.

  First, as shown in FIG. 16, a shielding plate M is placed on the exposed surface side of the bump land portion 3L2 on the strip-shaped tape 3T on which the wiring 3L is patterned.

  That is, in the wiring 3L of the flexible wiring board 3, the non-bonding surface side of the bump land portion 3L2 and the lead portion 3L1 is covered with the shielding plate M, and the pad side bonding surface of the lead portion 3L1 of the flexible wiring substrate 3 is exposed from the shielding plate M. It will be in the state.

  In this state, the flexible wiring 3 is put into the plating bath. The plating method may be, for example, electrolytic plating or electroless plating. As a result, the plating solution does not make much contact with the bump land portion 3L2 covered with the shielding plate M, but efficiently contacts the solder ball side joint surface of the lead portion 3L1 exposed from the shielding plate M. Therefore, an Au plating layer having a desired thickness can be formed on the lead joint surface of the lead portion 3L1.

  Thereafter, the shielding plate M is removed, and the Au plating process is similarly performed on the flexible wiring board 3. However, in this plating process, the Au plating layer is deposited to the thickness required for the bump land portion 3L2 of the flexible wiring board 3.

  By performing the Au plating process in two steps in this manner, the Au of the lead portion 3L1 is thick on the pad side bonding surface, and the bump land portion 3L2 is thin on the solder ball side bonding surface. A plated layer can be formed.

  However, the formation method of the Au plating layer is not limited to this, and can be variously changed. For example, a thin Au plating layer is first formed on the surface of the lead portion 3L1 of the wiring 3L and the solder ball bonding surface of the bump land portion 3L2. After the formation, a shielding plate M may be attached to the exposed surface side of the bump land portion 3L2, and a thick Au plating layer may be formed on the pad side bonding surface of the lead portion 3L1.

  Next, a method for assembling the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

  First, the elastomer 2 is formed on the flexible wiring board 3 by a printing method or the like (step 101).

  The wiring 3L has already been formed on the flexible wiring board 3 at this stage, and the lead portion 3L1 and the bump land portion 3L2 are plated as described above.

  However, at this stage, the lead portion 3L1 is not formed into a substantially S-shaped cross section, but is flat. Further, the tape 3T has a strip shape in which a plurality of package forming regions are integrated.

  The flexible wiring board 3 is formed as follows, for example. First, Cu foil is bonded to one whole surface of a strip-shaped tape made of, for example, polyimide resin or the like, for example, with an adhesive 6b. This Cu foil may be a rolled Cu foil or an electrolytic Cu foil. Subsequently, the wiring 3L is patterned by patterning the Cu foil by a photolithography technique and an etching technique. Thereafter, an opening or the like is formed in the tape 3T, and then the above-described plating process is performed on the exposed surface of the wiring 3L to form the flexible wiring board 3.

  The printing method for forming the elastomer 2 is, for example, as follows. First, a metal mask 8m as shown in FIG. 18 is prepared. In the metal mask 8m, two rectangular openings 8m1 arranged in parallel to each other are perforated at a predetermined distance. The opening 8m1 is a printing area where the elastomer 2 is formed.

  Subsequently, as shown in FIG. 19, after the metal mask 8m is arranged in alignment with the elastomer forming surface side of the flexible wiring board 3, an elastomer such as a silicone resin supplied on the metal mask 8m is formed. The material 2A is stretched in the printing direction of FIG. 19 by the squeegee 9, and is poured through the opening 8m1 of the metal mask 8m in the middle.

  Thereafter, the metal mask 8m is lifted. As a result, the elastomer 2 formed in the shape of the opening 8m1 of the metal mask 8m is printed on the flexible wiring board 3.

  However, the method of forming the elastomer 2 is not limited to the printing method and can be variously changed. For example, a tape-shaped elastomer-formed body is cut into a desired shape and size of the elastomer 2 and is then flexible printed circuit board. 3 may be bonded with an adhesive.

  After forming the elastomer 2 in this manner, an adhesive 6a made of, for example, a silicone material is applied to the upper surface of the elastomer 2 by a printing method (step 102), and the semiconductor chip 1 is attached to the elastomer via the adhesive 6a. 2 (step 103).

  In this step, for example, the following is performed. First, the main surface of the semiconductor chip 1, that is, the surface on which the bonding pads 5 are formed is opposed to the surface on which the adhesive 6a of the elastomer 2 is applied.

  Subsequently, the planar alignment of the semiconductor chip 1 and the flexible wiring board 3 is performed so that the relative positions of the bonding pads 5 on the main surface of the semiconductor chip 1 and the lead portions 3L1 on the flexible wiring board 3 coincide. I do.

  Thereafter, the semiconductor chip 1 is adhered to the elastomer 2 by the adhesive 6a by bringing the main surface of the semiconductor chip 1 into contact with the adhesive material application surface of the elastomer 2 while ensuring such an alignment state.

  After the semiconductor chip 1 is bonded to the elastomer 2 in this way, the lead portion 3L1 of the flexible wiring board 3 and the bonding pad 5 of the semiconductor chip 1 are bonded by a single bonding method or the like (step 104).

  In this step, for example, the following is performed. First, after making the main surface of the semiconductor chip 1 face the bonding tool 10 side, the bonding tool 10 is disposed above the tip of the lead portion 3L1 as shown in FIG.

  Subsequently, the lead tool 3L1 is bent as shown in FIG. 21 by dropping the bonding tool 10 perpendicularly to the main surface side of the semiconductor chip 1 (downward direction in FIG. 20).

  Further, as shown in FIG. 22, the bonding tool 10 is moved horizontally to the side of the elastomer 2 (to the left in the figure) until the tip of the lead 3L1 is located above the bonding pad 5 to lead the lead. After the portion 3L1 is further bent, it is lowered to the main surface side of the semiconductor chip 1, and the tip of the lead portion 3L1 and the bonding pad 5 are joined by an ultrasonic thermocompression bonding method or the like.

  After bonding the lead portion 3L1 of the flexible wiring board 3 and the bonding pad 5 of the semiconductor chip 1 in this way, the grooves exposed from the opening 3T1 of the tape 3T, that is, the side surfaces of the elastomer 2 and the semiconductor chip 1 facing each other. The sealing resin 7b is poured into the groove formed by the main surface by a dispenser method (step 105).

  As a result, the lead portion 3L1, the main surface of the semiconductor chip 1, and the bonding pad 5 are covered, and the reliability of the semiconductor integrated circuit device is improved.

  Next, after such a sealing process, the strip-shaped tape 3T constituting the flexible wiring board 3 at this stage is cut at a position slightly outside the outer periphery of the semiconductor chip 1 to thereby obtain a CSP type semiconductor integrated circuit. The package outline of the device is formed (step 106).

  At this stage, the side surface of the semiconductor chip 1 and the side surface of the elastomer 2 may be covered with the sealing resin 7a. Thereby, the reliability of the semiconductor integrated circuit device can be further improved.

  In the case of a so-called land grid array type semiconductor integrated circuit device in which the bump land portion 3L2 is left exposed without providing the solder bump electrode on the bump land portion 3L2 of the wiring board 3, at this stage. A pass / fail test is performed and the assembly process is completed.

  Subsequently, after the tape cutting step described above, solder bump electrodes 3B are formed by bonding solder balls made of, for example, a Pb—Sn alloy or the like to the bump land portion 3L2 of the flexible wiring board 3 (step 107).

  Thereafter, the CSP type semiconductor integrated circuit device is checked for quality by performing a predetermined inspection (step 108). In this way, the assembly process of the CSP type semiconductor integrated circuit device is completed.

  Next, FIG. 23 and FIG. 24 show the case where the CSP type semiconductor integrated circuit device of the first embodiment is applied to a memory card.

  A plurality of CSP type semiconductor integrated circuit devices 13 described in the present embodiment and, for example, one QFP (Quad Flat Package) type semiconductor integrated circuit device 14 are provided on the printed wiring board 12 constituting the memory card 11. Has been implemented.

  Each CSP type semiconductor integrated circuit device 13 is formed with a storage circuit such as DRAM, SRAM, mask ROM (Read Only Memory) or EEPROM (Electrically Erasable Programmable ROM). The solder bump electrode 3B of the CSP type semiconductor integrated circuit device 13 is electrically connected to the land of the printed wiring board 12.

  In the case of the so-called land grid array type semiconductor integrated circuit device described above, solder balls for forming the solder bump electrodes 3B may be attached to the land side of the printed wiring board 12.

  Further, the QFP type semiconductor integrated circuit device 14 is formed with a control circuit for controlling the operation of each CSP type semiconductor integrated circuit device and the operation of the entire memory circuit of the memory card 11, for example. The lead portion 14 a of the QFP type semiconductor integrated circuit device 14 is electrically connected to the land of the printed wiring board 12. The control circuit may be provided on the information processing apparatus side in which the memory card 11 is mounted.

  Each CSP type semiconductor integrated circuit device 13 and QFP type semiconductor integrated circuit device 14 are electrically connected through the lands and wirings formed on the printed wiring board, thereby having a predetermined configuration in the memory card. A memory circuit is formed.

  The wiring of the printed wiring board 12 is electrically connected to a plurality of terminals 15 regularly arranged at a predetermined interval on one short side of the printed wiring board 12. The terminal 15 is a connection terminal for electrically connecting a memory circuit having a predetermined configuration of the memory card 11 and an interface circuit of an information processing apparatus in which the memory card 11 is mounted.

  In this memory card 11, since the CSP type semiconductor integrated circuit device 13 as in the first embodiment is used as a memory, the memory card 11 can be made small, light and thin, and promotes an increase in memory capacity. It is possible to do.

As described above, according to the first embodiment, the following effects can be obtained.
(1) Aging inspection by changing the thickness of the Au plating layer on the pad side bonding surface of the lead portion 3L1 of the flexible wiring board 3 and the thickness of the Au plating layer on the solder ball side bonding surface of the bump land portion 3L2. Even after being left at a high temperature due to the above, sufficient bonding strength can be obtained on both the pad side bonding surface and the solder ball side bonding surface.
(2) Since the minimum necessary Au plating layer can be formed in each of the lead joint and the bump joint without lowering the joint strength, the amount of expensive Au used is minimized. Therefore, the manufacturing cost of the semiconductor integrated circuit device can be reduced.
(3). Between the core material portion 3Lb and the Au plating layer 3LmA1 at the pad side bonding surface of the lead portion 3L1, and between the core material portion 3Lb and the Au plating layer 3LmA2 at the solder ball side bonding surface of the bump land portion 3L2. By providing the Ni plating layers 3LmN1 and 3LmN2, it is possible to suppress the diffusion of Cu in the core portion 3Lb into the Au plating layers 3LmA1 and 3LmA2 during heat treatment in the manufacturing process and mounting process of the semiconductor integrated circuit device. As a result, it is possible to improve the reliability of the joint of each joint.
(4) By the above (1) to (3), it becomes possible to manufacture a highly reliable semiconductor integrated circuit device at a low cost.

(Embodiment 2)
25 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention, FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 25, and FIG. 27 is plating on the wiring substrate of the semiconductor integrated circuit device in FIG. It is explanatory drawing for demonstrating a processing method.

  In the semiconductor integrated circuit device according to the second embodiment, as shown in FIGS. 25 and 26, the tape 3T surface on which the wiring 3L of the flexible wiring board 3 is not formed is brought into contact with the elastomer 2 and the tape 3T The wiring 3L is covered with a photosensitive insulating film 16 such as a solder resist. Other than this, the structure is the same as that of the first embodiment.

  This photosensitive insulating film 16 is made of a material containing, for example, epoxy, polystyrene, polyimide, etc., has heat resistance, has a property of not getting wet with solder, and prevents deterioration of the wiring board surface due to moisture and contamination, Furthermore, the thing which has the property which can be equal to exposure to a flux or cleaning liquid is preferable. The photosensitive insulating film 16 includes a polymer material whose chemical and physical properties are changed by irradiation of radiation such as an electron beam.

  In the case of the structure in which the elastomer 2 is formed on the wiring forming surface side of the flexible wiring board 3, when the elastomer 2 is formed on the wiring forming surface, voids are formed in the gap between the wiring 3L and the wiring 3L. May end up.

  However, this void expands during heat treatment in the manufacturing process and mounting process of the semiconductor integrated circuit device, and may cause deformation, peeling or destruction of the flexible wiring board 3.

  Therefore, in the second embodiment, by forming the elastomer 2 on the flat tape 3T, it is possible to prevent a void from being formed between the flexible wiring board 3 and the elastomer 2 when the elastomer 2 is formed. Therefore, it is possible to improve the reliability of the CSP type semiconductor integrated circuit device during heat treatment during manufacturing or mounting.

  Further, in the case of a structure in which the solder bump electrode 3B and the bump land 3L2 of the wiring 3L are connected through the opening 3T2 (see FIGS. 1 and 2) drilled in the tape 3T, the opening 3T2 is formed with a punch or the like. Since it is formed by a mechanical processing method, there is a limit to the lower limit of the opening diameter, which hinders the size reduction of the solder bump electrode 3B, and the aspect ratio (opening depth and opening) of the opening 3T2 becomes smaller as the solder bump electrode 3B becomes finer. There is a risk that the reliability of the bonding between the solder bump electrode 3B and the bump land portion 3L2 will be reduced.

  Therefore, in the second embodiment, the wiring 3L on the tape 3T is covered with the photosensitive insulating film 16 that can be formed thinner than the tape 3T, and the opening 16a is formed on the photosensitive insulating film 16 by photolithography. And the solder bump electrode 3B and the bump land 3L2 of the wiring 3L are joined through the opening 16a.

  In this case, since the opening 16a for connecting the solder bump electrode 3B and the bump land 3L2 is formed by a photolithography technique capable of fine processing, the opening 3T2 formed on the tape 3T (see FIGS. 1 and 2). It is also possible to form a small opening 16a.

  Further, since the photosensitive insulating film 16 can be formed thinner than the tape 3T, an increase in the aspect ratio of the opening 16a can be prevented, and the reliability in bonding between the solder bump electrode 3B and the bump land 3L2. Can also be improved.

  In the semiconductor integrated circuit device having such a structure, the plating method applied to the wiring 3L of the flexible wiring board 3 is basically the same as that described in the first embodiment.

  That is, as shown in FIG. 27, the photosensitive insulating film 16 is applied on the wiring formation surface of the strip-shaped tape 3T on which the wiring 3L is patterned, and the opening 16a is formed by a photolithography technique and further cured.

  Subsequently, on the strip-shaped tape 3T on which the wiring 3L is formed, the photosensitive insulating film 16 is uncovered on the exposed surface side of the bump land portion 3L2, and the shielding plate M is adhered and covered.

  That is, in the wiring 3L of the flexible wiring board 3, the non-bonding surface side of the bump land portion 3L2 and the lead portion 3L1 is covered with the shielding plate M, and the pad side bonding surface of the lead portion 3L1 of the flexible wiring substrate 3 is exposed from the shielding plate M. It will be in the state.

  In this state, the flexible wiring 3 is put into the plating bath. The plating method may be, for example, electrolytic plating or electroless plating. As a result, the plating solution does not make much contact with the bump land portion 3L2 covered with the shielding plate M, but efficiently contacts the solder ball side joint surface of the lead portion 3L1 exposed from the shielding plate M. Therefore, an Au plating layer having a desired thickness can be formed on the lead joint surface of the lead portion 3L1.

  Thereafter, the shielding plate M is removed, and the Au plating process is similarly performed on the flexible wiring board 3. However, in this plating process, the Au plating layer is deposited to the thickness required for the bump land portion 3L2 of the flexible wiring board 3.

  By performing the Au plating process in two steps in this manner, the Au of the lead portion 3L1 is thick on the pad side bonding surface, and the bump land portion 3L2 is thin on the solder ball side bonding surface. A plated layer can be formed.

  However, the formation method of the Au plating layer is not limited to this, and can be variously changed. For example, a thin Au plating layer is first formed on the surface of the lead portion 3L1 of the wiring 3L and the solder ball bonding surface of the bump land portion 3L2. After the formation, a shielding plate M may be attached to the exposed surface side of the bump land portion 3L2, and a thick Au plating layer may be formed on the pad side bonding surface of the lead portion 3L1.

Thus, according to the second embodiment, in addition to the effects obtained in the first embodiment, the following effects can be obtained.
(1) By forming the elastomer 2 on the flat tape 3T, it is possible to prevent voids from being formed between the flexible wiring board 3 and the elastomer 2 when the elastomer 2 is formed. In addition, it is possible to prevent the semiconductor integrated circuit device from being broken during mounting.
(2). By covering the wiring 3L on the flexible wiring board 3 with the photosensitive insulating film 16, the opening 16a connecting the solder bump electrode 3B and the bump land 3L2 is formed by a photolithography technique capable of fine processing. Since it can be formed, the opening 16a can be made smaller than the opening of the tape 3T. Therefore, it is possible to promote the size reduction of the solder bump electrode 3B.
(3) By covering the wiring 3L on the flexible wiring board 3 with the photosensitive insulating film 16 which can be formed thinner than the tape 3T, an increase in the aspect ratio of the opening 16a can be prevented, and soldering can be performed. It is also possible to improve the reliability in bonding between the bump electrode 3B and the bump land 3L2.
(4) According to the above (1) to (3), the reliability and yield of the CSP type semiconductor integrated circuit device can be improved.

(Embodiment 3)
28 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 29 is a sectional view taken along line XXIX-XXIX in FIG.

  In the semiconductor integrated circuit device according to the third embodiment, a plurality of bonding pads 5 are arranged in the vicinity of the outer periphery of the main surface of the semiconductor chip 1 as shown in FIGS. On the main surface of the semiconductor chip 1, a flexible wiring board 3 having an outer shape smaller than the outer shape of the semiconductor chip 1 is bonded via an elastomer 2 having a planar rectangular shape.

  A plurality of lead portions 3L1 extending in the outer peripheral direction of the semiconductor chip 1 protrude from the outer periphery of the flexible wiring board 3, and the tip portions of the lead portions 3L1 are electrically connected to the bonding pads 5 on the main surface of the semiconductor chip 1. It is connected.

  A plurality of solder bump electrodes 3 </ b> B are regularly arranged on the main surface of the flexible wiring board 3 at a predetermined distance. Each solder bump electrode 3B is electrically connected to the bump land 3L2 of the flexible wiring board 3 through the opening 3T1 drilled in the tape 3T.

  The outer peripheral side surfaces of the elastomer 2 and the flexible wiring board 3 are covered with a sealing resin 7a, thereby covering the main surface of the semiconductor chip 1, the bonding pad 5 and the lead portion 3L1.

  Except for this configuration, the second embodiment is the same as the first embodiment. Therefore, according to the third embodiment, it is possible to obtain the same effect as that obtained in the first embodiment.

(Embodiment 4)
30 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 31 is a sectional view taken along line XXXI-XXXI in FIG.

  The semiconductor integrated circuit device of the fourth embodiment is basically the same as the structure described in the third embodiment, as shown in FIGS. The difference is that the surface of the flexible wiring board 3 where the wiring 3L is not formed comes into contact with the elastomer 2, and the wiring 3L on the tape 3T is replaced with a photosensitive insulating film 16 such as a solder resist. It is that it is the structure covered by.

  That is, the fourth embodiment has a structure in which the elastomer 2 is formed on the flat tape 3T of the flexible wiring board 3 as in the second embodiment.

  In the fourth embodiment, similar to the second embodiment, the wiring 3L on the tape 3T is covered with the photosensitive insulating film 16 that can be formed thinner than the tape 3T, and the photosensitive insulating film is formed. 16 has a structure in which an opening 16a is perforated by photolithography, and the solder bump electrode 3B and the bump land 3L2 of the wiring 3L are joined through the opening 16a.

  Therefore, in the fourth embodiment, in addition to the effects obtained in the third embodiment, it is possible to obtain the effects obtained in the second embodiment.

(Embodiment 5)
32 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 33 is a sectional view taken along line XXXIII-XXXIII in FIG.

  The semiconductor integrated circuit device according to the fifth embodiment has a protective member 17 as shown in FIGS. The protective member 17 is made of a metal having a high thermal conductivity such as Cu, for example, and a recess having a concave cross section is formed at the center of one surface thereof, and the semiconductor chip 1 is in its main surface in the recess. Is stored in a state facing downward in FIG.

  The back surface of the semiconductor chip 1 is bonded to the bottom surface of the recess of the protective member 17 through the adhesive 6c. The four side surfaces of the semiconductor chip 1 are surrounded by leg portions 17a on the outer periphery of the protective member 17 extending so as to surround the four side surfaces.

  Therefore, the heat generated during the operation of the semiconductor chip 1 can be dissipated through the protective member 17 from the back and side surfaces of the semiconductor chip 1.

  The main surface of the semiconductor chip 1 is exposed from the protection member 17, and the height of the main surface is set to be approximately equal to the upper surface height of the leg portion 17 a on the outer periphery of the protection member 17. In the vicinity of the outer periphery of the main surface of the semiconductor chip 1, a plurality of bonding pads 5 are arranged along the outer periphery.

  On the main surface of the semiconductor chip 1, a planar square-shaped elastomer 2a formed so as to expose the bonding pad forming region is bonded via an adhesive 6a.

  A planar frame-shaped elastomer 2b formed along the shape of the upper surface of the leg portion 17a is bonded onto the leg portion 17a of the protective member 17 via an adhesive 6d. The elastomers 2a and 2b are formed at the same time, for example, and are formed so that the heights of the upper surfaces thereof are substantially the same.

  On such elastomers 2a and 2b, the flexible wiring board 3 is joined with the formation surface of the wiring 3L formed on the tape 3T facing the elastomers 2a and 2b.

  In the flexible wiring board 3, four relatively wide openings 3T1 are formed at positions on the four sides of the semiconductor chip 1 so that the bonding pads 5 on the outer periphery of the semiconductor chip 1 are exposed.

  That is, the flexible wiring board 3 includes a rectangular portion disposed on the main surface of the semiconductor chip 1 and a frame portion disposed on the leg portion 17a of the protective member 17, and the rectangular portion. However, it is connected and supported by tapes 3T extending from the four corners to the four corners of the inner periphery of the frame-shaped portion.

  A lead portion 3L1 of the wiring 3L projects from the outer periphery of the rectangular portion of the flexible wiring board 3. The lead portion 3L1 is electrically connected to the bonding pad 5 on the outer periphery of the main surface of the semiconductor chip 1, for example, in a state where the lead portion 3L1 is bent in a substantially S-shaped cross section.

  Further, the bump land portion 3L2 of the wiring 3L in the rectangular portion of the flexible wiring board 3 is electrically connected to the solder bump electrode 3B through the opening 3T2 drilled in the tape 3T. On the main surface of the rectangular portion of the flexible wiring board 3, the solder bump electrodes 3B are regularly arranged at a predetermined distance.

  On the other hand, the lead portion 3L1 of the wiring 3L protrudes also from the inner periphery of the frame-like portion of the flexible wiring board 3. The lead portion 3L1 is electrically connected to the bonding pad 5 on the outer periphery of the main surface of the semiconductor chip 1, for example, in a state where the lead portion 3L1 is bent in a substantially S-shaped section. Since the plating structure of the lead portion 3L1 is the same as that of the first embodiment, the description thereof is omitted.

  Further, the bump land 3L2 of the wiring 3L in the frame-like portion of the flexible wiring board 3 is electrically connected to the solder bump electrode 3B through the opening 3T2 drilled in the tape 3T. Since the plating structure of the bump land portion 3L2 is the same as that of the first embodiment, the description thereof is omitted.

  On the main surface of the frame-shaped portion of the flexible wiring board 3, the solder bump electrodes 3B are regularly arranged along the outer periphery of the frame-shaped portion. That is, the solder bump electrodes 3 </ b> B are also arranged on the main surface of the frame-like portion in the flexible wiring substrate 3 arranged outside the outer periphery of the semiconductor chip 1.

  As a result, the number of solder bump electrodes 3B that can be arranged can be increased as compared with the case where the solder bump electrodes 3B are provided only on the rectangular portion of the flexible wiring board 3. The structure is compatible.

  A groove portion exposed from the opening 3T1 of the flexible wiring board 3 is filled with a sealing resin 7c. As a result, the main surface of the semiconductor chip 1, the bonding pad 5 and the lead portion 3L1 are covered, so that the reliability of the semiconductor integrated circuit device can be improved.

Thus, according to the fifth embodiment, in addition to the effects obtained in the first embodiment, the following effects can be obtained.
(1) Since the solder bump electrodes 3B can be arranged on the frame-like portion of the flexible wiring board 3 arranged outside the outer periphery of the semiconductor chip 1, the multi-pin requirement of the semiconductor integrated circuit device can be met. Is possible.
(2) By providing the protective member 17 on the outer periphery of the semiconductor chip 1, it is resistant to external impacts and can improve the transportability.
(3) Since the back surface of the semiconductor chip 1 is joined to the protection member 17 and the side surface of the semiconductor chip 1 is surrounded by the protection member 17, heat can be released from the back surface and side surface of the semiconductor chip 1 as well. Thus, the heat dissipation performance of the semiconductor integrated circuit device can be improved. Therefore, it is possible to improve the operational reliability and lifetime of the semiconductor integrated circuit device.

(Embodiment 6)
34 is a plan view of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 35 is a sectional view taken along line XXXV-XXXV in FIG.

  The semiconductor integrated circuit device of the sixth embodiment is basically the same as the structure described in the fifth embodiment, as shown in FIGS. The difference is that the surface of the flexible wiring board 3 where the wiring 3L is not formed comes into contact with the elastomer 2, and the wiring 3L on the tape 3T is replaced with a photosensitive insulating film 16 such as a solder resist. It is that it is the structure covered by.

  That is, the sixth embodiment has a structure in which the elastomer 2 is formed on the flat tape 3T of the flexible wiring board 3 as in the second embodiment.

  In the sixth embodiment, similarly to the second embodiment, the wiring 3L on the tape 3T is covered with the photosensitive insulating film 16 that can be formed thinner than the tape 3T, and the photosensitive insulating film is formed. 16 has a structure in which an opening 16a is perforated by photolithography, and the solder bump electrode 3B and the bump land 3L2 of the wiring 3L are joined through the opening 16a.

  Therefore, in the sixth embodiment, in addition to the effects obtained in the fifth embodiment, the effects obtained in the second embodiment can be obtained.

(Embodiment 7)
36 is a plan view of a principal part of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 37 is a sectional view taken along line XXXVII-XXXVII in FIG.

  In the seventh embodiment, as shown in FIGS. 36 and 37, an opening 3T1 penetrating the upper and lower surfaces of the tape 3T is perforated at the center of the flexible wiring board 3, and the opening 3T1 is formed in the opening 3T1. The semiconductor chip 1 is well arranged with its main surface exposed. The semiconductor chip 1 is arranged so that its main surface is in a direction facing the flat surface (non-wiring forming surface) of the tape 3T.

  In the vicinity of the outer periphery of the back surface of the tape 3T of the flexible wiring board 3, a protective frame 18a extending along the outer periphery of the tape 3T is bonded via an adhesive 6e. Thereby, the deformation | transformation etc. of the flexible wiring board 3 are prevented.

  Further, the wiring 3L is bonded to the main surface of the tape 3T of the flexible wiring board 3 with an adhesive 6b. Further, a photosensitive insulating film 16 such as a solder resist is deposited on the main surface of the tape 3T, thereby covering the wiring 3L.

  The lead portion 3L1 of the wiring 3L protrudes from the inner periphery of the flexible wiring board 3, and is formed in, for example, a substantially S-shaped cross section and is electrically connected to the bonding pad 5 near the outer periphery of the semiconductor chip 1. The lead portion 3L1 is also subjected to the same plating process as in the first embodiment.

  The bump land portion 3L2 of the wiring 3L is electrically connected to the solder bump electrode 3B through a fine opening portion 16a drilled in the photosensitive insulating film 16. The bump bonding surface of the bump land portion 3L2 is also subjected to the same plating process as in the first embodiment. The solder bump electrodes 3B are regularly arranged on the main surface of the flexible wiring board 3 along the outer periphery thereof.

  The opening 3T of the flexible wiring board 3 is filled with a sealing resin 7d. Thereby, the semiconductor chip 1 has a structure that is relatively firmly fixed. Further, the main surface, side surface, bonding pad 5 and lead portion 3L1 of the semiconductor chip 1 are covered, so that the reliability of the semiconductor integrated circuit device can be improved. In FIG. 36, the sealing resin 7d is not shown for easy viewing of the drawing.

  Thus, according to the seventh embodiment, it is possible to obtain the same effects as those obtained in the first and second embodiments.

(Embodiment 8)
FIG. 38 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention.

  The semiconductor integrated circuit device according to the eighth embodiment is basically the same as the structure described in the seventh embodiment as shown in FIG. The plan view is the same as FIG. 36 used in the seventh embodiment.

  The difference is that the height of the main surface of the semiconductor chip 1 and the height of the formation surface of the wiring 3L of the flexible wiring board 3 are set to be substantially the same, and the lead 3L1 of the wiring 3L is flat and the semiconductor chip 1 is flat. That is, it is electrically connected to the bonding pad 5 on the main surface.

  That is, no bending is formed in the lead portion 3L1. However, the same plating treatment as described in the first embodiment is applied to the lead bonding surface of the lead portion 3L1 and the bump bonding surface of the bump land portion 3L2.

  Therefore, in the eighth embodiment, it is possible to obtain the same effect as that obtained in the first and second embodiments.

(Embodiment 9)
FIG. 39 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention.

  The semiconductor integrated circuit device according to the ninth embodiment is basically the same as the structure described in the seventh embodiment, as shown in FIG. The plan view on the bump electrode forming surface side is the same as FIG. 36 used in the seventh embodiment. The difference is as follows.

  First, the height of the main surface of the semiconductor chip 1 and the height of the formation surface of the wiring 3L of the flexible wiring board 3 are set to be substantially the same, and the lead 3L1 of the wiring 3L is flat and the semiconductor chip 1 is flat. That is, it is electrically connected to the bonding pad 5 on the main surface.

  That is, no bending is formed in the lead portion 3L1. However, the same plating treatment as described in the first embodiment is applied to the lead bonding surface of the lead portion 3L1 and the bump bonding surface of the bump land portion 3L2.

  Second, the back surface of the semiconductor chip 1 is joined to the heat radiating plate 19 by the adhesive 6f, so that the heat generated in the semiconductor chip 1 can be dissipated from the back surface of the semiconductor chip 1. is there.

  The heat sink 19 is made of a metal having high thermal conductivity such as Cu. The adhesive 6f is made of an adhesive material having heat dissipation and heat resistance, for example.

  Between the outer peripheral surface of the heat radiating plate 19 and the non-bump electrode forming surface of the tape 3T, a protective frame 18b having substantially the same shape as the planar shape of the tape 3T is installed so as to surround the side surface of the semiconductor chip 1. The protective frame 18b is joined to the heat radiating plate 19 with an adhesive 6g.

  The protective frame 18b is made of the same material as the heat radiating plate 19, for example. This is because the function of dissipating the heat generated in the semiconductor chip 1 is given, the bonding property with the heat sink 19 is taken into consideration, and the reliability in bonding with the heat sink 19 when heat is generated is taken into consideration. Because of that. The adhesive 6g is also made of an adhesive material having heat dissipation and heat resistance, for example.

  The main surface of the semiconductor chip 1 and the lead portion 3L1 are covered with a sealing resin 7d, thereby improving the reliability of the semiconductor integrated circuit device.

As described above, in the ninth embodiment, in addition to the effects obtained in the first and second embodiments, the following effects can be obtained.
(1) The structure in which the semiconductor chip 1 is surrounded by the protective frame 18b and the heat radiating plate 19 is strong against an external impact and can improve the transportability.
(2) By bonding the back surface of the semiconductor chip 1 to the heat radiating plate 19 and surrounding the side surface of the semiconductor chip 1 with a protective frame 18b having high heat dissipation, heat is also applied from the back surface and side surface of the semiconductor chip 1. Since it can escape, the heat dissipation performance of the semiconductor integrated circuit device can be improved. Therefore, it is possible to improve the operational reliability and lifetime of the semiconductor integrated circuit device.

(Embodiment 10)
40 is a plan view of a principal part of a semiconductor integrated circuit device according to another embodiment of the present invention, FIG. 41 is a sectional view taken along line XXXXI-XXXXI in FIG. 40, and FIGS. 42 to 44 are semiconductor integrated circuit devices in FIG. It is principal part sectional drawing in the manufacturing process of this.

  In the tenth embodiment, as shown in FIG. 40 and FIG. 41, an opening located on the leading end side of the lead portion 3L1 in the opening 4b1 of the passivation film 4b formed on the uppermost layer of the main surface of the semiconductor chip 1 The end is formed so as to recede in a direction away from the bonding pad 5 as compared with the first embodiment.

  The other configuration is the same as that of the first embodiment. Note that although the plating structure is not shown in the wiring 3L in FIG. 41, the same plating treatment as in the first embodiment is performed.

  In this semiconductor integrated circuit device, when the lead portion 3L1 and the bonding pad 5 are joined by the bonding tool, the lead portion 3L1 is in contact with the main surface of the semiconductor chip 1 as described in the first embodiment. After being downed to a position, it is shifted in a direction perpendicular to the downhill direction, and further down on the bonding pad 5.

  For this reason, the pad-side bonding surface of the lead portion 3L1 may come into contact with the main surface of the semiconductor chip 1 at the time of the first downing, which causes damage to the passivation film 4b and the semiconductor chip 1. In addition, the components of the passivation film 4b may adhere to the pad side bonding surface of the lead portion 3L1, and the bonding performance may be deteriorated.

  Therefore, in the tenth embodiment, the opening end portion of the lead portion 3L1 at the opening portion 4b1 of the passivation film 4b formed on the uppermost layer of the main surface of the semiconductor chip 1 is used as the lead portion 3L1 in the lead bonding step. The lead portion 3L1 is formed so as to recede in the direction away from the bonding pad 5 so that the lead portion 3L1 does not contact the passivation film 4b on the main surface of the semiconductor chip 1 when the semiconductor chip 1 is lowered to the main surface side. Yes.

  Here, in the first embodiment, the length from the end of the opening 4a1 of the passivation film 4a to the end of the opening 4b1 of the passivation film 4b is, for example, about 25 μm.

  Further, the dimension of the pressing surface of the bonding tool is equal to or slightly smaller than that of the bonding pad 5. The size of the bonding pad 5 is, for example, about 100 μm × 100 μm.

  Therefore, since it varies depending on the product, the length L from the end of the opening 4a1 of the passivation film 4a to the end of the opening 4b1 of the passivation film 4b in the tenth embodiment is about 125 μm, for example. Is preferred.

  Next, the bonding process steps between the lead portion 3L1 and the bonding pad 5 in the semiconductor integrated circuit device of the tenth embodiment will be described with reference to FIGS. 42 to 44, although the plating structure is not shown in the wiring 3L, the same plating process as in the first embodiment is performed.

  First, after the main surface of the semiconductor chip 1 is directed toward the bonding tool 10, the bonding tool 10 is disposed above the tip of the lead portion 3L1, as shown in FIG.

  Subsequently, the lead tool 3L1 is bent as shown in FIG. 43 by dropping the bonding tool 10 perpendicularly to the main surface side of the semiconductor chip 1 (downward in FIG. 42).

  At this time, since there is no passivation film 4b below the lead portion 3L1, for example, the passivation film 4 or the semiconductor chip 1 is damaged, or the component of the passivation film 4b adheres to the pad side bonding surface of the lead portion 3L1. There is no problem caused by the lead portion 3L1 coming into contact with the passivation film 4b, such as deterioration in performance.

  Subsequently, the bonding tool 10 is moved horizontally to the side of the elastomer 2 (to the left in FIG. 43) until the tip of the lead 3L1 is positioned above the bonding pad 5, and then the bonding tool 10 is moved. As shown in FIG. 44, the tip of the lead portion 3L1 and the bonding pad 5 are joined by an ultrasonic thermocompression bonding method or the like.

Thus, according to the tenth embodiment, in addition to the effects obtained in the first embodiment, the following effects can be obtained.
(1) Lead bonding step by retreating the opening end on the leading end side of the lead portion 3L1 away from the bonding pad 5 in the opening 4b1 of the passivation film 4b in the uppermost layer of the semiconductor chip 1 main surface. When the lead portion 3L1 is lowered to the main surface side of the semiconductor chip 1, the lead portion 3L1 can be prevented from coming into contact with the passivation film 4b.
(2) By the above (1), it is possible to avoid the problem that the lead portion 3L1 damages the main surface side of the semiconductor chip 1 during the lead bonding step.
(3) By the above (1), it is possible to avoid the problem that the component of the passivation film 4b adheres to the pad side bonding surface of the lead portion 3L1 during the lead bonding step, thereby deteriorating the bonding property. It is possible to improve the reliability of bonding with the pad 5.
(4) By the above (1) to (3), it becomes possible to improve the yield and reliability of the semiconductor integrated circuit device.

(Embodiment 11)
FIG. 45 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention.

  The structure of the semiconductor integrated circuit device of the eleventh embodiment shown in FIG. 45 is substantially the same as the structure of the semiconductor integrated circuit device of the second embodiment. The difference is that a second-layer wiring 3 </ b> L is provided between the back surface of the tape 3 </ b> T of the flexible wiring substrate 3 and the elastomer 2.

  The second layer wiring 3L is a wiring for a reference voltage such as a power supply voltage or a ground voltage, and is formed so as to cover the entire back surface of the tape 3T. Accordingly, in the tape 3T, unevenness due to the second-layer wiring 3L is not formed on the formation surface of the second-layer wiring 3L. That is, the surface where the flexible wiring board 3 contacts the elastomer 2 is flat.

  Therefore, it is possible to prevent voids from being formed between the flexible wiring board 3 and the elastomer 2 when the elastomer 2 is formed. Therefore, a CSP type semiconductor integrated circuit device during heat treatment such as manufacturing and mounting. Can be prevented.

  The second-layer wiring 3L is electrically connected to the solder bump electrode 3B through the opening 20 formed in the tape 3T and the photosensitive insulating film 16.

  Note that an insulating film 21 is provided in a portion where the first layer wiring 3L is in contact with the opening 20, and the solder bump electrode 3B and the first layer wiring 3L are insulated.

  The core material portion of the second layer wiring 3L is made of, for example, Cu, and the surface of the lead portion connecting the second layer wiring 3L and the bonding pad 5 and the bump bonding surface of the bump land portion have the above-mentioned The same plating process as in the first embodiment is performed.

Therefore, in the eleventh embodiment, in addition to the effects obtained in the first and second embodiments, the following effects can be obtained.
(1) Since the flexible wiring board 3 has two wiring layers, the degree of freedom of wiring can be improved, and therefore the ease of wiring design of the flexible wiring board 3 can be improved. Become.
(2) The wiring layer of the flexible wiring board 3 has two layers, and one wiring layer is a solid wiring layer for a reference voltage such as a power supply voltage or a ground voltage, so that the wiring of the other wiring layer is provided. Since noise generated in 3L can be reduced, the operation reliability of the semiconductor integrated circuit device can be improved.

(Embodiment 12)
46 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIGS. 47A and 47B are schematic views of the cross-sectional state of the wiring in the flexible wiring of the semiconductor integrated circuit device of FIG. FIG. 48 is an explanatory diagram for explaining cracks in the lead portion of the flexible wiring board.

  In the twelfth embodiment, as shown in FIGS. 46 and 47, Ni plating layers 3LmN1, 3LmN2 are formed only on the surface of the lead portion 3L1 on the lead joint portion side and only on the solder ball side joint surface of the bump land portion 3L2. Has been. The rest of the configuration is the same as that of the semiconductor integrated circuit device of the first embodiment.

  In the case of the structure in which the Ni plating layer is formed on the entire surface of the lead portion 3L1, the Ni plating layer has a hard and brittle property. Therefore, as shown in FIG. Cracks 23 may occur. In FIG. 48, reference numeral 24 denotes an Ni plating layer, reference numeral 25 denotes an Au plating layer, and reference numeral 26 denotes a core part of the wiring.

  However, if the Ni plating layer in the lead portion 3L1 is completely eliminated, Cu constituting the core portion 3Lb of the lead portion 3L1 becomes the Au plating layer 3LmA1, 3LmA2 in the heat treatment during the manufacturing process or mounting process of the semiconductor integrated circuit device. As a result of diffusion to the side, there may be a problem that the bonding strength of the lead bonding portion and the bump bonding portion deteriorates.

  Therefore, in the twelfth embodiment, Ni plating layers 3LmN1 and 3LmN2 are formed on the surface of the lead joint portion of the lead portion 3L1 and the upper surface of the bump land portion 3L2, but Ni plating is applied to the other lead portion 3L1. The layers 3LmN1 and 3LmN2 were not formed.

  47A schematically shows the cross-sectional state of the lead joint portion of the lead portion 3L1, and FIG. 47B schematically shows the cross-sectional state of the bent portion of the lead portion 3L1.

  As a result, it is possible to prevent the problem of cracks in the bent portion of the lead portion 3L1, and Cu constituting the core material portion 3Lb diffuses into the Au plating layers 3LmA1 and 3LmA2 at the lead joint portion and the bump joint portion during heat treatment. It has a structure that can prevent.

Thus, in the twelfth embodiment, in addition to the effects obtained in the first embodiment, the following effects can be obtained.
(1) By forming the Ni plating layers 3LmN1 and 3LmN2 only on the surface of the lead joint portion of the lead portion 3L1 and the upper surface of the bump land portion 3L2, it is possible to prevent the problem of cracks in the bent portion of the lead portion 3L1. At the same time, it is possible to prevent the Cu of the core material portion 3Lb from diffusing into the Au plating layers 3LmA1 and 3LmA2 at the lead bonding portion and the bump bonding portion during heat treatment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described Embodiments 1 to 12, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the seventh embodiment, the case where the bonding pad is provided near the outer periphery of the semiconductor chip has been described. However, the present invention is not limited to this, and the bonding pad is arranged at the center of the main surface of the semiconductor chip. It can also be applied to structures.

  In the eighth and ninth embodiments, the wiring of the flexible wiring board is covered with the photosensitive insulating film, and the bump land portion of the wiring and the solder bump electrode are joined through the opening formed in the photosensitive insulating film. However, the present invention is not limited to this. For example, as described in the first embodiment, in the flexible wiring board, the wiring is formed on one surface of the tape and is opposed thereto. A solder bump electrode may be provided on the other surface of the tape to be connected, and the bump land portion of the wiring and the solder bump electrode may be electrically connected through an opening formed in the tape. In this case, the semiconductor chip is arranged so that its main surface faces the direction facing the wiring formation surface of the tape.

  In the first to twelfth embodiments, the case where the metal layer such as the gold plating layer and the Ni plating layer is formed by the electrolytic plating method or the electroless plating method has been described. However, the present invention is not limited thereto. Instead, it may be deposited on the core part of the wiring by, for example, sputtering or vapor deposition.

  In the above description, the case where the invention made by the present inventor is mainly applied to a BGA type semiconductor integrated circuit device has been described. However, the present invention is not limited to this. For example, a solder bump electrode is not provided on a wiring board. Thus, the present invention can be applied to a so-called land grid array type semiconductor integrated circuit device in which the bump land portion is exposed.

  Although the case where the semiconductor integrated circuit device having the present invention is applied to a memory card has been described, the present invention is not limited to this, and can be applied to, for example, a mobile phone, a portable computer, a large computer, or the like.

  The present invention can be applied to the manufacturing industry of semiconductor integrated circuit devices.

1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention. It is sectional drawing of the II-II line of FIG. FIG. 2 is a plan view of a principal part of the semiconductor integrated circuit device of FIG. 1. It is sectional drawing of the IV-IV line of FIG. It is a graph which shows the relationship between the thickness of the gold layer formed in each junction surface of the wiring of a wiring board, and the joint strength deterioration rate in each junction part. FIG. 2 is a cross-sectional view of a main part of the semiconductor integrated circuit device showing an example of a wiring plating structure on the wiring substrate of the semiconductor integrated circuit device of FIG. 1. FIG. 7 is an explanatory diagram schematically showing a plating structure of a joint surface of a lead portion and a joint surface of a bump electrode in the wiring of the semiconductor integrated circuit device of FIG. 6. FIG. 7 is a cross-sectional view of the principal part of the semiconductor integrated circuit device showing another example of the plating structure in the lead portion of the semiconductor integrated circuit device of FIG. 1. FIG. 9 is an explanatory diagram schematically illustrating a plating structure of a bonding surface of a lead portion and a bonding surface of a bump electrode in the wiring of the semiconductor integrated circuit device of FIG. 8. FIG. 7 is a cross-sectional view of the principal part of the semiconductor integrated circuit device showing another example of the plating structure in the lead portion of the semiconductor integrated circuit device of FIG. 1. FIG. 11 is an explanatory diagram schematically illustrating a plating structure of a bonding surface of a lead portion and a bonding surface of a bump electrode in the wiring of the semiconductor integrated circuit device of FIG. 10. FIG. 7 is a cross-sectional view of the principal part of the semiconductor integrated circuit device showing another example of the plating structure in the lead portion of the semiconductor integrated circuit device of FIG. 1. FIG. 13 is an explanatory diagram schematically showing a plating structure of a joint surface of a lead portion and a joint surface of a bump electrode in the wiring of the semiconductor integrated circuit device of FIG. FIG. 7 is a cross-sectional view of the principal part of the semiconductor integrated circuit device showing another example of the plating structure in the lead portion of the semiconductor integrated circuit device of FIG. 1. FIG. 15 is an explanatory diagram schematically showing a plating structure of a joint surface of a lead portion and a joint surface of a bump electrode in the wiring of the semiconductor integrated circuit device of FIG. 14. FIG. 3 is an explanatory diagram for explaining a plating method for the wiring board of the semiconductor integrated circuit device of FIG. 1. FIG. 8 is an explanatory diagram for explaining an assembly process of the semiconductor integrated circuit device of FIG. 1. FIG. 2 is a plan view of a mask used in a process for forming an elastic structure of the semiconductor integrated circuit device of FIG. 1. FIG. 2 is an explanatory diagram of a process for forming an elastic structure of the semiconductor integrated circuit device of FIG. 1. FIG. 2 is an explanatory diagram of a lead connection process of the semiconductor integrated circuit device of FIG. 1. FIG. 21 is an explanatory diagram of a lead connection process following FIG. 20 of the semiconductor integrated circuit device of FIG. 1; FIG. 22 is an explanatory diagram of a lead connection process following FIG. 21 of the semiconductor integrated circuit device of FIG. 1; It is explanatory drawing of the example of application of the semiconductor integrated circuit device of FIG. It is explanatory drawing of the example of application of the semiconductor integrated circuit device of FIG. It is a top view of the semiconductor integrated circuit device which is other embodiment of this invention. It is sectional drawing of the XXVI-XXVI line of FIG. FIG. 26 is an explanatory diagram for explaining a plating method for the wiring board of the semiconductor integrated circuit device of FIG. 25; It is a top view of the semiconductor integrated circuit device which is other embodiment of this invention. It is sectional drawing of the XXIX-XXIX line | wire of FIG. It is a top view of the semiconductor integrated circuit device which is other embodiment of this invention. It is sectional drawing of the XXXI-XXXI line | wire of FIG. It is a top view of the semiconductor integrated circuit device which is other embodiment of this invention. It is sectional drawing of the XXXIII-XXXIII line | wire of FIG. It is a top view of the semiconductor integrated circuit device which is other embodiment of this invention. It is sectional drawing of the XXXV-XXXV line | wire of FIG. It is a principal part top view of the semiconductor integrated circuit device which is other embodiment of this invention. It is sectional drawing of the XXXVII-XXXVII line of FIG. It is principal part sectional drawing of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor integrated circuit device which is other embodiment of this invention. It is a principal part top view of the semiconductor integrated circuit device which is other embodiment of this invention. It is sectional drawing of the XXXXI-XXXXI line | wire of FIG. FIG. 41 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 40 during a manufacturing step. FIG. 43 is an essential part cross sectional view of the semiconductor integrated circuit device of FIG. 40 during a manufacturing step following that of FIG. 42; FIG. 44 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 40 during the manufacturing process following that of FIG. 43; It is principal part sectional drawing of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor integrated circuit device which is other embodiment of this invention. (A) And (b) is explanatory drawing which showed typically the cross-sectional state of the wiring in the flexible wiring of the semiconductor integrated circuit device of FIG. It is explanatory drawing for demonstrating the crack in the lead part of a flexible wiring board.

Explanation of symbols

1 Semiconductor chip 2, 2a, 2b Elastomer (elastic structure)
2A Elastomer forming material 3 Flexible wiring board (wiring board)
3T tape (substrate substrate)
3L wiring 3L1 lead 3L2 bump land 3L3 plating current supply wiring 3LmA1 gold plating layer (first gold layer)
3LmA2 gold plating layer (second gold layer)
3LmN1 Nickel plating layer 3LmN2 Nickel plating layer 3LmP1 Palladium plating layer 3B Solder bump electrode 4 Passivation film 4a Passivation film 4a1 Opening 4b Passivation film 4b1 Opening 5 Bonding pad (external terminal)
6a to 6g Adhesives 7a to 7d Sealing resin 8m Metal mask 8m1 Opening 9 Squeegee 10 Bonding tool 11 Memory card 12 Printed wiring board 13 CSP type semiconductor integrated circuit device 14 QFP type semiconductor integrated circuit device 15 Terminal 16 Photosensitivity Insulating film (insulating film)
16a Opening 17 Protective member 17a Legs 18a, 18b Protective frame 19 Heat sink 20 Opening 21 Insulating film 22 Lead part 23 Crack 24 Nickel plating layer 25 Gold plating layer 26 Core material M Shielding plate Z Insulating film

Claims (4)

The wiring lead formed on the wiring board is electrically connected to the external terminal on the main surface of the semiconductor chip, and the wiring land formed on the wiring board is electrically connected to the solder bump electrode. A semiconductor integrated circuit device comprising:
(A) While joining the lead portion to the external terminal through a metal layer formed in the order of a nickel layer and a first gold layer,
(B) The semiconductor integrated circuit device, wherein the land portion is joined to the solder bump electrode through a nickel layer.   2. The semiconductor integrated circuit device according to claim 1, wherein an elastic structure is provided between the main surface of the semiconductor chip and the wiring substrate, and the lead portion of the wiring substrate is bent. A semiconductor integrated circuit device characterized in that it is electrically connected to an external terminal. The wiring lead formed on the wiring board is electrically connected to the external terminal on the main surface of the semiconductor chip, and the wiring land formed on the wiring board is electrically connected to the solder bump electrode. A semiconductor integrated circuit device comprising:
(A) While joining the lead part to the external terminal through a first gold layer,
(B) The semiconductor integrated circuit device, wherein the land portion is bonded to the solder bump electrode through a palladium layer.   4. The semiconductor integrated circuit device according to claim 3, wherein an elastic structure is provided between the main surface of the semiconductor chip and the wiring substrate, and a lead portion of the wiring substrate is bent. A semiconductor integrated circuit device characterized in that it is electrically connected to an external terminal.

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