JP2006159551A - Inkjet recorder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inkjet recorder whereby an accessing frequency to a printing buffer can be reduced to half, bottleneck in memory accessing is solved, and a high speed as the whole system can be attained, by leading accessing of the second time and afterwards from a FIFO memory side at the time when the same ejection data is distributed to a plurality of heads and printed by temporarily storing data for head ejection into the FIFO memory inside an inkjet printer controller. <P>SOLUTION: Head ejection data stored in the printing buffer is temporarily stored in the FIFO memory present in the inkjet printer controller. Thereafter, the FIFO memory is repeatedly read for an amount of a plurality of nozzle arrays in line with respective ejection timings of the nozzle arrays. Data necessary for designated nozzle arrays is selected from the read ejection data and printed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention divides data for one column composed of many nozzles into blocks that are simultaneously ejected, transmits the divided data to an inkjet head, and applies energy by heat pulses after transmission. The present invention relates to an ink jet recording apparatus using an ink jet head having a structure for ejecting ink.

  A head used in an ink jet printer has an ink nozzle that is an opening facing a recording medium, and has a structure that discharges ink droplets by heating a heater existing in a deep part of the nozzle and generating bubbles. Yes.

  Many printers have used an encoder scale and an optical transmission sensor to detect the scale position to detect the absolute position of the carriage to determine the ink ejection timing, thereby realizing high-definition inkjet printing. It was.

  Based on the printing position information determined by the encoder scale, the inkjet printer controller transmits ejection data to the inkjet head, and after transmission, heat pulses are applied, energy is input, ink is ejected, and an image is formed.

In recent years, the number of nozzles in the column direction of the head tends to increase, and the printing speed has been improved by discharging many nozzles simultaneously. However, when the number of nozzles increases, it is impossible for the power supply to discharge all the data for one column at the same time, and it is necessary to heat the maximum simultaneous discharge nozzles permitted by the power supply in units of the same block. The nozzle data belonging to the block unit is serially transmitted from the ink jet printer controller side, and after transmission, the data is latched in the latch circuit inside the head, and then the heat pulse is applied, and the head voltage is changed when the heat pulse is active. In addition, the ink is added to the heater inside the inkjet head, and ink is ejected from the nozzle. (See Patent Document 1)
In addition, since bubbles are generated and ink droplets are ejected, the minimum time required for the generation of bubbles is determined in advance from the structure of the head and the ink, and the drive needs to be performed at a maximum drive frequency or less. As the number of nozzles increases, the number of block divisions also increases, and the discharge time required for one column is (number of block divisions) x (1 / maximum drive frequency)
It will take more than that.
JP 2002-96471 A

  In recent years, in order to improve print image quality, the ink jet nozzle shape has been further miniaturized, ink droplets have become smaller, and higher-resolution printing has become possible.

  On the other hand, there is a need for further improvement in printing speed. In addition to increasing the number of nozzles in the main scanning direction, by adding more nozzle rows in the sub-scanning direction, multiple nozzle rows can be used for high-speed carriage operations. It is necessary to multiply the discharge frequency of the entire head by a plurality of times by alternately discharging the nozzles and limiting the blocks output by the respective nozzle rows. However, when a nozzle row is simply added, there has been a problem that the data reading process is not in time for the ejection data control circuit in the conventional ink jet printer controller.

  The ink jet recording apparatus of the present invention stores the head discharge data stored in the print buffer, which is an external large capacity memory of the ink jet printer controller, once in the FIFO memory inside the ink jet printer controller, and then stores the plurality of nozzle arrays. According to each ejection timing, the FIFO memory is repeatedly read out for each nozzle row, and data necessary for the designated nozzle row is selected from the read ejection data, and printing is performed.

  As described above, according to the present invention, when the head ejection data is stored in the FIFO memory inside the temporary inkjet printer controller, when the same ejection data is distributed to a plurality of heads and printed, the second and subsequent accesses are performed by the FIFO. By reading from the memory side, it is possible to halve the frequency of access to the print buffer, eliminating the bottleneck of memory access and increasing the speed of the entire system.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 3 is a schematic view of a printer unit used in the present invention.

  Reference numeral 301 denotes an auto-feeder unit, which separates sheets stacked one by one and performs a sheet feeding operation by a sheet feeding mechanism such as an LF motor 305 and an LF gear 304. The carriage 307 moves in the sub-scanning direction perpendicular to the paper feeding direction by moving the belt 311 connected to the carriage 307 by the carriage drive motor 310 while the paper is fed.

  An ink jet head 107 is mounted on the carriage 307 and is attached by a head attaching / detaching lever 308. The carriage 307 is connected to a shaft fixed to the chassis 303 by a bearing 306. Position detection that the carriage 307 has moved is performed by an encoder scale 312 and an encoder sensor 201 not shown in the figure.

  FIG. 4 is a block diagram relating to the electrical components constituting the ink jet printer.

  The encoder sensor 201 is mounted on the CR board unit 419, and the encoder sensor 201 reads the encoder scale 312 to detect the movement amount of the carriage. The encoder signal 416 output from the encoder sensor 201 is output to the main board unit 401. The inkjet head 107 is controlled to be discharged by a head drive signal 417 output from the main board unit 401 via the CR board unit 419.

  Reference numeral 402 denotes a power supply unit that supplies power used by the printer via the main board.

  A PE sensor 413 controls the supply / discharge of the printer by detecting the presence / absence of print paper.

  Reference numeral 414 denotes a PG sensor, which is a sensor for performing a recovery operation control by detecting a cam position in the recovery unit 309.

  Reference numeral 415 denotes an operation panel, which is composed of a switch and an LCD panel and performs an interface with the user.

  Reference numeral 401 denotes a main board unit, which is a PCB unit on which main electrical components for printer control are mounted. Inkjet printer controller 101, which is the main component of the printer control logic circuit, has a variety of functions on a single chip, including the inkjet head controller. It captures the signal from encoder sensor 201, detects the carriage position, A drive signal 417 is generated. Also, the PE sensor 413, the PG sensor 414, and the operation panel 415 are connected to the inkjet printer controller 101 and controlled. Although not shown in the drawing, the inkjet printer controller 101 controls the motor control circuit 403.

  The ink jet printer controller 101 is connected to a CPU 405, an I / F control circuit 408, a program ROM 409, and a RAM 410 via a bus 406. The I / F control circuit 408 controls the parallel interface 411 and the serial interface circuit 412.

  The CPU 405 controls the printer by controlling the ink jet printer controller 101 using the program ROM 409 and RAM 410.

  The motor control circuit 503 converts the signal logically processed by the inkjet printer controller 101 into drive signals for the PG motor 404, the CR motor 310, the LF motor 305, and the paper feed motor 418. The PG motor 404 is a motor that drives the recovery unit 309, the CR motor 310 is a motor that drives the carriage 307, the LF motor 305 is a motor for conveying paper, and the paper feed motor 418 is the 301 This is a motor for separating sheets one by one from the auto sheet feeder unit and delivering them to the sheet conveying means.

  FIG. 1 is a block diagram of the ejection data control in the ink jet printer controller showing the main part of the present invention.

  Reference numeral 101 denotes an inkjet printer controller which is a custom IC in which the circuit of the present invention is built.

  The print buffer controller 103 of the external SDRAM storing the print data reads the necessary data, and the data is temporarily stored in the FIFO memory 111 controlled by the 110 FIFO controller.

  The data stored in 111 is read out via the 110 FIFO controller as data for the head instructed by the print buffer controller 103 in accordance with the ejection timing of the head. After performing data processing for selecting data necessary for the nozzle row that actually ejects from the read data, the data is transferred to the head ejection data SRAM controller 104.

  Since 107 inkjet heads contain multiple heads of the same color, when accessing the same column data of the same color more than once, they are stored in 111 FIFO memory instead of from the 102 print buffer. Data will be read multiple times.

  The read data is sent to the head ejection data SRAM controller 104, temporarily stored in the head ejection data SRAM, and after fine timing adjustment according to the ejection characteristics of the head and fine timing adjustment by the mechanical mechanism, The data is read and sent to the head ejection waveform generation controller 106.

  A head ejection waveform generation controller 106 generates a head data transfer waveform and a head drive waveform in a form that matches the drive specifications of the 107 inkjet head.

  FIG. 2 is a detailed block diagram of ejection data in the inkjet printer controller showing details of FIG. Encoder pulses equivalent to 300 dpi received from 201 encoder sensors are input to the inkjet printer controller 101, and encoder pulses equivalent to 600 dpi, 1200 dpi, and 2400 dpi are generated using the encoder signal multiplier circuit 202, and then sent to the 203 encoder sequence controller. input. The encoder sequence controller 203 controls the print buffer controller 103, the FIFO controller 110, and the head discharge data SRAM controller 104 in accordance with the printer operation mode set in the mode register 204. Based on the preset print buffer read start position information, the encoder sequence controller 203 makes a data access request to the print buffer sequence controller 205. Upon receiving the request, the print buffer sequence controller 251 generates a memory address via the 252 print buffer address generation circuit, converts it into an SDRAM access waveform via the 207 SDRAM controller, and performs a burst read operation on the 102 print buffer SDRAM. . The read data read in burst is subjected to bus width conversion by the 207 SDRAM controller, expanded to a 128-bit bus, and sent to the 262 FIFO data control circuits as 512-bit data collected four times. The print buffer read sequence controller 251 sends a write request to the 261 FIFO sequence controller to create a write address to the 111 FIFO memory by the 263 FIFO address control circuit, and the data is sent via the 262 FIFO data control circuit. 111 is written. The FIFO sequence controller 261 issues a read request to the print buffer read sequence controller 251 until the predetermined amount of data is stored in the 111 memory, and the data read operation from the 102 and the data write operation to the 111 are repeatedly performed. .

  After the 111 FIFO memory has stored enough data, the 203 encoder sequence controller detects when the encoder sensor position has reached a position that takes into account the latency required for data transfer inside the controller from the predetermined print start position. From 261, an instruction to read data for a predetermined head is sent to the 261 FIFO sequence controller. In this embodiment, there are two heads for the same color, and the mounting positions of these heads are shifted by 30 columns, so the position to read from the 111 FIFO memory depends on which head is selected. It will be different. Specific instructions, such as which head data to prepare from 203 encoder sequence controller, are sent to 261 FIFO sequence controller, the required address is generated by 263 FIFO address control circuit, and the necessary data is read out. Made.

  The method of distributing the two head data of the same color will be described with reference to FIG.

  The data generation circuit 253 generates 512 bits of necessary data and transfers it to the head discharge data SRAM controller 104. The 210 sequence controller inside the 104 head ejection data SRAM controller operates at the timing determined by the encoder sequence controller 203 and the print buffer sequence controller 205, and from the data generation circuit 208 via the 211 write control circuit. The received data is stored in accordance with the format of 105 head ejection data SRAM via the 212 bus controller. Further, the read controller circuit 213 is activated by the sequence controller 210 and reads data from the head ejection data SRAM 105 via the 212 bus controller.

  The 212 bus controller performs bus arbitration for the head ejection data SRAM 105 of the 211 write control circuit and the 213 read control circuit. The data read out by the read control circuit 213 is converted into a serial transmission waveform conforming to the specifications of the 107 4-color double inkjet head by the 220 head ejection waveform generation controller and transmitted. 107 four-color double inkjet heads have 240 yellow head 1, 241 yellow head 2, 242 magenta head 1, 243 magenta head 2, 244 cyan head 1, 245 cyan head 2, 246 black head 1 and The 247 black heads 2 consist of 8 heads, 2 each for 4 colors, and drive waveforms are supplied to each head.

  FIG. 5 is a diagram illustrating a detailed block configuration of ejection data control in a conventional inkjet printer controller.

  Compared to Fig. 2, the head has been changed and the 510 four-color inkjet head is used, 501 yellow head, 502 magenta head, 503 cyan head and 504 BK head 4 It consists of a total of four heads, one for each color. In addition, since there is no 110 FIFO controller or 111 FIFO memory, the data read from the 107 SDRAM is directly sent to the 104 head ejection data SRAM controller.

  FIG. 6 is a diagram showing a printing image of four colors and four heads in a conventional example. 510 is a four-color inkjet head, and 601 is printing paper. The nozzle position when the ink jet head is seen through from above is as shown in the figure. The nozzle 605 belongs to block 23 and the nozzle 606 belongs to block 0. The interior of the 510 ink-jet head has a nozzle arrangement belonging to the same block every 24 nozzles. Reference numeral 604 denotes a carriage operation direction, and 510 head moves from left to right on 601 printing paper.

  Since the nozzle position is shifted for each block, after ejecting the nozzle of block 0, the 510 inkjet head is moved to the right, then the nozzle of block 1 is ejected. Is driven, the print result is printed in a straight line like the print data of the first column 602. 603 is the printing result of the second column moved by 1/600 inch of 618. The one-column printing of 602 and 603 is the result of discharging all the upper 24 dots of 501 Y heads. In the main scanning direction, the head nozzle arrangement resolution 600 dpi is directly connected to the printing result, and the distance between 616 dots is 1/600 inch.

  In the inkjet head 510, 501 indicates a Y head, 502 indicates an M head, 503 indicates a C head, and 504 indicates a BK head. 620 indicates the distance between each head. In this embodiment, the head is shifted by 60 columns at 2.54 mm, that is, 600 dpi, and the printing of each head is overwritten in the order of BK, Y, M, and C by shifting 60 columns. Color printing is realized by lapping.

  FIG. 7 is a view showing a printing image using the four-color 8-head used in this embodiment.

  107 is a four-color double inkjet head, and 701 is printing paper. The nozzle position when the ink jet head is seen through from above is as shown in the figure. The nozzle configuration inside each head is the same as in FIG. The nozzle 705 belongs to block 23 and the nozzle 706 belongs to block 1. The 707 nozzle belongs to block 22 and the 708 nozzle belongs to block 0. The inside of the ink jet head 107 has a nozzle arrangement belonging to the same block every 24 nozzles. Reference numeral 704 denotes a carriage operation direction, and 107 head moves from left to right on 701 printing paper.

  Since the nozzle position is shifted for each block, after ejecting the nozzle in block 0, move the 107 inkjet head to the right, and then eject the nozzle in block 1, then 24 blocks in time order. Is driven, the print result is printed in a straight line like the print data in the first column 702.

  In the inkjet head 107, 240 indicates a Y1 head, 241 indicates a Y1 head, 242 indicates an M1 head, 243 indicates an M2 head, 244 indicates a C1 head, 245 indicates a C2 head, 246 indicates a BK1 head, and 247 indicates a BK2 head. 720 indicates the distance between the heads. In this embodiment, the distance is 30 columns at 1.27 mm, that is, 600 dpi, and is shifted by 30 columns in the order of BK2, BK1, C2, C1, M2, M1, Y2, Y1. In this way, color printing is realized by overlapping printing.

  For 702 1 column printing, 241 Y2 head upper 24 dots even block, total 12 blocks are ejected, then 30 column carriage moves to the right, 240 Y1 head upper 24 dots odd block This is the result of discharging a total of 12 blocks. In the main scanning direction, 240 head nozzle arrangement resolution 600 dpi is directly connected to the printing result, and the distance between 716 dots is 1/600 inch.

  FIG. 8 is an output waveform diagram of 24 block division driving in the conventional example.

  840 is a voltage axis, and 841 is a time axis.

  Reference numeral 801 denotes a 300-dpi A-phase encoder pulse input from the encoder sensor 201. Similarly, 802 is a B-phase encoder pulse. Reference numeral 803 denotes a pulse width required for the carriage to move a distance of 300 dpi. Carriage is 25inch / sec. When moving at a speed of 133 seconds, it takes 133us. Reference numeral 804 denotes a trigger waveform for every 300 dpi created from 801 encoder A phase waveforms. Reference numeral 805 denotes a trigger waveform having a 600 dpi period generated by the encoder signal multiplication circuit 202. Reference numeral 806 is an enlarged view of a trigger waveform having a 600 dpi period of 805, and T1 of 807 indicates a pulse width corresponding to 600 dpi.

  Reference numeral 808 denotes a block trigger waveform for driving a pulse width equivalent to 600 dpi by 24, 809 denotes a heat pulse waveform, 810 denotes a heat pulse for block 1, and 811 denotes a heat pulse for block 2.

  820 is a latch pulse waveform for latching serially transferred data, 821 is a block 1 latch pulse, and 822 is a block 2 latch pulse.

  830 is a serial clock waveform, 834 is a serial data waveform 1, 835 is a serial data waveform 2, 832 is data in block 2, and 833 is data in block 3.

  Data required for driving each block of each color is 32 bits, of which 27 bits are used for print data and the remaining 5 bits are used for block instruction. And 835 are divided into two data lines for output.

  FIG. 9 is an output waveform diagram of 24 block division driving in the present embodiment.

  T2 of 903 indicates a pulse width equivalent to 600 dpi.

  908 is a block trigger waveform for dividing and driving a pulse width equivalent to 600 dpi, but it is an even number 12 block that is an ejection block of 901 Y2 head and an odd number 12 block that is an ejection block of 902 Y1 head In this way, since the two heads drive half by half, only 12 pulses are output.

  909 is a heat pulse waveform, 910 is a heat pulse of blocks 2 and 3, and 811 is a heat pulse of blocks 4 and 5.

  920 is a latch pulse waveform for latching serially transferred data, 921 is a latch pulse of blocks 2 and 3, and 922 is a latch pulse of blocks 4 and 5.

  930 is a serial clock waveform, 934 is a serial data waveform 1, 935 is a serial data waveform 2, 932 is data in blocks 4 and 5, and 933 is data in blocks 6 and 7.

  The data to which each block of each color belongs is 32 bits, of which 27 bits are used for print data and the remaining 5 bits are used for block instruction. Are divided into two data lines for output.

  As can be seen from the comparison with the conventional example in Fig. 8, the block trigger signal at 908 can be reduced from 24 pulses to 12 pulses by increasing the number of heads of the same color to two, realizing about double the speed is doing.

  FIG. 10 is a control output waveform diagram when the four-color head is driven in the conventional example. The x-axis at 1070 indicates time. Reference numeral 1001 denotes the use state of the print buffer. The period designated as 1002 is the access state of the print buffer, and the period indicated by 1003 is the state without access. In this figure, it is assumed that only the print buffer controller 103 is assumed to access the print buffer, and there is a sufficient margin for accessing the print buffer.

  Specifically, 1004 is the data read for HSRAM write of n column Y, 1005 is the data read for M HSRAM write of n column, 1006 is the data read for HSRAM write of n column C, 1007 is n column BK shows the data read access period for HSRAM write. The data read from the print buffer is processed by the print buffer controller 103 and then written to the head discharge data SRAM 105 by the head discharge data SRAM controller (hereinafter referred to as HSRAMC) 104. 1010 is the Y data write transfer waveform to HSRAMC, 1011 is the Y data write transfer to HSRAMC of n columns, 1014 is the M data write transfer to HSRAMC, and 1015 is the M data write transfer to HSRAMC of n columns , 1018 is C data write transfer to HSRAMC, 1019 is C data write transfer to n-column HSRAMC, 1020 is BK data write transfer to HSRAMC, and 1021 is BK data write transfer to n-column HSRAMC Is shown.

  Reference numeral 1030 denotes Y data read transfer from HSRAMC, and reference numeral 1031 denotes Y data read transfer from HSRAMC of the n-2 column, and 24 read transfers of all 24 blocks in this period. 1034 is M data read transfer from HSRAMC, and 1035 is M data read transfer from HSRAMC of n-2 column. 1038 is C data read transfer from HSRAMC, and 1039 is C data read transfer from HSRAMC of n-2 column. 1040 is BK data read transfer from HSRAMC, and 1041 is BK data read transfer from HSRAMC of n-2 column.

  Reference numeral 1050 indicates serial transfer to the head, which is a waveform obtained by converting the data received by the read data transfer from the HSRAMC of 1030, 1034, 1038, and 1040 into serial data and outputting it in accordance with the specifications of the head. 1051 indicates serial transfer to the head of the n-2 column, and data transfer of all 24 blocks for four colors is collectively displayed. Reference numeral 1052 denotes a period in which the transfer state is indicated, and reference numeral 1053 denotes a period in which no transfer is performed.

  A head heat signal 1060 is a signal for heating the data received at 1050. Reference numeral 1061 denotes a heat signal of the n-2 column head. Actually, 24 pulses corresponding to 24 blocks are included.

  FIG. 11 is a diagram illustrating in detail the control of the FIFO controller 110 and the FIFO memory 111 in FIG. 2 using a block diagram.

  The encoder sequence controller 203 makes a data access request to the print buffer sequence controller 205 based on the multiplied encoder signal. Upon receiving the request, the print buffer sequence controller 251 generates a memory address via the 252 print buffer address generation circuit, converts it into an SDRAM access waveform by the 207 SDRAM controller, and performs a burst read operation on the 102 print buffer SDRAM. The read data that has been burst read is subjected to bus width conversion by the 207 SDRAM controller, expanded to a 128-bit bus, and sent to the FIFO write data control circuit 1103 as 512-bit data collected four times. The print buffer read sequence controller 251 sends a write request to the 261 FIFO sequence controller, that is, requests 111 FIFO memory write access rights from the 1112 FIFO access arbiter. When the 1112 FIFO access arbiter authorizes write access, the internal 1111 FIFO data remaining amount control circuit counts down the remaining amount by 1, outputs 1113 FIFO R / W trigger, and 263 FIFO address circuit The FIFO write pointer control circuit that manages the write address of the internal 1114 creates the write address and creates the memory address signal of 1120, and outputs the 1104 of the output from the FIFO write data control circuit of the 1103 Write data to 111 FIFO memory.

  The bit configuration of 111 FIFO memory is 512 addresses X128 bits, and ejection data of other colors ejected simultaneously with the ejection timing of 240 Y1 heads are collectively managed and stored. Reference numeral 1140 denotes a data area in which the Y1 head has n-30 columns. Reference numeral 1141 denotes an area in which Y1 discharges BK data simultaneously discharged to the n-30 column, and stores 512-bit data of 4 words X128 bits from X0h to X3h. Similarly, 1142 is an area in which C data Y1 discharges simultaneously to the n-30 column is stored, and 512-bit data of 4 words X128 bits from X4h to X7h is stored. Reference numeral 1143 denotes an area in which M data that Y1 discharges simultaneously to the n-30 column is stored, and 512-bit data of 4 words X128 bits from X8h to XBh is stored. Reference numeral 1144 denotes an area in which Y1 data to be discharged to the n-30 column is stored, and 512-bit data of 4 words X128 bits from XCh to XFh is stored. The value X in the upper address is a value that the 1114 FIFO write pointer control circuit sequentially updates in response to access to the 111 FIFO memory.

  Similarly, 1131 is the data in the (n + 5) th column. Strictly speaking, it is data for four colors discharged simultaneously when the Y1 head is in the (n + 5) th column. Similarly, the Y1 head is n + 4, 1132 is n + 3, 1133 is n + 2, 1134 is n + 1, 1135 is n + 1, 1135 is n-1 and 1136 is data in the (n-1) th column.

  The 261 FIFO sequence controller sends a read request by sending an 1110 FIFO empty flag to the 251 print buffer read sequence controller until a predetermined amount of data is stored in the 111 FIFO memory, reading data from 102, The data write operation to 111 is repeatedly performed.

  After the 111 FIFO memories have stored enough data, the 203 encoder sequence controller places 1106 ejection triggers for each head into the 261 FIFO sequence controller. Based on the trigger, when the 1112 FIFO access arbiter permits read access, the value of the 1111 FIFO data remaining amount control circuit is decremented by 1, and the 1113 FIFO R / W trigger is output to the 263 FIFO address control circuit. To do. The read pointer control circuit 1115 outputs the address where the requested ejection data of the head is stored to the FIFO memory 111, and read access is performed.

  Here, there are two heads for the same color, and the mounting position of these heads is shifted by 30 columns, so the address position read from the FIFO memory of 111 differs depending on which head triggers. Become.

  The FIFO read data 1121 is stored in the read data control circuit 1104 and sent to the 253 data generation circuit in the print buffer controller 103. Data is distributed to valid data using 254 data distribution masks. There are two heads of the same color, and the method of distributing data to each head is determined in advance by 254 data distribution masks. By ANDing the read data and the mask data, Only the selected data is sent to the head ejection data SRAM controller 104. The 254 data distribution masks are created so that 100% printing is performed with two heads. By giving the sorting mask randomness, printing with reduced printing unevenness is possible. In addition, when the purpose of high-speed printing described in this embodiment is to store data in the head ejection data SRAM 104 by the 104 head ejection data SRAM controller without using the 254 data distribution masks. It is possible to substitute by storing only the data of the block necessary for. Specifically, as described with reference to FIG. 9, this is a method of driving 24 division driving by two heads by 12 divisions, and shows that 12 blocks of data to be ejected are selected and stored.

  FIG. 12 is a detailed block diagram of ejection data control in an ink jet printer controller in which 107 four-color double ink jet heads are connected to the conventional example shown in FIG.

  By increasing the number of heads to be controlled with respect to FIG. 5, it is possible to drive eight heads.

  FIG. 13 is a control output waveform diagram during driving when a four-color double inkjet head is connected to the conventional example shown in FIG. The x-axis at 1070 indicates time. Reference numeral 1301 denotes the use state of the print buffer. The period indicated by 1302 is the access state of the print buffer, and the period indicated by 1303 is a state without access. As shown in the figure, in this example, the period of no access 1303 is almost zero. In this figure, it is assumed that only the print buffer controller 103 is assumed to access the print buffer, and there is still no room for access to the print buffer.

  Specifically, 1370 is the data read for HSRAM write of Y column in Y1, 1371 is the data read for HSRAM write of Y2 in n column, 1372 is the data read for HSRAM write of M1 in N column, 1373 is n column M2 data read for HSRAM write, 1374 data read for n-column C1 HSRAM write, 1375 data read for n-column C2 HSRAM write, 1376 data for n-column BK1 HSRAM write Read, 1377 indicates the access period of the data read for HSRAM write of BK2 of n column. The data read from the print buffer is processed by the print buffer controller 103 and then written to the head discharge data SRAM 105 by the head discharge data SRAM controller (hereinafter referred to as HSRAMC) 104. Reference numeral 1310 denotes a Y1 data write transfer waveform to HSRAMC, and reference numeral 1311 denotes a Y1 data write transfer to the n-column HSRAMC. 1312 is a Y2 data write transfer waveform to HSRAMC, and 1313 is a Y2 data write transfer to n-column HSRAMC. Reference numeral 1314 denotes an M1 data write transfer waveform to HSRAMC, and reference numeral 1315 denotes an M1 data write transfer to the n-column HSRAMC. Reference numeral 1316 denotes an M2 data write transfer waveform to HSRAMC, and reference numeral 1317 denotes an M2 data write transfer to the n-column HSRAMC. Reference numeral 1318 denotes a C1 data write transfer waveform to HSRAMC, and reference numeral 1319 denotes C1 data write transfer to the n-column HSRAMC. Reference numeral 1320 denotes a C2 data write transfer waveform to HSRAMC, and 1321 denotes C2 data write transfer to an n-column HSRAMC. 1322 is a BK1 data write transfer waveform to HSRAMC, and 1323 is a BK1 data write transfer to n-column HSRAMC. Reference numeral 1324 denotes a BK2 data write transfer waveform to HSRAMC, and reference numeral 1325 denotes BK2 data write transfer to the n-column HSRAMC.

  1330 shows Y1 and Y2 data read transfer from HSRAMC, and 1331 is Y1 and Y2 data read transfer from HSRAMC of n-2 column, and 24 read transfers for 24 blocks in total with 2 heads during this period. Is shown. 1334 shows M1 and M2 data read transfer from HSRAMC, 1335 M1 and M2 data read transfer from HSRAMC of n-2 column, and 24 read transfers for 24 blocks in total with two heads during this period Is shown. 1338 shows C1 and C2 data read transfer from HSRAMC, 1339 is C1 and C2 data read transfer from HSRAMC of n-2 column, and 24 read transfers for 24 blocks in total with 2 heads during this period Is shown. 1340 shows BK1 and BK2 data read transfer from HSRAMC, 1341 is BK1 and BK2 data read transfer from HSRAMC in n-2 column, and 24 read transfers for 24 blocks in total with 2 heads during this period Is shown. 1350 indicates serial transfer to the head, which is head serial transfer that converts data prepared by read data transfer from HSRAMC of 1330, 1334, 1338, and 1340 into serial data and outputs it according to the specifications of the head . 1051 shows the serial transfer to the head of the n-2 column, and all the data transfers for 4 colors and 8 heads are displayed together. Reference numeral 1352 denotes a period in which the transfer state is indicated, and reference numeral 1353 denotes a period in which no transfer is performed.

  1360 is a head heat signal for heating the data received at 1350. Reference numeral 1361 denotes a heat signal of the n-2 column head. Actually, 12 pulses corresponding to 12 blocks are included for each head.

  FIG. 14 is a control output waveform diagram of the embodiment of the present invention shown in FIG. The x-axis at 1070 indicates time. Reference numeral 1401 denotes the use state of the print buffer. The period indicated by 1402 is the access state of the print buffer, and the period indicated by 1403 is a state without access. In this example, because it has 110 FIFO controllers, for example, Y1 head and Y2 head data access is only for data access of Y2 head that is ejected first, and Y1 head data access. Will use the data stored in the FIFO during Y2 head access. Therefore, the access to the print buffer is halved compared to the access of the conventional example shown in FIG. 13, and the period of no access 1403 is a sufficient time as in FIG.

  Specifically, 1470 is data read for HS2 write of Y2 in n + 5 column, 1471 is data read for HS2 write of M2 in n + 5 column, 1472 is data for HSRAM write of C2 in n + 5 column Read, 1473 indicates a data read access period for HSRAM write of BK2 of n + 5 column. Here, the n + 5 column data is being accessed because it has a FIFO area for ensuring 1101 memory access margin.

  The data read from the print buffer is sent to the 110 FIFO controller and stored in the 111 FIFO memory. After that, the head column data necessary for ink ejection is read from the FIFO memory, and written in 105 head ejection data SRAM by 104 head ejection data SRAM controller (hereinafter, HSRAMC).

  1410 is a Y1 data write transfer waveform to HSRAMC, and 1411 is a Y1 data write transfer to HSRAMC of n-30 column data read from 111 FIFO memory. 1412 is a Y2 data write transfer waveform to HSRAMC, and 1413 is a Y2 data write transfer to HSRAMC of n-column data read from 111 FIFO memory. 1414 is an M1 data write transfer waveform to HSRAMC, and 1415 is an M1 data write transfer to HSRAMC of n-30 column data read from 111 FIFO memory. Reference numeral 1416 denotes an M2 data write transfer waveform to HSRAMC, and reference numeral 1417 denotes an M2 data write transfer to HSRAMC of n-column data read from the 111 FIFO memory. 1418 is a C1 data write transfer waveform to HSRAMC, and 1419 is a C1 data write transfer to HSRAMC of n-30 column data read from the 111 FIFO memory. 1420 is a C2 data write transfer waveform to HSRAMC, and 1421 is a C2 data write transfer to HSRAMC of n-column data read from 111 FIFO memory. Reference numeral 1422 denotes a BK1 data write transfer waveform to HSRAMC, and 1423 denotes BK1 data write transfer to the HSRAMC of n-30 column data read from the 111 FIFO memory. Reference numeral 1424 denotes a BK2 data write transfer waveform to HSRAMC, and reference numeral 1425 denotes BK2 data write transfer to the HSRAMC of n-column data read from the 111 FIFO memory.

  After the data read transfer to HSRAMC, it is exactly the same as the description of FIG. 1330 shows Y1 and Y2 data read transfer from HSRAMC, and 1331 is Y1 and Y2 data read transfer from HSRAMC of n-2 column, and 24 read transfers for 24 blocks in total with 2 heads during this period. Is shown. 1334 shows M1 and M2 data read transfer from HSRAMC, 1335 M1 and M2 data read transfer from HSRAMC of n-2 column, and 24 read transfers for 24 blocks in total with two heads during this period Is shown. 1338 shows C1 and C2 data read transfer from HSRAMC, 1339 is C1 and C2 data read transfer from HSRAMC of n-2 column, and 24 read transfers for 24 blocks in total with 2 heads during this period Is shown. 1340 shows BK1 and BK2 data read transfer from HSRAMC, 1341 is BK1 and BK2 data read transfer from HSRAMC in n-2 column, and 24 read transfers for 24 blocks in total with 2 heads during this period Is shown. 1350 indicates serial transfer to the head, which is head serial transfer that converts data prepared by read data transfer from HSRAMC of 1330, 1334, 1338, and 1340 into serial data and outputs it according to the specifications of the head . 1051 shows the serial transfer to the head of the n-2 column, and all the data transfers for 4 colors and 8 heads are displayed together. Reference numeral 1352 denotes a period in which the transfer state is indicated, and reference numeral 1353 denotes a period in which no transfer is performed.

  1360 is a head heat signal for heating the data received at 1350. Reference numeral 1361 denotes a heat signal of the n-2 column head. Actually, 12 pulses corresponding to 12 blocks are included for each head.

The block diagram of the ejection data control in the ink jet printer controller showing the main part in the embodiment of the present invention. FIG. 2 is a detailed block configuration diagram of ejection data control in an ink jet printer controller showing a main part in an embodiment of the present invention. FIG. 2 is an overview of a printer unit according to an embodiment of the present invention. 1 is a block diagram relating to main electrical components of an inkjet printer according to an embodiment of the present invention. FIG. 10 is a detailed block diagram of ejection data control in an inkjet printer controller in a conventional example. The figure which showed the printing image of 4 colors 4 heads in a prior art example. The figure which showed the printing image of 4 colors 8 heads in embodiment of this invention. The output waveform figure of 24 block division drive in a prior art example. The output waveform figure of 24 block division drive in an embodiment of the invention. The control output waveform figure at the time of 4 color head drive in a prior art example. The detailed block diagram regarding control of the FIFO controller and FIFO memory in embodiment of this invention. FIG. 5 is a block diagram of a detailed discharge data control block in an inkjet printer controller in which a four-color double inkjet head is connected to the conventional example in the embodiment of the present invention. FIG. 7 is a control output waveform diagram during driving when a four-color double inkjet head is connected to the conventional example in the embodiment of the present invention. The control output waveform diagram in the embodiment of the present invention.

Explanation of symbols

101 Inkjet printer controller
102 Print buffer
103 Print buffer controller
104 SRAM controller for head ejection data
105 Head ejection data SRAM
106 Head ejection waveform generator controller
107 Inkjet head
110 FIFO controller
102 FIFO memory
201 Encoder sensor
202 Encoder signal multiplier
203 Encoder sequence controller
204 Mode register
207 SDRAM controller
210 Sequence controller
211 Light control circuit
212 Bus controller
213 Read control circuit
220 Head discharge waveform generation controller
240 Y1 head
241 Y2 head
242 M1 head
243 M2 head
244 C1 head
245 C2 head
246 BK1 head
247 BK2 head
251 Print buffer read sequence controller
252 Address generation circuit
253 Data generation circuit
254 Data distribution mask
261 FIFO sequence controller
262 FIFO data control circuit
263 FIFO address control circuit
301 Auto sheet feeder unit
303 chassis
304 LF gear
305 LF motor
306 bearing
307 Carriage
308 Head release lever
309 Recovery Unit
310 Carriage drive motor
311 belt
312 Encoder scale
401 Main board unit
402 Power supply unit
403 Motor control circuit
404 PG motor
405 CPU
406 Internal bus
408 I / F control circuit
409 Program ROM
410 RAM
411 Parallel interface
412 Serial interface
413 PE sensor
414 PG sensor
415 Operation panel
416 Encoder signal
417 Head drive signal
418 Paper feed motor
419 CR board unit
501 Y head
502 M head
503 C head
504 BK head
510 inkjet head
520 Data generation circuit
601 printing paper
602 First column print data
603 Second column print data
604 Carriage direction
605 Nozzle of block 23
606 Nozzle of block 0
616 1 / 600inch
618 1 / 600inch
620 Distance between each head
701 printing paper
702 Print data for the first column
704 Carriage movement direction
705 Nozzle of block 23
706 nozzle of block 1
707 Nozzle of block 22
708 Nozzle of block 0
716 1 / 600inch
720 Y1 head and Y2 head distance (1.27mm)
801 Encoder A phase
802 Encoder B phase
803 300dpi equivalent pulse width
804 300dpi trigger waveform
805 Trigger waveform with 600dpi period
806 Enlarged view of trigger waveform with 600dpi period
807 T1 (pulse width equivalent to 600 dpi)
808 Block trigger waveform
809 Heat pulse waveform
810 Block 1 heat pulse
811 Block 2 heat pulse
820 Latch pulse waveform
821 Block 1 latch pulse
822 Block 2 latch pulse
830 Serial clock waveform
832 Block 2 data
833 Block 3 data
834 Serial data waveform 1
835 Serial data waveform 2
840 voltage axis
841 Time axis
901 Encoder A phase
902 Encoder B phase
903 hours T2 (pulse width equivalent to 600dpi)
908 Block trigger waveform
909 Heat pulse waveform
910 Block 1 heat pulse
911 Block 2 heat pulse
920 Latch pulse waveform
921 Block 1 latch pulse
922 Block 2 latch pulse
930 Serial clock waveform
932 Data of block 2
933 Block 3 data
934 Serial data waveform 1
935 Serial data waveform 2
1001 Print buffer usage
1002 Access status
1003 No access
1004 Data read for n column Y HSRAM write
Data read for 1005 n column M HSRAM write
Data read for 1006 n column C HSRAM write
1007 n column BK data read for HSRAM write
1010 Y data write transfer to HSRAMC
1011 Y data write transfer to HSRAMC with n columns
1014 M data write transfer to HSRAMC
1015 M data write transfer to n-column HSRAMC
1018 C data write transfer to HSRAMC
1019 C data write transfer to n-column HSRAMC
BK data write transfer to 1020 HSRAMC
BK data write transfer to 1021 n-column HSRAMC
1030 Y data read transfer from HSRAMC
1031 Y data read transfer from HSRAMC of n-2 column
1034 M data read transfer from HSRAMC
1035 M data read transfer from HSRAMC of n-2 column
1038 C data read transfer from HSRAMC
1039 C data read transfer from HSRAMC of n-2 column
1040 BK data read transfer from HSRAMC
1041 BK data read transfer from HSRAMC of n-2 column
Serial transfer to 1050 head
1051 Serial transfer to n-2 column head
1052 Transfer status
1053 No transfer
1060 Head heat signal
1061 n-2 column head heat signal
1070 time axis
1101 Print buffer access enable
1102 Print buffer read data
1103 FIFO write data control circuit
1104 FIFO read data control circuit
1105 FIFO write data
1106 Head ejection trigger
1110 FIFO empty flag
1111 FIFO data remaining amount control circuit
1112 FIFO access arbiter
1113 FIFO R / W trigger,
1114 FIFO write pointer control circuit
1115 FIFO read pointer control circuit
1120 FIFO address
1121 FIFO read data
1131 n + 5 column data
1132 n + 4 column data
1133 n + 3 column data
1134 n + 2 column data
1135 n + 1 column data
1136 n columns of data
1137 n + 5 column data
1140 n-30 column data area
1141 K data area
1142 C data area
1143 M data area
1144 Y data area
1301 Print buffer usage
1302 Access status
1303 No access
1310 Y1 data write transfer to HSRAMC
1311 Y1 data write transfer to HSRAMC with n columns
1312 Y2 data write transfer to HSRAMC
1313 Y2 data write transfer to HSRAMC with n columns
1314 M1 data write transfer to HSRAMC
1315 M1 data write transfer to n-column HSRAMC
1316 M2 data write transfer to HSRAMC
1317 M2 data write transfer to n-column HSRAMC
1318 C1 data write transfer to HSRAMC
1319 C1 data write transfer to n-column HSRAMC
1320 C2 data write transfer to HSRAMC
1321 C2 data write transfer to n-column HSRAMC
1322 BK1 data write transfer to HSRAMC
BK1 data write transfer to 1323 n-column HSRAMC
1324 BK1 data write transfer to HSRAMC
BK1 data write transfer to 1325 n-column HSRAMC
1330 Y1, Y2 data read transfer from HSRAMC
1331 Y1, Y2 data read transfer from HSRAMC of n-2 column
1334 M1, M2 data read transfer from HSRAMC
1335 M-2 data read transfer from HSRAMC in n-2 column
1338 C1, C2 data read transfer from HSRAMC
1339 C1, C2 data read transfer from HSRAMC of n-2 column
1340 BK1, BK2 data read transfer from HSRAMC
BK1, BK2 data read transfer from 1341 n-2 column HSRAMC
Serial transfer to 1350 head
1351 Serial transfer to n-2 column head
1352 Transfer status
1353 No transfer
1360 head heat signal
1361 n-2 column head heat signal
1370 n column Y1 data read for HSRAM write
1371 Data read for n-column Y2 HSRAM write
1372 Data read for n-column M1 HSRAM write
1373 Data read for n-column M2 HSRAM write
1374 Data read for n-column C1 HSRAM write
Data read for 1375 n-column C2 HSRAM write
1376 n-column BK1 HSRAM write data read
1377 Data read for n-column BK2 HSRAM write
1401 Print buffer usage
1402 Access status
1403 No access
1410 Y1 data write transfer to HSRAMC
1411 Y1 data write transfer of n2 column data of Y2 in FIFO to HSRAMC
1412 Y2 data write transfer to HSRAMC
1413 Y2 data write transfer to HSRAMC with n columns
1414 M1 data write transfer to HSRAMC
1415 M1 data write transfer of M2 n-30 column data in FIFO to HSRAMC
1416 M2 data write transfer to HSRAMC
1417 M2 data write transfer to HSRAMC with n columns
1418 C1 data write transfer to HSRAMC
1419 Write C1 data write to HSRAMC of C2 n-30 column data in FIFO
1420 C2 data write transfer to HSRAMC
1421 C2 data write transfer to HSRAMC with n columns
1422 BK1 data write transfer to HSRAMC
1423 BK1 data write transfer of n-30 column data of BK2 in FIFO to HSRAMC
1424 BK1 data write transfer to HSRAMC
BK1 data write transfer to 1425 n-column HSRAMC
1470 n column data read for Y2 HSRAM write
1471 n-column data read for M2 HSRAM write
1472 Data read for n-column C2 HSRAM write
1473 n column BK2 HSRAM write data read

Claims (1)

In a configuration in which an image is formed by a print medium conveying means and an inkjet head scanning and moving the print medium, the inkjet head receives data divided into block units that simultaneously eject multiple nozzles for one column, and after receiving the data In an inkjet printer having a structure in which energy is applied by a drive pulse and ink is ejected,
Having multiple inkjet nozzle rows of the same color
First storage means for storing inkjet head ejection data;
Second storage means for reading out data from the first storage means and storing data for a plurality of columns for ejection;
Position detecting means for detecting head position information;
Based on the information from the position detection means, data is read from the second storage means,
Means for generating a discharge drive waveform to the head;
The data for the plurality of inkjet nozzle rows is repeatedly read from the second storage unit.

Images