JP2006108490A - Semiconductor device including mim capacitor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device whereby an upper layer conductive film connects a MIM capacitor to a lower layer conductor without incurring the breakage of the upper layer conductive film and preventing the upper layer conductive film from having high resistance. <P>SOLUTION: The MIM capacitor CAP including a lower electrode 5, a capacitor dielectric film 6, and an upper electrode 7 is formed on a multilayer wire on a semiconductor substrate 1. An interlayer insulating film 8 and upper conductive films 9A, 9B are laminated thereon. A lower electrode 5 or an upper electrode 7 or both of them of the MIM capacitor CAP are provided with extension parts 5B, 7B extended outwardly from an effective capacitor to the upper part of either of embedded copper wires, that is, either of first and second lower conductors 3A, 3B. Either of tips of extensions 5B, 7B is connected to either of the embedded copper wires 3A and 3B in an opening 8A or 8B formed at the inter-layer insulating film 8 by the upper conductive film 9A or 9B. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having an MIM type capacitor including a lower electrode, a capacitor dielectric film, and an upper electrode in a stacked portion on a semiconductor substrate, and a method for manufacturing the same.

MIM type capacitors are widely used because large capacity capacitors can be manufactured by a relatively simple process.
In the conventional semiconductor laminated portion, a plug is formed on each of the upper electrode and the lower electrode of the MIM type capacitor, and once connected to the upper layer wiring, it is applied to an element such as a lower layer wiring or a transistor than the MIM type capacitor. It has been common to connect.

  As a lower layer wiring connected to the MIM type capacitor, for example, a buried copper wiring can be cited. The connection between the MIM type capacitor and the embedded copper wiring will be described below.

In the CMOS semiconductor process that is the mainstream of LSI, aluminum wiring is used up to its minimum dimension, for example, contact node diameter up to 180 nm. After forming the aluminum wiring, an interlayer insulating film is deposited, and the surface is chemically and mechanically polished. A wiring formation method that is smoothed by CMP (hereinafter, CMP) or the like has been adopted.
However, the contact node diameter has become 130 nm or less, and in order to suppress signal delay due to wiring, it has become the mainstream to adopt a buried copper wiring process in recent LSI wiring structures.

The buried copper wiring process is a method of burying copper in the groove dug in the interlayer insulating film by digging a groove in the interlayer insulating film, forming copper by plating, and etching the copper by CMP or the like.
In the case of the buried copper wiring process, all the wirings and plugs formed in each interlayer insulating film are formed by a method of burying a conductive material in a groove or a through hole formed in the interlayer insulating film. Therefore, the process for forming a MIM type capacitor that requires patterning by etching the conductive layer sandwiching the capacitor dielectric film differs from the embedded copper wiring structure and the basic patterning method for forming the conductive layer, From this point of view, the process consistency is poor.

  When it is necessary to form an MIM type capacitor, if a MIM type capacitor is formed on a multilayer wiring portion formed by a buried copper wiring, the consistency with the buried copper wiring process is good. In an LSI using a normal buried copper wiring process, an interlayer insulating film is formed on the uppermost buried copper wiring, and a pad for wire bonding is formed thereon with aluminum alloy wiring. In the case of this structure, it is common to connect the uppermost buried copper wiring and the MIM capacitor by an aluminum alloy wiring for pads.

  6 (A) to 9 (B) are cross-sectional views of the semiconductor device in each process when forming an MIM type capacitor on the multilayer wiring portion of the embedded copper wiring as a related technique of the present invention.

  As shown in FIG. 6A, a multilayer wiring portion is formed on a silicon substrate 101, and buried copper wirings 103A and 103B are formed in the uppermost interlayer insulating film. The surfaces of the interlayer insulating film 102 and the embedded copper wirings 103A and 103B are covered with a copper diffusion preventing film 104. In FIG. 6A, wirings, transistors and the like below the uppermost buried copper wirings 103A and 103B are not shown.

  When forming an MIM type capacitor on this, as shown in FIG. 6B, a titanium nitride film 105A to be a lower electrode of the MIM type capacitor is formed to about 200 nm by sputtering, for example. On the titanium nitride film 105A, a silicon nitride film 106A serving as a dielectric of the MIM type capacitor is formed with a thickness of about 50 nm, for example, by plasma enhanced CVD (hereinafter referred to as PECVD). On the silicon nitride film 106A, a titanium nitride film 107A to be an upper electrode of the MIM type capacitor is formed with a thickness of about 100 nm by, for example, sputtering.

  For example, a photoresist is patterned, and the titanium nitride film 107A is dry-etched using this as a mask. When the photoresist is removed, the upper electrode 107 of the MIM capacitor is formed as shown in FIG.

  For example, a photoresist is patterned, and the silicon nitride film 106A and the titanium nitride film 107A are sequentially dry-etched using the photoresist as a mask. When the photoresist is removed, as shown in FIG. 7B, the capacitor dielectric film 106 and the lower electrode 105 of the MIM type capacitor are formed, and the basic structure of the MIM type capacitor CAP is completed.

  As shown in FIG. 8A, a silicon oxide film is formed to a thickness of about 700 nm as the interlayer insulating film 108 in which the formed MIM type capacitor is embedded, for example, by PECVD.

  For example, a photoresist is patterned, and using this as a mask, the interlayer insulating film (silicon oxide film) 108 and the two silicon nitride films (capacitor dielectric film 106 and copper diffusion prevention film 104) are dry-etched. When the photoresist is removed, four contact holes 108A, 108B, 108C, and 108D are formed as shown in FIG. 8B. Since the contact holes 108A and 108B are formed in the interlayer insulating film 108 and the copper diffusion prevention film 104, the buried copper wirings 103A and 103B are exposed. The upper electrode 107 is exposed by forming the contact hole 108C in the interlayer insulating film 108, and the lower electrode 105 is exposed by forming the contact hole 108D in the interlayer insulating film 108 and the capacitor dielectric film 106. Yes.

  As shown in FIG. 9A, a pad aluminum alloy 109C that completely embeds these four contact holes is formed to a thickness of about 1000 nm by sputtering, for example.

For example, a photoresist is patterned, and the pad aluminum alloy 109C is dry-etched using this as a mask. As a result, as shown in FIG. 9B, an aluminum alloy layer 109A for connecting the upper electrode 107 of the MIM capacitor and the buried copper wiring (lower conductor) 103A through the contact holes 108A and 108C, and the MIM type An aluminum alloy layer 109B that connects the lower electrode 105 of the capacitor and the buried copper wiring (lower conductor) 103B through contact holes 108B and 108D is formed at the same time.
Thereafter, a passivation film is formed and a pad opening is formed thereon, which is not shown here.

When the MIM type capacitor is formed on the multilayer wiring portion and the MIM type capacitor is connected to the lower conductive layer as in the related art described above, the connection is formed in the interlayer insulating film to form the lower layer. This is achieved by the upper conductive film through a contact hole exposing the conductive layer and a contact hole exposing the electrode of the MIM capacitor.
However, this connection method has a problem that a steep step is likely to occur at the edge of the contact hole, and the upper conductive film is likely to be disconnected or have high resistance at the step portion.

  This will be described in detail in the related art described above. As shown in A part and B part surrounded by broken lines in FIG. 9B, there is a steep step particularly at the edges of the contact holes 108C and 108D of the MIM capacitor. Arise. The sharp edge shape of the step reduces the coverage of the aluminum alloy layer 109A or 109B, and the aluminum alloy layer tends to have high resistance in this portion. In the worst case, the aluminum alloy layer 109A or 109B may be disconnected.

In order to prevent this, the interlayer insulating film 108 may be smoothed by CMP or the like before the contact holes 108A to 108D are formed.
However, in this method, the number of steps increases and the cost increases, and the thickness of the interlayer insulating film 108 differs between contact holes due to smoothing. For this reason, over-etching when forming the contact hole becomes excessive, particularly with respect to the upper electrode 107 of the MIM capacitor, leading to a decrease in the reliability of the MIM capacitor due to plasma damage.

  A problem to be solved by the present invention is a semiconductor device in which an MIM type capacitor and a lower layer conductor are connected by this upper layer conductive film without causing disconnection or high resistance of the upper layer conductive film, and a method for manufacturing the same. Is to provide.

In a semiconductor device according to the present invention, an interlayer insulating film and an upper conductive film are stacked on an MIM capacitor including a lower electrode, a capacitor dielectric film, and an upper electrode in a stacked portion on a semiconductor substrate. One electrode includes an extension portion that extends outward from a portion that is capacitively coupled to the other electrode via the capacitor dielectric film and extends above a lower conductor formed below the MIM capacitor portion, A distal end portion of the extension portion and the lower conductor are connected by the upper conductive film in an opening formed in the interlayer insulating film.
Preferably, the lower conductor is a wiring made of a conductive material formed by embedding in a lower insulating layer of the MIM capacitor.
Preferably, the upper conductive film is a wiring made of a conductive material containing aluminum.

In this semiconductor device, the connection portion between one electrode of the MIM capacitor and the lower layer conductor, that is, the vicinity of the tip of the extension portion extending outward from the substantial capacitor portion is in one opening formed in the interlayer insulating film. positioned. Then, the one electrode and the lower layer conductor are connected by an upper layer conductive film in the opening.
In the related art described above, when the upper conductive film starts from one of the electrodes, it temporarily reaches the lower conductor through the interlayer insulating film. In the present invention, the upper conductive film crosses the interlayer insulating film. It is not.
In the present invention, the one electrode may be either an upper electrode or a lower electrode. Moreover, the structure by which the upper electrode and the lower electrode are each connected to another lower-layer conductor may be sufficient.

According to the method of manufacturing a semiconductor device of the present invention, an MIM type capacitor including a lower electrode, a capacitor dielectric film, and an upper electrode is formed on a stacked portion including first and second lower conductors stacked on a semiconductor substrate. And a method of manufacturing a semiconductor device for connecting the upper electrode and the first lower conductor, and connecting the lower electrode and the second lower conductor, wherein the second lower conductor and Forming the lower electrode at a position that partially overlaps the planar pattern; forming a capacitor dielectric film on the lower electrode; and part of the capacitance with the lower electrode via the capacitor dielectric film A step of forming the upper electrode at a position where the other portion overlaps the first lower conductor on the planar pattern; and depositing an interlayer insulating film on the formed MIM capacitor; A first opening including a portion near a boundary where the upper electrode of the MIM capacitor and the first lower layer conductor overlap; and a portion near a boundary of a portion where the lower electrode and the second lower layer conductor overlap. Forming a second opening in the interlayer insulating film; and forming and patterning a conductive film on the interlayer insulating film to form the upper electrode and the first lower layer in the first opening. Simultaneously forming a first upper conductive film connecting a conductor and a second upper conductive film connecting the lower electrode and the second lower conductor in the second opening; including.
Preferably, as the first and second lower layer conductors, two wirings of a conductive material containing copper are embedded in the insulating layer of the stacked portion.
Preferably, the upper conductive film is formed from a conductive material containing aluminum.

  In this manufacturing method, when the MIM type capacitor is formed, it is necessary to shift the lower electrode and the upper electrode on the plane pattern, and to form at least one of the “extension portions” referred to in the semiconductor device on one of the electrodes. The number of times of patterning, that is, the number of photomasks is one in the step of forming the lower electrode and one in the step of forming the upper electrode, which is two in total, which is different from the manufacturing method of the related art. Absent. In addition, the number of openings for opening the interlayer insulating film is different from that of the related art, but since these are formed together, there is no increase or decrease in the number of photomasks or the number of processes.

  According to the semiconductor device of the present invention, the upper conductive film for connecting one electrode of the MIM capacitor to the lower conductor achieves the connection in one opening of the interlayer insulating film. This means that the upper conductive film does not pass through a steep step due to the opening edge of the interlayer insulating film in the connection path. For this reason, the coverage of the upper conductive film is uniform in the connection path as compared with the related art, and there is no place where the resistance is extremely increased or there is a possibility of disconnection. As a result, the electrical reliability of the MIM type capacitor connection structure is improved.

  According to the semiconductor device manufacturing method of the present invention, the above-described MIM capacitor connection structure with high electrical reliability can be achieved without increasing the cost.

  Hereinafter, embodiments of the present invention will be described by taking the case where the lower conductor is a buried copper wiring as an example.

FIG. 1 shows a cross-sectional view of a semiconductor device having an MIM type capacitor.
This semiconductor device includes a multilayer wiring portion (laminated portion) formed on a semiconductor substrate 1 such as a silicon wafer. In FIG. 1, the uppermost interlayer insulating film 2 of this multilayer wiring portion and two embedded copper wirings as lower conductors 3A and 3B formed thereon are shown.
A copper diffusion prevention film 4 made of, for example, silicon oxide is formed on the interlayer insulating film 2 and the lower conductors 3A and 3B, and an MIM capacitor CAP is formed thereon.

The MIM type capacitor CAP includes a lower electrode 5, a capacitor dielectric film 6, and an upper electrode 7 that are stacked in order from the copper diffusion prevention film 4 side.
Capacitor dielectric film 6 is made of, for example, silicon nitride or another dielectric.
The lower electrode 5 and the upper electrode 7 are shifted to one and the other in the horizontal direction in FIG. 1, whereby an effective capacitor part where both electrodes face each other with the capacitor dielectric film 6 interposed therebetween, and one from the capacitor part And a portion of each electrode that extends to the other side and does not face the other electrode (hereinafter referred to as an extension portion). The extension portion 7B of the upper electrode extends from the capacitor portion to one side and reaches the upper side of the first lower layer conductor 3A. The extension part 5B of the lower electrode extends from the capacitor part to the other side and reaches the upper side of the second lower layer conductor 3B.

  On the MIM type capacitor CAP, an interlayer insulating film 8 made of, for example, silicon oxide is deposited, and two openings are formed therein. A first opening 8A is formed on the extension part 7B side of the upper electrode, and a second opening 8B is formed on the extension part 5B side of the lower electrode. Since these openings are formed with a silicon oxide etching gas, the silicon oxide insulating film, that is, the copper diffusion prevention film 4 and the capacitor dielectric film 6 on the first and second lower conductors 3A and 3B. The capacitor dielectric film 6 existing on the lower electrode 5 in the second opening 8B is removed. However, in the second opening 8B, the copper diffusion prevention film 4 immediately below the extension part 5B of the lower electrode is protected by the extension part 5B and is not etched. Similarly, in the first opening 8A, the capacitor dielectric film 6 and the copper diffusion prevention film 4 immediately below the extension part 7B of the upper electrode are protected by the extension part 7B and are not etched.

  A first upper conductive film 9A filling the first opening 8A and a second upper conductive film 9B filling the second opening 8B are formed. The first and second upper conductive films 9A and 9B can be formed as a wiring made of, for example, an aluminum alloy (such as copper-containing aluminum), and can be patterned to have a wire bonding pad at the tip.

The first and second upper conductive films 9A and 9B are separated by a portion of the interlayer insulating film 8 that protects the vicinity of the boundary between the extension portion 5B and the upper electrode 7 of the lower electrode. This portion of the interlayer insulating film 8 is absolutely necessary, and in this example, the first and second openings 8A and 8B are formed on both sides thereof.
However, the first and second openings 8A and 8B may be a single opening. That is, FIG. 1 shows a cross section when a portion of the interlayer insulating film 8 for separating the first and second upper conductive films 9A and 9B is left in an island shape in one opening. It can also be considered.

  Further, the first and second lower-layer conductors 3A and 3B are not limited to the embedded copper wiring, but may be a conductive layer (for example, a plug or an intermediate connection layer) other than the embedded wiring and wiring of other materials. Therefore, the laminated portion where the MIM capacitor CAP is formed does not necessarily need to be a multilayer wiring portion. Moreover, the material and film thickness of each conductive film and insulating film are also arbitrary.

According to this semiconductor device, in the connection portion between the upper electrode 7 of the MIM type capacitor CAP and the first lower layer conductor 3A, that is, in the upper electrode 7, the vicinity of the tip of the extension portion 7B extending outward from the substantial capacitor portion is formed. It is located in one opening (first opening 8A) formed in the interlayer insulating film 8. The upper electrode 7 and the first lower conductor 3A are connected by the first upper conductive film 9A in the first opening 8A. Further, in the connection portion between the lower electrode 5 of the MIM type capacitor CAP and the second lower conductor 3B, that is, in the lower electrode 5, the vicinity of the tip of the extension portion 5B extending outward from the substantial capacitor portion is the interlayer insulating film 8. It is located in one formed opening (second opening 8B). The lower electrode 5 and the second lower conductor 3B are connected by the second upper conductive film 9B in the second opening 8B.
By adopting such a connection portion, the first and second upper conductive films 9A and 9B do not go through a steep step due to the opening edge of the interlayer insulating film 8 in the connection path. For this reason, the coverage of the first and second upper conductive films 9A and 9B is uniform in the connection path as compared with the related art, and there are no places where the resistance is extremely increased or there is a risk of disconnection. As a result, the electrical reliability of the MIM type capacitor connection structure is improved.

In FIG. 1, the lower conductor and the MIM type capacitor CAP are connected to each other at two connection points. However, depending on the integrated circuit configuration formed in the semiconductor device, there may be a case where the MIM type capacitor is simply connected to the pad or the like.
In consideration of such a case, in the present invention, the electrode of the MIM type capacitor CAP is connected to the lower layer conductor only at one connection point, and the MIM type capacitor CAP is simply connected to the upper layer conductive film at the other connection point. It does not matter if you make it.

  Next, taking the configuration shown in FIG. 1 as an example, an embodiment of the semiconductor device manufacturing method according to the present invention will be described.

2A to 5 show cross-sectional views of the respective steps in manufacturing the semiconductor device. In these drawings, only the uppermost layer portion of the multilayer wiring portion is shown, and lower-layer wiring, transistors, and the like are not shown.
As shown in FIG. 2A, lower conductors 3 A and 3 B are formed in an interlayer insulating film 2 on the surface of the semiconductor substrate 1, and the surface is covered with a copper diffusion preventing film 4. A normal buried copper wiring process can be used to form the lower conductors 3A and 3B.
An interlayer insulating film 2 is deposited, a groove is dug in the upper part of the interlayer insulating film 2 by photolithography and dry etching, and copper is formed by plating. When this copper is etched and separated by CMP or the like, a buried copper wiring is formed in each groove. A copper diffusion prevention film 4 is formed on the interlayer insulating film 2 including the upper surface of the buried trench wiring by, for example, a CVD method so that the copper does not diffuse easily.

  Next, a titanium nitride (TiN) film 5A to be the lower electrode 5 of the MIM type capacitor CAP is formed on the copper diffusion prevention film 4 by, for example, a sputtering method to a thickness of about 200 nm.

  For example, the photoresist is patterned and the titanium nitride film 5A is dry-etched using this as a mask to form the lower electrode 5 of the MIM type capacitor CAP shown in FIG. 2B (lower electrode forming step). The lower electrode 5 does not overlap with the first lower layer conductor 3A on the plane pattern, but partially overlaps with the second lower layer conductor 3B.

  As shown in FIG. 3A, a silicon nitride film to be the capacitor dielectric 6 of the MIM type capacitor CAP is formed with a thickness of about 50 nm by, for example, PECVD, and titanium nitride to be the upper electrode 7 of the MIM type capacitor CAP, for example, by sputtering. A (TiN) film 7A is formed to a thickness of about 100 nm (capacitor dielectric film forming step).

For example, the upper electrode 7 of the MIM type capacitor CAP is formed by patterning a photoresist and dry-etching the titanium nitride film 7A using this as a mask (upper electrode forming step). At this time, a part of the upper electrode 7 of the MIM type capacitor CAP protrudes above the first lower layer conductor 3A rather than the lower electrode 5 of the MIM type capacitor CAP.
When the photoresist is removed, the basic structure of the MIM type capacitor CAP shown in FIG. 3B is completed. The upper electrode 7 includes a portion (extension portion 7B) in which the upper electrode 7 extends from the capacitor portion facing the lower electrode 5 through the capacitor dielectric film 6 to above the first lower conductor 3A. Similarly, the lower electrode 5 includes a portion (extension portion 5B) protruding from the capacitor portion to above the second lower layer conductor 3B.

  As shown in FIG. 4A, a silicon oxide film of about 700 nm is formed as an interlayer insulating film 8 between the lower conductors 3A and 3B and the aluminum alloy layer for pads (upper conductive film; not shown), for example, by PECVD.

For example, after patterning a photoresist and using this as a mask, the interlayer insulating film 8, the silicon nitride film 6A and the copper diffusion prevention film 4 are dry etched, and then the photoresist is removed. As a result, as shown in FIG. 4B, the upper electrode 7 of the MIM capacitor CAP and the first lower conductor 3A are connected by the pad aluminum alloy layer (first upper conductive film 9A; described later). 8A for opening, and 2nd opening for connecting lower electrode 5 and 2nd lower layer conductor 3B by the aluminum alloy layer for pads (2nd upper layer electrically conductive film 9B; mentioned later) 8B is formed in each interlayer insulating film 8 (opening forming step).
At this time, the upper electrode 7 of the MIM type capacitor CAP and the first lower layer conductor 3A are both positioned in the first opening 8A, and the lower electrode 5 and the second lower layer conductor are positioned in the second opening 8B. Both conductors 3B are located.

  As shown in FIG. 5, an aluminum alloy for pad 9C is formed to a thickness of about 1000 nm by sputtering, for example.

For example, after patterning a photoresist and using this as a mask, the aluminum alloy for pad 9C is dry-etched, the photoresist is removed. Accordingly, as shown in FIG. 1, the first upper conductive film 9A connecting the upper electrode 7 of the MIM type capacitor CAP and the first lower layer conductor 3A, the lower electrode 5 of the MIM type capacitor CAP, and the second electrode The second upper conductive film 9B connecting the lower conductor 3B is formed from two aluminum alloy layers separated from each other (upper conductive film forming step).
Thereafter, a passivation film is formed, and an opening of the pad is formed in this, but the details are omitted here.

According to the semiconductor device manufacturing method described above, when the MIM type capacitor is formed, the lower electrode 5 and the upper electrode 7 are shifted on the plane pattern, and at least one “extension portion” is formed on one of the electrodes. The number of times of patterning at this time, that is, the number of photomasks is one in the step of FIG. 2B for forming the lower electrode 5 and one in the step of FIG. 3B for forming the upper electrode 7. It is two pieces, and this is not different from the manufacturing method of related technology. Although the number of openings 8A and 8B for opening the interlayer insulating film 8 is different from that of the related art, since these are formed at the same time, there is no increase or decrease in the number of photomasks or the number of processes. Therefore, the application of the present invention does not change the number of steps in the manufacturing process and the increase or decrease in the number of photomasks.
Further, since the MIM capacitor electrode, the lower conductor, and the upper conductive film are directly connected, the area of the connection portion is not changed or can be reduced.
As described above, the application of the manufacturing method according to the present embodiment provides the advantage that the structure shown in FIG. 1 effective in improving the electrical reliability described above can be easily manufactured at low cost.

  The present invention can be applied to all semiconductor devices that have, for example, a laminated portion having a buried copper wiring and other laminated portions and need to connect a lower conductor in the laminated portion and an electrode of an MIM capacitor.

It is sectional drawing of the semiconductor device which has a MIM type | mold capacitor which concerns on embodiment of this invention. (A) And (B) is sectional drawing which shows the process until lower electrode formation, when forming a MIM type capacitor on a multilayer wiring part in manufacture of the semiconductor device shown in FIG. (A) And (B) is sectional drawing which shows the process from the process following FIG. 2 (B) to upper electrode formation. (A) And (B) is sectional drawing which shows the process from the process following FIG. 3 (B) to opening of an interlayer insulation film. FIG. 5 is a cross-sectional view showing a step after the step of forming the aluminum alloy subsequent to FIG. (A) And (B) is sectional drawing which shows the process until formation of the film | membrane used as an upper electrode, when forming a MIM type capacitor on a multilayer wiring part by the manufacturing method as a related technique of this invention. (A) And (B) is sectional drawing which shows the process from the process following FIG. 6 (B) to the patterning of a lower electrode. (A) And (B) is sectional drawing which shows the process from the process following FIG. 7 (B) to the opening of an interlayer insulation film. (A) And (B) is sectional drawing which shows the process from the process following FIG. 8 (B) to the patterning of an aluminum alloy layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Interlayer insulation film of uppermost layer of multilayer wiring part, 3A ... 1st lower layer conductor, 3B ... 2nd lower layer conductor, 4 ... Copper diffusion prevention film, 5 ... Lower electrode, 5B ... Extension part of lower electrode, 6 ... capacitor dielectric film, 7 ... upper electrode, 7B ... extension part of upper electrode, 8 ... interlayer insulating film, 9A ... first upper conductive film, 9B ... second upper conductive film

Claims (10)

In the laminated portion on the semiconductor substrate, an interlayer insulating film and an upper conductive film are laminated on the MIM type capacitor including the lower electrode, the capacitor dielectric film, and the upper electrode,
One electrode of the MIM type capacitor extends outward from a portion capacitively coupled to the other electrode via the capacitor dielectric film, and extends above a lower layer conductor formed below the MIM capacitor portion. Part
A semiconductor device having an MIM type capacitor in which a tip portion of the extension part and the lower conductor are connected by the upper conductive film in an opening formed in the interlayer insulating film. The upper electrode includes the extension part,
The semiconductor device having an MIM type capacitor according to claim 1, wherein the extension portion and the lower layer conductor are connected by the upper layer conductive film in an opening formed in the interlayer insulating film. The lower electrode includes the extension part,
The semiconductor device having an MIM type capacitor according to claim 1, wherein the extension portion and the lower layer conductor are connected by the upper layer conductive film in an opening formed in the interlayer insulating film. Each of the upper electrode and the lower electrode includes the extension part,
The extension portion of the upper electrode and the first lower conductor are connected by the first upper conductive film in the first opening formed in the interlayer insulating film,
The MIM type capacitor according to claim 1, wherein the extension part of the lower electrode and the second lower layer electrode are connected by a second upper conductive film in the second opening formed in the interlayer insulating film. Semiconductor device having. 5. The semiconductor having an MIM type capacitor according to claim 4, wherein the first and second openings are formed on both sides of an interlayer insulating film portion covering the vicinity of the boundary between the extension portion of the lower electrode and the upper electrode. device. The semiconductor device having the MIM type capacitor according to claim 1, wherein the lower layer conductor is a wiring made of a conductive material including copper embedded in an insulating layer below the MIM type capacitor. The semiconductor device having a MIM type capacitor according to claim 1, wherein the upper conductive film is a wiring made of a conductive material containing aluminum. An MIM type capacitor including a lower electrode, a capacitor dielectric film and an upper electrode is formed on a stacked portion including the first and second lower conductors stacked on the semiconductor substrate, and the upper electrode and the first lower layer are formed. A method of manufacturing a semiconductor device for connecting a conductor and connecting the lower electrode and the second lower layer conductor,
Forming the lower electrode at a position partially overlapping with the second lower layer conductor on a planar pattern;
Forming a capacitor dielectric film on the lower electrode;
Forming the upper electrode at a position where a part is capacitively coupled to the lower electrode via the capacitor dielectric film and the other part overlaps the first lower conductor on the plane pattern;
An interlayer insulating film is deposited on the formed MIM capacitor, the first opening including the vicinity of the boundary where the upper electrode of the MIM capacitor and the first lower layer conductor overlap, the lower electrode, and the first Forming in the interlayer insulating film a second opening including the vicinity of the boundary of the portion where the two lower conductors overlap;
Forming a conductive film on the interlayer insulating film and patterning the first upper conductive film for connecting the upper electrode and the first lower conductor in the first opening; and the second Simultaneously forming a second upper conductive film connecting the lower electrode and the second lower conductor in the opening of
A method of manufacturing a semiconductor device having an MIM type capacitor including: The manufacturing of a semiconductor device having an MIM type capacitor according to claim 8, wherein two wirings of a conductive material containing copper are embedded in the insulating layer of the stacked portion as the first and second lower layer conductors. Method. The method for manufacturing a semiconductor device having an MIM type capacitor according to claim 8, wherein the upper conductive film is formed from a conductive material containing aluminum.

Images