KR101096524B1 - Semiconductor device and method for forming the same - Google Patents

Semiconductor device and method for forming the same Download PDF

Info

Publication number
KR101096524B1
KR101096524B1 KR1020040118001A KR20040118001A KR101096524B1 KR 101096524 B1 KR101096524 B1 KR 101096524B1 KR 1020040118001 A KR1020040118001 A KR 1020040118001A KR 20040118001 A KR20040118001 A KR 20040118001A KR 101096524 B1 KR101096524 B1 KR 101096524B1
Authority
KR
South Korea
Prior art keywords
forming
resistor
semiconductor device
mim capacitor
metal
Prior art date
Application number
KR1020040118001A
Other languages
Korean (ko)
Other versions
KR20060078396A (en
Inventor
조진연
Original Assignee
매그나칩 반도체 유한회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 매그나칩 반도체 유한회사 filed Critical 매그나칩 반도체 유한회사
Priority to KR1020040118001A priority Critical patent/KR101096524B1/en
Publication of KR20060078396A publication Critical patent/KR20060078396A/en
Application granted granted Critical
Publication of KR101096524B1 publication Critical patent/KR101096524B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
    • H01L27/0788—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type comprising combinations of diodes or capacitors or resistors
    • H01L27/0794—Combinations of capacitors and resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes

Abstract

본 발명은 반도체 소자 및 그의 형성 방법에 관한 것으로, MIM(Metal Insulator Metal) 캐패시터 및 박막 레지스터(Thin Film Resistor : TFR)를 구비한 반도체 소자에 있어서, MIM 캐패시터 및 레지스터가 분리되어 있고 레지스터에는 패드부가 더 포함되어 반도체 소자의 고집적화를 저해하고 그 형성 공정이 복잡하여 수율이 떨어지는 문제를 해결하기 위하여, 레지스터 패드부를 상부 전극으로 하고 상기 패드부의 하부에 형성되는 확산방지막을 유전층으로 하며 금속 배선을 하부 전극으로 사용하는 MIM 캐패시터를 포함하는 반도체 소자 및 그의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for forming the same. In the semiconductor device having a metal insulator metal (MIM) capacitor and a thin film resistor (TFR), the MIM capacitor and the resistor are separated, and the pad portion is formed on the resistor. In order to prevent the high integration of semiconductor devices and to solve the problem that the formation process is complicated and the yield is lowered, the resistor pad part is used as the upper electrode, the diffusion barrier formed under the pad part is used as the dielectric layer, and the metal wiring is used as the lower electrode. The present invention relates to a semiconductor device including a MIM capacitor to be used and a method of forming the same.

Description

반도체 소자 및 그의 형성 방법{SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME}Semiconductor device and method of forming the same {SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME}

도 1a 내지 1c는 종래 기술에 따른 MIM 캐패시터 및 레지스터의 형성 방법을 도시한 단면도들.1A-1C are cross-sectional views illustrating a method of forming a MIM capacitor and a resistor according to the prior art.

도 2는 종래 기술에 따른 MIM 캐패시터 및 레지스터를 도시한 평면도.2 is a plan view showing a MIM capacitor and a register according to the prior art;

도 3a 내지 도 3c는 본발명에 따른 반도체 소자의 형성 방법을 도시한 단면도들.3A to 3C are cross-sectional views illustrating a method of forming a semiconductor device according to the present invention.

도 4 및 도 5는 본 발명에 따른 반도체 소자를 도시한 평면도들.4 and 5 are plan views showing a semiconductor device according to the present invention.

본 발명은 반도체 소자 및 그의 형성 방법에 관한 것으로, MIM 캐패시터 및 박막 레지스터(Thin Film Resistor : TFR)를 구비한 반도체 소자에 있어서, MIM 캐패시터 및 레지스터가 분리되어 있고 레지스터에는 패드부가 더 포함되어 반도체 소자의 고집적화를 저해하고 그 형성 공정이 복잡하여 수율이 떨어지는 문제를 해결하기 위하여, 레지스터 패드부를 상부 전극으로 하고 상기 패드부의 하부에 형성되는 확산방지막을 유전층으로 하며 금속 배선을 하부 전극으로 사용하는 MIM 캐패 시터를 포함하는 반도체 소자 및 그의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of forming the same, wherein the semiconductor device includes a MIM capacitor and a thin film resistor (TFR), wherein the MIM capacitor and the resistor are separated, and the resistor further includes a pad part. In order to prevent high integration and to reduce the yield due to the complicated formation process, the MIM capacitor using the resistor pad as the upper electrode, the diffusion barrier formed under the pad as the dielectric layer, and the metal wiring as the lower electrode. A semiconductor device comprising a sheeter and a method of forming the same.

반도체 소자 중 고집적 반도체 소자에 사용되는 캐패시터의 구조로는 폴리실리콘 대 폴리실리콘(Polysilicon to Polysilicon), 폴리실리콘 대 실리콘(Polysilicon to Silicon), 금속층 대 실리콘(Metal to Silicon), 금속층 대 폴리실리콘(Metal to Polysilicon) 및 금속층 대 금속층(Metal to Metal)의 다양한 캐패시터 구조들이 사용되어 왔다. 이들 캐패시터 구조들 중 금속층 대 금속층(Metal to Metal) 또는 금속층/유전막/금속층(Metal Insulator Metal : 이하 MIM) 구조는 직렬 저항(Series Resistance)이 낮아 높은 저장 용량을 갖는 캐패시터를 만들 수 있으며, 열적 안정성 및 VCC가 낮은 장점으로 인하여 현재 캐패시터의 구조로 널리 이용되고 있다.Among the semiconductor devices, capacitors used in highly integrated semiconductor devices include polysilicon to polysilicon, polysilicon to silicon, metal to silicon, and metal to metal. Various capacitor structures of to Polysilicon and metal to metal have been used. Among these capacitor structures, metal to metal or metal to dielectric / metal insulator metal (MIM) structures have a low series resistance, which makes a capacitor having high storage capacity and thermal stability. And because of the low VCC advantage is widely used as the structure of the current capacitor.

한편 반도체 소자에 사용되는 소자는 MIM 캐패시터 이외에 레지스터(Resistor) 또는 인덕터(Inductor)와 같은 것들이 있다. 그 중에서도 레지스터, 특히 박막 레지스터(TFR)은 MIM 캐패시터와 동일한 층에 형성할 수 있는 소자로 동일한 식각 공정을 통하여 형성될 수 있다.On the other hand, devices used in semiconductor devices include resistors or inductors in addition to MIM capacitors. Among them, the resistor, particularly the thin film resistor (TFR), may be formed on the same layer as the MIM capacitor and may be formed through the same etching process.

도 1a 내지 1c는 종래 기술에 따른 MIM 캐패시터 및 레지스터의 형성 방법을 도시한 단면도들이다.1A to 1C are cross-sectional views illustrating a method of forming a MIM capacitor and a resistor according to the prior art.

도 1a를 참조하면, 반도체 기판(10) 상부에 층간절연막(20)을 형성하고 하부 제 1 금속 배선(30)을 형성한다. 다음에는 전체 표면에 금속 배선 확산 방지용 질화막(40), 상부 전극용 TaN막(50) 및 비아 에치(Via Etch)용 식각정지 질화막(60)을 순차적으로 형성한다. Referring to FIG. 1A, an interlayer insulating film 20 is formed on a semiconductor substrate 10, and a lower first metal wire 30 is formed. Next, the nitride film 40 for preventing the diffusion of metal wirings, the TaN film 50 for the upper electrode, and the etch stop nitride film 60 for the via etch are formed sequentially on the entire surface.                         

도 1b를 참조하면, 식각정지 질화막(60) 상부에 MIM 캐패시터(85) 및 레지스터(65)를 각각 정의 하는 감광막 패턴(70)을 형성한 후, 감광막 패턴(70)을 식각마스크로 식각정지 질화막(60) 및 상부 전극용 TaN막(50)을 식각하여 MIM 캐패시터(85) 및 레지스터(65)를 형성한다. 이때, 레지스터(65)의 양측에 레지스터(65)를 연결하는 패드부(75)가 형성된다.Referring to FIG. 1B, after the photoresist pattern 70 defining the MIM capacitor 85 and the resistor 65 is formed on the etch stop nitride layer 60, the photoresist pattern 70 is used as the etch stop nitride layer. The 60 and the TaN film 50 for the upper electrode are etched to form the MIM capacitor 85 and the resistor 65. At this time, pad portions 75 are formed at both sides of the resistor 65 to connect the resistor 65.

도 1c를 참조하면, 감광막 패턴(70)을 제거한 후 반도체 기판 전면에 IMD(Inter Metal Dielectric) 층간절연막(80)을 형성한다. 다음에는, 층간절연막(80)에 제 2 금속 배선용 다마신 패턴을 형성하고, 패턴 내에 금속층을 매립하여 제 2 금속 배선(90)을 형성한다. 이때, 제 2 금속 배선(90)은 MIM 캐패시터(85) 및 레지스터 양단의 패드부(75)와 각각 연결된다.Referring to FIG. 1C, after removing the photoresist pattern 70, an inter metal dielectric (IMD) interlayer dielectric layer 80 is formed on the entire surface of the semiconductor substrate. Next, a damascene pattern for the second metal wiring is formed in the interlayer insulating film 80, and the second metal wiring 90 is formed by embedding the metal layer in the pattern. In this case, the second metal wire 90 is connected to the MIM capacitor 85 and the pad portion 75 at both ends of the resistor, respectively.

도 2는 종래 기술에 따른 MIM 캐패시터 및 레지스터를 도시한 평면도이다.2 is a plan view illustrating a MIM capacitor and a register according to the prior art.

도 2를 참조하면, 반도체 기판(10) 상에 MIM 캐패시터(85) 및 레지스터(65)가 구비된 것을 나타낸 개념도로, 레지스터(65)의 양측에 레지스터 패드부(75)가 구비되어 있다.Referring to FIG. 2, a conceptual diagram showing that the MIM capacitor 85 and the resistor 65 are provided on the semiconductor substrate 10, the register pads 75 are provided on both sides of the resistor 65.

상술한 바와 같이, MIM 캐패시터 및 레지스터는 서로 분리되어 형성되고, 레지스터에는 패드부가 더 포함되어 두 소자가 차지하는 면적 비율이 높다. 따라서, 반도체 소자에서 고집적화를 저해하고 그 형성 공정이 복잡해지는 원인이 된다. 이로 인해 반도체 소자의 불량률이 증가하고, 형성 수율이 떨어지는 문제가 발생한다.As described above, the MIM capacitor and the resistor are formed separately from each other, and the register further includes a pad portion, so that the area ratio of the two elements is high. Therefore, high integration is inhibited in the semiconductor device and the formation process thereof becomes complicated. As a result, the defect rate of the semiconductor element increases, and the yield of the formation decreases.

본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, MIM 캐패시터 및 박막 레지스터를 구비한 반도체 소자에 있어서 레지스터 패드부를 상부 전극으로 하고 상기 패드부의 하부에 형성되는 확산방지막을 유전층으로 하며 금속 배선을 하부 전극으로 사용하는 MIM 캐패시터를 구성함으로써, 반도체 소자를 고집적화하고 형성 수율 및 반도체 소자의 특성을 향상 시킬 수 있는 반도체 소자 및 그의 형성 방법을 제공하는 것을 그 목적으로 한다. The present invention is to solve the above problems, in a semiconductor device having a MIM capacitor and a thin film resistor, the resistor pad portion as the upper electrode, the diffusion barrier formed on the lower portion of the pad portion as a dielectric layer and the metal wiring lower electrode It is an object of the present invention to provide a semiconductor device and a method for forming the same, which are capable of high integration of semiconductor devices, and improved formation yields and characteristics of semiconductor devices by constituting MIM capacitors.

본 발명은 상기와 같은 목적을 달성하기 위한 것으로서,The present invention is to achieve the above object,

양단에 패드부를 구비한 레지스터 및A register having pads at both ends thereof;

상기 패드부를 상부 전극으로 하고 상기 패드부의 하부에 형성되는 확산방지막을 유전층으로 사용하며 금속 배선을 하부 전극으로 사용하는 MIM 캐패시터를 포함하는 것을 특징으로 한다.And a MIM capacitor using the pad portion as an upper electrode, a diffusion barrier formed under the pad portion as a dielectric layer, and a metal wiring as the lower electrode.

아울러, 본 발명에 따른 반도체 소자의 형성 방법은In addition, the method of forming a semiconductor device according to the present invention

(a) 반도체 기판 상에 층간절연막을 형성하고, 상기 층간절연막 내에 제 1 및 제 2 금속 배선을 형성하는 단계와,(a) forming an interlayer insulating film on the semiconductor substrate, and forming first and second metal wirings in the interlayer insulating film;

(b) 상기 제 1 및 제 2 금속 배선을 포함한 전체 표면에 확산방지 유전층, 상부 전극층 및 식각정지막을 순차적으로 형성하는 단계와,(b) sequentially forming a diffusion barrier dielectric layer, an upper electrode layer, and an etch stop layer on the entire surface including the first and second metal lines;

(c) 상기 식각정지막 상부에 패드부를 MIM 캐패시터로 사용하는 레지스터를 정의하는 감광막 패턴을 형성하는 단계와,(c) forming a photoresist pattern on the etch stop layer and defining a register using the pad as a MIM capacitor;

(d) 상기 감광막 패턴을 식각 마스크로 상기 식각정지막 및 상부 전극층을 식각하여 상기 제 1 및 제 2 금속 배선 사이에 위치하는 레지스터 및 상기 레지스터의 양 단부에 위치하는 MIM 캐패시터를 형성하는 것을 특징으로 한다.
상기 (d) 단계에서 상기 식각정지막 및 상부 전극층을 식각하는 단계는 3 ~ 2000mT의 압력하에서 CxHyFz(x, y, z는 자연수)의 유량을 1 ~ 300sccm, O2의 유량을 1 ~ 100sccm 및 Ar의 유량을 100 ~ 2000sccm을 주입하여 수행하는 것을 특징으로 한다.(d) etching the etch stop layer and the upper electrode layer using the photoresist pattern as an etch mask to form a resistor located between the first and second metal wires and a MIM capacitor located at both ends of the resistor; do.
Etching the etch stop layer and the upper electrode layer in the step (d) is a flow rate of CxHyFz (x, y, z is natural water) 1 ~ 300sccm, O 2 flow rate of 1 ~ 100sccm and under a pressure of 3 ~ 2000mT and The flow rate of Ar is characterized by performing by injecting 100 ~ 2000sccm.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 형성 방법에 관하여 상세히 설명하기로 한다.Hereinafter, a method of forming a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3c는 본발명에 따른 반도체 소자의 형성 방법을 도시한 단면도들이다.3A to 3C are cross-sectional views illustrating a method of forming a semiconductor device according to the present invention.

도 3a를 참조하면, 반도체 기판(100) 상에 층간절연막(120)을 형성하고, 층간절연막 내에 제 1 및 제 2 금속 배선(130)을 형성한다.Referring to FIG. 3A, an interlayer insulating film 120 is formed on a semiconductor substrate 100, and first and second metal wires 130 are formed in the interlayer insulating film.

다음에는, 전체 표면에 확산방지 유전층(140), 상부 전극층(150) 및 식각정지막(160)을 순차적으로 형성한다. 이때, 제 1 및 제 2 금속 배선(130)은 MIM 캐패시터의 하부 전극층이 되고, 식각정지막(160)은 후속의 공정에서 상부 전극층(150)과 연결되는 비아 콘택홀을 형성할 때 상부 전극층(150)을 보호하는 기능을 수행한다.Next, the diffusion barrier dielectric layer 140, the upper electrode layer 150, and the etch stop layer 160 are sequentially formed on the entire surface. In this case, the first and second metal wires 130 become lower electrode layers of the MIM capacitor, and the etch stop layer 160 forms an upper contact electrode layer when forming a via contact hole connected to the upper electrode layer 150 in a subsequent process. 150) to protect the function.

도 3b를 참조하면, 식각정지막(160) 상부에 패드부를 MIM 캐패시터로 사용하는 레지스터(165)를 정의하는 감광막 패턴(170)을 형성 한다.Referring to FIG. 3B, a photoresist pattern 170 is formed on the etch stop layer 160 to define a resistor 165 using the pad as a MIM capacitor.

도 3c를 참조하면, 감광막 패턴(170)을 식각 마스크로 식각정지막(160) 및 상부 전극층(150)을 식각하여 제 1 및 제 2 금속 배선(130) 사이에 위치하는 레지스터(165) 및 레지스터의 양 단부에 위치하는 MIM 캐패시터(185)를 형성한다.Referring to FIG. 3C, the etch stop layer 160 and the upper electrode layer 150 are etched using the photoresist pattern 170 as an etch mask, and the register 165 and the resistor are positioned between the first and second metal wires 130. MIM capacitors 185 are formed at both ends of the substrate.

다음에는, 반도체 기판(100) 전면에 상부 제 3 금속 배선용 트렌치 형성을 위한 층간절연막(180)을 형성하고, 레지스터 패드부가 되는 MIM 캐패시터(185)와 연결되는 제 3 금속 배선(190)을 형성한다.Next, an interlayer insulating layer 180 for forming an upper third metal wiring trench is formed on the entire surface of the semiconductor substrate 100, and a third metal wiring 190 connected to the MIM capacitor 185 serving as a resistor pad is formed. .

도 4 및 도 5는 본 발명에 따른 반도체 소자를 도시한 평면도들이다.4 and 5 are plan views illustrating a semiconductor device according to the present invention.

도 4는 상기 도 3b의 단계에서 반도체 기판(100) 상에 감광막 패턴(170)을 형성한 것을 나타낸 평면도이다. 하부의 제 1 및 제 2 금속 배선(130) 사이에 레지스터(165)가 위치하고, 레지스터 양단부에 MIM 캐패시터(185)가 형성되도록 감광막 패턴(170)을 형성한다.4 is a plan view illustrating the formation of the photosensitive film pattern 170 on the semiconductor substrate 100 in the step of FIG. 3B. The resistor 165 is positioned between the lower first and second metal wires 130, and the photosensitive film pattern 170 is formed to form the MIM capacitor 185 at both ends of the resistor.

도 5는 감광막 패턴(170)을 제거한 후 비아 콘택홀이 형성될 영역을 나타낸 평면도이다. MIM 캐패시터(185) 상부 전극층 및 하부의 제 1 및 제 2 금속 배선과 연결되도록 설계된다.5 is a plan view illustrating a region where a via contact hole is to be formed after removing the photoresist pattern 170. The MIM capacitor 185 is designed to be connected with the upper electrode layer and the lower first and second metal wires.

이상에서 설명한 바와 같이, 본 발명은 레지스터 패드부를 상부 전극으로 하고 상기 패드부의 하부에 형성되는 확산방지막을 유전층으로 하며 금속 배선을 하부 전극으로 사용하는 MIM 캐패시터를 구성함으로써, 반도체 소자의 크기를 효과적으로 감소시킬 수 있으므로 반도체 소자를 고집적화하고 형성 수율 및 소자의 특성을 향상 시킬 수 있는 효과를 제공한다.As described above, the present invention effectively reduces the size of the semiconductor device by constructing a MIM capacitor using a resistor pad as an upper electrode, a diffusion barrier formed under the pad as a dielectric layer, and metal wiring as a lower electrode. As a result, the semiconductor device can be highly integrated, and the yield and characteristics of the device can be improved.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (3)

양단에 패드부를 구비한 레지스터; 및A resistor having pads at both ends; And 상기 패드부를 상부 전극으로 하고 상기 패드부의 하부에 형성되는 확산방지막을 유전층으로 사용하며 금속 배선을 하부 전극으로 사용하는 MIM 캐패시터를 포함하는 것을 특징으로 하는 반도체 소자.And a MIM capacitor using the pad portion as an upper electrode, a diffusion barrier formed under the pad portion as a dielectric layer, and a metal wiring as the lower electrode. (a) 반도체 기판 상에 층간절연막을 형성하고, 상기 층간절연막 내에 제 1 및 제 2 금속 배선을 형성하는 단계;(a) forming an interlayer insulating film on the semiconductor substrate, and forming first and second metal wirings in the interlayer insulating film; (b) 상기 제 1 및 제 2 금속 배선을 포함한 전체 표면에 확산방지 유전층, 상부 전극층 및 식각정지막을 순차적으로 형성하는 단계;(b) sequentially forming a diffusion barrier dielectric layer, an upper electrode layer, and an etch stop layer on the entire surface including the first and second metal wires; (c) 상기 식각정지막 상부에 패드부를 MIM 캐패시터로 사용하는 레지스터를 정의하는 감광막 패턴을 형성하는 단계;(c) forming a photoresist pattern on the etch stop layer and defining a register using the pad as a MIM capacitor; (d) 상기 감광막 패턴을 식각 마스크로 상기 식각정지막 및 상부 전극층을 식각하여 상기 제 1 및 제 2 금속 배선 사이에 위치하는 레지스터 및 상기 레지스터의 양 단부에 위치하는 MIM 캐패시터를 형성하는 것을 특징으로 하는 반도체 소자의 형성 방법.(d) etching the etch stop layer and the upper electrode layer using the photoresist pattern as an etch mask to form a resistor located between the first and second metal wires and a MIM capacitor located at both ends of the resistor; A method of forming a semiconductor device. 제 2 항에 있어서,The method of claim 2, 상기 (d) 단계에서 상기 식각정지막 및 상부 전극층을 식각하는 단계는 3 ~ 2000mT의 압력하에서 CxHyFz(x, y, z는 자연수)의 유량을 1 ~ 300sccm, O2의 유량을 1 ~ 100sccm 및 Ar의 유량을 100 ~ 2000sccm을 주입하여 수행하는 것을 특징으로 하는 반도체 소자의 형성 방법.Etching the etch stop layer and the upper electrode layer in the step (d) is a flow rate of CxHyFz (x, y, z is natural water) 1 ~ 300sccm, O 2 flow rate of 1 ~ 100sccm and under a pressure of 3 ~ 2000mT and Method for forming a semiconductor device, characterized in that performed by injecting a flow rate of Ar 100 ~ 2000sccm.
KR1020040118001A 2004-12-31 2004-12-31 Semiconductor device and method for forming the same KR101096524B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020040118001A KR101096524B1 (en) 2004-12-31 2004-12-31 Semiconductor device and method for forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040118001A KR101096524B1 (en) 2004-12-31 2004-12-31 Semiconductor device and method for forming the same

Publications (2)

Publication Number Publication Date
KR20060078396A KR20060078396A (en) 2006-07-05
KR101096524B1 true KR101096524B1 (en) 2011-12-20

Family

ID=37170308

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020040118001A KR101096524B1 (en) 2004-12-31 2004-12-31 Semiconductor device and method for forming the same

Country Status (1)

Country Link
KR (1) KR101096524B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102411417B1 (en) * 2015-12-02 2022-06-22 삼성전자주식회사 Semiconductor devices having a resistor and semiconductor integrated circuit devices using the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050111415A (en) * 2004-05-20 2005-11-25 매그나칩 반도체 유한회사 Method for manufacturing a semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050111415A (en) * 2004-05-20 2005-11-25 매그나칩 반도체 유한회사 Method for manufacturing a semiconductor device

Also Published As

Publication number Publication date
KR20060078396A (en) 2006-07-05

Similar Documents

Publication Publication Date Title
US6395637B1 (en) Method for fabricating a inductor of low parasitic resistance and capacitance
JP3961412B2 (en) Semiconductor device and method for forming the same
KR100755365B1 (en) Mimmetal-insulator-metal capacitors and methods of forming the same
JP2007221161A (en) Capacitor used in semiconductor device, and production method thereof
JP2003017556A (en) Semiconductor device and method of manufacturing same
JP2004221444A (en) Method for manufacturing semiconductor device
US7087350B2 (en) Method for combining via patterns into a single mask
JP5477396B2 (en) Semiconductor device and manufacturing method thereof
KR101096524B1 (en) Semiconductor device and method for forming the same
KR100650192B1 (en) Semiconductor device and method for forming the same
KR100641980B1 (en) Interconnection line of semiconductor device and method of forming the same
KR100256525B1 (en) Semiconductor device manufacturing method having caviti
KR100571407B1 (en) Wiring manufacturing method of semiconductor element
KR100457044B1 (en) Method for manufacturing semiconductor device
KR100667900B1 (en) Method for forming semiconductor device
KR100667903B1 (en) Method for forming semiconductor device
KR100753671B1 (en) Method for forming of semiconductor device
KR101095998B1 (en) Method for forming semiconductor device
KR100922550B1 (en) Method of metalization for semiconductor device
KR100922558B1 (en) Metal line of the semiconduct and method for manufacturing the same
KR101030239B1 (en) Method for forming thin film resistor of semiconductor device
KR100562329B1 (en) Method for forming contact and semiconductor device using the same
KR100315849B1 (en) a forming method of a contact for multi-level interconnects
KR100641994B1 (en) Semiconductor device and manufacturing method thereof
KR20010113520A (en) A process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20141119

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20151118

Year of fee payment: 5

FPAY Annual fee payment

Payment date: 20161118

Year of fee payment: 6

FPAY Annual fee payment

Payment date: 20171117

Year of fee payment: 7

FPAY Annual fee payment

Payment date: 20181120

Year of fee payment: 8

FPAY Annual fee payment

Payment date: 20191119

Year of fee payment: 9