JP2006100694A - Mesa-structure semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mesa-structure semiconductor device where reliable electrical insulation is carried out in the mesa-structure semiconductor device having an isolation groove for insulation. <P>SOLUTION: In the mesa-structure semiconductor device, an n<SP>++</SP>type cathode area 2 is formed on the rear surface side of an n<SP>-</SP>type semiconductor wafer 1, a p-type anode area 3 is formed on the front surface side of the wafer 1, and the isolation groove 8 for insulating each element electrically is formed. An SiO<SB>2</SB>film 4 is formed on the wafer 1 so as to extend from the vicinities of the upper end of the groove 8 to its upper parts, and a glass protection film 9 is formed in the groove 8. The upper end of the groove 8 is covered with the SiO<SB>2</SB>film 4 and the glass protection film 9. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a high withstand voltage mesa type semiconductor device such as a high withstand voltage mesa bipolar transistor, a diode, and a MOSFET, and a method for manufacturing the same.

  Mesa-type semiconductor devices are widely used as power semiconductor elements. Conventionally, this type of mesa type high withstand voltage semiconductor device has been manufactured by the following method (for example, see Patent Document 1).

First, p-type impurities are selectively diffused into an n ⁺⁺ type cathode region 2 formed on the surface side of the n ⁻ type semiconductor wafer 1 to form a p-type anode region 3 for each element.

Thereafter, the SiO ₂ film 4 is formed on the semiconductor wafer 1 by using the CVD method (FIG. 2A). Further, an electrode forming opening 5 for connecting to the p-type anode region 3 is formed in the SiO ₂ film 4 by using a photolithography technique and dry etching or etch etching (FIG. 2B).

In addition, among the PN junctions formed by the n ⁺⁺ type cathode region 2 and the p type anode region 3 simultaneously with the electrode forming opening 5, the junction interface is a part where the junction interface reaches the surface of the semiconductor wafer 1. A separation forming opening 7 having a width of 500 μm is formed on the joint 6a.

  Next, a separation groove 8 having a depth of 100 μm or more for separating the PN junction portion 6b is formed inside the separation formation opening 7 by means such as etching (FIG. 2C). With such a depth, a high breakdown voltage characteristic of 1500 V or more can be obtained.

  Thereafter, a glass paste 9a containing glass powder (64% by weight) and a photosensitive material (36% by weight) is applied to the surface of the semiconductor wafer 1 by a spin coating method to a thickness of 30 μm (FIG. 2D). . Thereafter, the glass paste 9a is left in the separation groove 8 by exposure and development.

After that, the wafer 1 is put into a vacuum furnace, heat-treated at about 900 ° C. for 60 minutes under reduced pressure, and fired to form a glass protective film 9 so as to cover the PN junction exposed in the separation groove 8 ( FIG. 2 (e)).
JP 2003-86814 A

  However, the conventional example has the following problems. That is, in the manufacturing method described above, glass paste is applied onto a semiconductor wafer by spin coating, but a deep separation groove is formed in the semiconductor wafer. As the shape of the separation groove is steep on the inclined surface at the upper end, the thickness of the applied glass paste tends to be thin, and when the glass paste is baked, it becomes even thinner due to the shrinkage of the glass and the substrate is exposed. Cause.

  Further, since the glass paste is applied on the semiconductor wafer having large irregularities, air is entrained in the separation groove, and a defect is created in the junction of the semiconductor region, which causes unnecessary dielectric substances to adhere.

  Furthermore, due to the centrifugal force during spin coating, it is difficult to uniformly apply to the left and right contrasts on the inside and outside of the inclined surface of the separation groove, which causes a defective shape of the glass protective film.

  As a result, when a voltage is applied to the formed semiconductor device, a leak current and a discharge are locally generated, resulting in a problem that a breakdown voltage is deteriorated, reliability is lowered, and yield is lowered.

  In addition, the separation groove region where the glass paste is left is 5% or less of the surface area of the semiconductor wafer, and there is a problem that the use efficiency of the paste is low and the cost is high.

  In order to solve such problems, the inventors of the present application have proposed a method of coating and forming glass powder and a glass paste of a photosensitive material by drawing injection by a dispensing method.

  However, there are concerns about the following problems in the method using the dispensing method.

  For example, the separation groove for separating the PN junctions of the semiconductor regions of each element unit needs to have a depth of 100 μm or more in order to obtain a high breakdown voltage of 1500 V or more. It has been found that the slope of the upper end portion becomes steep, and as a result, the thickness of the glass paste tends to be thin even if the dispensing method is used. The glass paste formed in this portion becomes thinner when fired due to the shrinkage of the glass, and the risk of exposing silicon becomes high.

  As a result, when a voltage is applied, a leak current and a discharge are locally generated, which may cause a problem that a breakdown voltage is deteriorated, reliability is lowered, and yield is reduced.

  Therefore, the present invention prevents the thinning of the glass paste at the upper end portion of the separation groove by leaving the oxide film as a mask when the separation groove is opened, and the mesa type semiconductor device having high breakdown voltage and high reliability. An object is to provide a manufacturing method.

In order to solve the above problems, a mesa semiconductor device according to the present invention is a mesa semiconductor device in which a separation groove for electrically insulating a semiconductor substrate is formed, and the separation from the vicinity of the upper end of the separation groove. An insulating film is formed on the semiconductor substrate so as to extend over the upper portion of the groove,
A glass protective film is formed in the separation groove, and an upper end portion of the separation groove is covered with the insulating film and the glass protective film.

  The method for manufacturing a mesa semiconductor device of the present invention includes a step of forming an insulating film on a semiconductor substrate, and a step of forming a first opening for patterning the insulating film to form an isolation groove. Etching the semiconductor substrate under the first opening using the insulating film as a mask to form a separation groove; and selectively drawing and forming a glass paste in the separation groove by a dispenser; And a step of heat-treating the semiconductor substrate to form the glass paste on a glass protective film, wherein in the step of forming the separation groove, the etching of the semiconductor substrate has an isotropic etching component, To do.

  In the step of forming the separation groove, it is preferable that an etching rate of the insulating film is slower than an etching rate of the semiconductor substrate.

  In the step of patterning the insulating film, it is preferable that an electrode forming opening for providing an electrode is simultaneously formed on the semiconductor substrate.

  Preferably, the semiconductor substrate further includes a step of forming a pn junction, and the pn junction is exposed on an inner wall of the separation groove.

  According to the present invention, the insulating film serving as a mask pattern is formed so as to cover the upper end portion of the element isolation groove, and then the glass paste is drawn and formed. A local thinning of the insulating film can be prevented, and a semiconductor device having a high breakdown voltage and high reliability can be realized.

  Furthermore, since the glass paste is formed by the dispensing method, it can be applied uniformly and thickly in the separation groove, and the separation characteristics can be further improved.

  Embodiments of the present invention will be specifically described below with reference to the drawings.

  FIG. 1 is an explanatory diagram of a manufacturing process of a mesa semiconductor device in an embodiment of the present invention.

An n-type impurity such as phosphorus having a higher concentration than the impurity concentration of the semiconductor wafer 1 is thermally diffused from the back surface side of the n ⁻ -type semiconductor wafer 1 having a specific resistance of 60 Ω · cm and a thickness of 300 μm to a diffusion depth of about 180 μm and a surface concentration. An n ⁺⁺ type cathode region 2 of 2 × 10 ²⁰ / cm ³ is formed.

Thereafter, a p-type impurity such as boron having a higher concentration than the impurity concentration of the semiconductor wafer 1 is selectively thermally diffused on the side opposite to the cathode region 2 to have a diffusion depth of 50 μm to 60 μm and a surface concentration of 1 × 10 ¹⁷ / cm. ^Three p-type anode regions 3 are formed for each element.

Then, a SiO ₂ film 4 is deposited on the surface of the semiconductor wafer 1 including the anode region 3 by using the CVD method (FIG. 1A).

Thereafter, the SiO ₂ film 4 is patterned to open a window for the electrode forming opening 5 for connection to the anode region 3. Further, simultaneously with the opening of the electrode forming opening 5, the silicon dioxide film in the isolation groove forming region of each element unit is selectively removed to form the junction isolation forming opening 7 with a width of 500 μm (FIG. 1B). ). At this time, the pn junction 6 is exposed in the junction isolation formation opening 7.

Thereafter, only the electrode forming opening 5 is covered with a mask pattern (not shown), and the pattern and the SiO ₂ film 4 are used as a mask to separate each element into a depth of 100 μm or more and a width of about 500 μm. The separation groove 8 is formed by wet etching. Thereafter, the mask pattern is removed (FIG. 1C). At this time, since the wet etching rate of the SiO ₂ film 4 remaining on the semiconductor wafer 1 is slower than that of silicon, the SiO ₂ film 4 is overhanging at the upper end of the separation groove 8 as shown in FIG. 10 and the upper end of the separation groove 8 is not exposed.

  Next, a glass paste (not shown) in which powder such as powder glass is mixed with a photosensitive substance is drawn and applied to the separation groove 8 of each element unit with a dispenser, and the semiconductor wafer is separated with a width of 500 μm at the junction separation forming opening. Apply to the groove 8.

  Thereafter, the wafer 1 is put into a vacuum furnace, and a glass protective film 9 is formed so as to cover the PN junction 6 exposed in the separation groove by performing a heat treatment for glass baking at about 900 ° C. for 60 minutes under reduced pressure (FIG. 1). (D)).

According to the present embodiment, the SiO ₂ film 4 is left so as to cover the upper end portion of the separation groove 8, and then the glass paste is drawn and formed. Thin film can be prevented, and a semiconductor device having high breakdown voltage and high reliability can be realized.

  Furthermore, since the glass paste is formed by the dispensing method, it can be applied uniformly and thickly in the separation groove, and the separation characteristics can be further improved.

  In this embodiment, the electrode forming opening and the separation forming opening are formed at the same time. However, after forming the separation forming opening first and further forming the separation groove, the electrode forming opening is formed. May be formed.

  In this embodiment mode, the separation groove is formed by wet etching, but may be performed by dry etching or a combination of dry etching and wet etching. In that case, it is necessary to combine isotropic etching instead of complete anisotropic etching. This is because an overhang portion is formed by doing so.

  In the present embodiment, the mesa diode is shown. However, the same effect can be obtained by applying the present invention to a bipolar transistor, a MOS transistor, or the like.

  The mesa semiconductor device of the present invention has a high breakdown voltage and high reliability, and is useful as a semiconductor device for power applications.

Manufacturing process explanatory diagram of a mesa semiconductor device in an embodiment of the present invention Manufacturing process explanatory diagram of mesa type semiconductor device in the prior art

Explanation of symbols

1 n ^- -type semiconductor wafer 2 n ⁺⁺ type cathode region 3 p-type anode region 4 SiO ₂ film 5 electrode formation opening 6, 6a, 6b PN junction 7 separate formation opening 8 separating groove 9 glass protective film 9a Glass paste 10 Overhang part

Claims (5)

A mesa semiconductor device in which a separation groove for electrically insulating a semiconductor substrate is formed,
An insulating film is formed on the semiconductor substrate so as to extend from the vicinity of the upper end of the separation groove to cover the upper portion of the separation groove,
A glass protective film is formed in the separation groove,
The mesa semiconductor device, wherein an upper end portion of the separation groove is covered with the insulating film and the glass protective film. Forming an insulating film on the semiconductor substrate;
Patterning the insulating film to form a first opening for forming a separation groove;
Etching the semiconductor substrate under the first opening using the insulating film as a mask to form a separation groove;
Selectively drawing and forming a glass paste with a dispenser in the separation groove;
And heat treating the semiconductor substrate to form the glass paste on a glass protective film,
A method of manufacturing a mesa semiconductor device, wherein in the step of forming the separation groove, the etching of the semiconductor substrate has an isotropic etching component. 3. The method for manufacturing a mesa semiconductor device according to claim 2, wherein, in the step of forming the isolation groove, an etching rate of the insulating film is made slower than an etching rate of the semiconductor substrate. 4. The method of manufacturing a mesa semiconductor device according to claim 2, wherein in the step of patterning the insulating film, an electrode forming opening for providing an electrode is formed on the semiconductor substrate at the same time. Forming a pn junction in the semiconductor substrate;
5. The method for manufacturing a mesa semiconductor device according to claim 2, wherein the pn junction is exposed on an inner wall of the separation groove.

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