JPH06151896A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent charge generated during breakdown of a voltage clamp diode from being directly captured in a silicon oxide film by forming a conductive layer by burying not to bring a P-N junction surface into contact with a LOCOS edge and not to be exposed to a silicon substrate surface at a position which is a specified depth from the substrate surface. CONSTITUTION:A silicon oxide film 22 is formed by selective oxidation method and a P<+>-type conductive layer 4 is formed simultaneously by activating ion- implanted boron. A silicon oxide film 32 is formed by thermal oxidation method and then boron is ion-implanted at an acceleration energy of 160 to 200keV to form a buried type P<+> conductive layer 44. This is positioned at a depth of about 0.5mum from a surface of a silicon substrate 1. Phosphorus is ion- implanted at an acceleration energy of 100keV and then a resist film is removed. After cleaned, it is thermally treated at 900 to 1000 deg.C for 10 to 30 minutes to form an N<+> type conductive layer 16. Thereby, variation of a clamp voltage can be prevented even if a clamp diode is energized for a long time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a P-N junction type diode.

[0002]

2. Description of the Related Art A conventional semiconductor device having a P-N junction type diode has a structure as shown in FIG. 4 and is obtained by the following manufacturing method. P-type silicon substrate 1
After forming the P ⁺ type conductive layer 4 selectively by ion implantation on the surface, the silicon oxide film where a selective field oxide film immediately above P ⁺ conductive layer 4 by a selective oxidation method 22
To form.

Next, a silicon oxide film serving as a gate insulating film and a polycrystalline silicon film 5 serving as a gate electrode are formed to form a peripheral MOS transistor, and the surface of the polycrystalline silicon film 5 is further oxidized. Then, by ion implantation using the photoresist film and the silicon oxide film 22 as a mask, the N ⁺ -type conductive layers 6 and 16 are formed in a self-aligned manner with respect to the silicon oxide film 22 and the polycrystalline silicon film 5.
Then, the silicon oxide film 22 is formed by an ion implantation method using the photoresist film and the silicon oxide film 22 as a mask.
On the other hand, the P ^{+ type} conductive layer 7 is formed in a self-aligned manner and heat treatment is performed. Next, BP as an interlayer insulating film is formed by the CVD method.
The SG film 8 is deposited on the entire surface by about 1.0 μm, and a contact hole is opened. Next, a metal wiring made of a laminated film of the polycrystalline silicon film 9 and the aluminum film 10 is formed to form a wiring for the PN junction diode. Then, in order to protect the surface of the semiconductor device, the PSG film 11 is formed on the entire surface by the CVD method.
Was deposited, a heat treatment was performed, and a silicon nitride film 12 was deposited on the entire surface by a CVD method to complete a conventional semiconductor device.

[0004]

In the semiconductor device manufactured by the conventional manufacturing method, the PN junction is formed at the locos edge of the silicon oxide film 22 which is the field oxide film, and the locos edge is formed at the time of forming the locos edge. A large number of charge trap levels are likely to be generated in the oxide film due to mechanical stress, and at the same time, this portion is a transition region of the oxide film thickness.
The oxide film near the N junction becomes extremely thin. Therefore, P
In a voltage clamp diode that is used in a state where the avalanche breakdown occurs at the N-junction, the charge generated during the avalanche breakdown is generated by the silicon oxide film 22.
It is trapped in the charge trap level inside. At the same time, in the transition region of the oxide film thickness of the silicon oxide film 22 and the region where the oxide film thickness is thin, the generated electric charges are generated by the silicon oxide film 22.
Through a thin film of the silicon oxide film 22 by a tunnel phenomenon, and is injected and trapped in the charge trap level at the interface between the silicon oxide film 22 and the BPSG film 8 which is the interlayer insulating film. As a result, the surface charge density of the P ⁺ conductive layer 4 below the trapped charges changes, and the clamp voltage becomes 1 with the energization time of the clamp diode.
It has a major drawback that it changes and rises by about 0% to 30%.

Further, in the semiconductor device obtained by this manufacturing method, since the PN junction surface has a shape exposed on the surface of the silicon substrate, the influence of charges due to contamination of the upper insulating film of the PN junction surface, etc. Also has a large fluctuation factor and is disadvantageous in terms of reliability.

An object of the present invention is a voltage clamp diode such as used in avalanche breakdown mode in a PN junction diode having a semiconductor surface contact, and as a result, charges generated during breakdown are trapped in an insulating film above a junction surface. It is to provide a highly reliable semiconductor device that can prevent the clamp voltage from changing.

[0007]

According to a method of manufacturing a semiconductor device of the present invention, an impurity having the same conductivity type is selectively introduced onto a semiconductor substrate, and a field oxide film is formed by a selective oxidation method after that. 150 to 300 keV by a step of forming a gate electrode of a MOS transistor by an ion implantation method with an impurity of the same conductivity type as the semiconductor substrate.
Ions are applied with an acceleration energy of 1 to form a buried type impurity layer at a depth of about 0.2 to 0.5 μm from the surface of the semiconductor substrate. Next, a step of selectively forming an impurity of the same conductivity type as the impurity layer as an electrode extraction diffusion layer of the buried layer, and a step of forming an impurity of a conductivity type opposite to that of the buried impurity layer in the buried impurity layer And a process for selectively performing heat treatment at 900 to 1000 ° C. for 10 to 30 minutes.

Here, the depth of the buried impurity layer is 0.2 μm.
When m or less, the impurity concentration peak value is
As a result of being exposed to the semiconductor substrate surface, the PN junction surface is exposed to the semiconductor substrate surface.

When the thickness is 0.5 μm or more, the diffusion layer for taking out the electrode of the impurity layer needs to be pushed deeply, and a steep concentration gradient of the PN junction layer cannot be obtained.

Further, when the impurity layer is pushed in from the surface of the semiconductor substrate by the thermal diffusion method, the impurity concentration is extremely lowered and it becomes difficult to secure a desired Zener voltage.

As for the heat treatment after the formation of impurities, if the heat treatment is insufficient, fine crystal defects in the impurity layer formed by ion implantation cannot be recovered and a PN junction leak occurs.

When the heat treatment amount is large, a desired impurity layer concentration gradient cannot be obtained.

[0013]

The present invention will be described below with reference to the drawings. 1A to 1D are cross-sectional views shown in order of steps for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 1A, a silicon oxide film 2 of about 100 nm is formed on the surface of a P-type silicon substrate 1 by a thermal oxidation method, and a film thickness of 100 nm is formed by a low pressure CVD method.
The silicon nitride film 3 is deposited to a certain extent, and the silicon nitride film 3 is patterned by the photolithography method.

Next, as shown in FIG. 1B, boron is selectively ion-implanted to remove the photoresist film, and then the silicon oxide film 22 which is a field oxide film is formed by a selective oxidation method.
Simultaneously with the formation of the above, the ion-implanted boron is activated to form the P ^{+ type} conductive layer 4.

Subsequently, as shown in FIG. 1C, after removing the silicon nitride film 3 and the silicon oxide film 2, the peripheral MO film is removed.
A silicon oxide film 32 to be a gate insulating film for an S transistor is formed by a thermal oxidation method, and a polycrystalline silicon film 5 to be a gate electrode for a peripheral MOS transistor is formed by CVD.
Method, photolithography method, and the surface of the polycrystalline silicon film 5 is oxidized to form a silicon oxide film 42.
Next, the aluminum film 10 is formed to a thickness of 1.5 μm by a sputtering method.
After depositing about m, openings are selectively formed by photolithography. Continuously, 1 ion of boron was obtained by the ion implantation method.
2-4 × 10 ¹⁴ with acceleration energy of 60-200 keV
Ions are implanted at about atm / cm ² to form a buried P ⁺ conductive layer 44.

Next, as shown in FIG. 1 (d), a photoresist 50 is ion-implanted at an acceleration energy of 30 to 50 keV, and ions of 3 to 9 × 10 ¹⁵ atm / cm ² are implanted to form a P ⁺ -type conductivity. Form the layer 7.

Subsequently, as shown in FIG. 1 (e), phosphorus is ion-implanted using a photoresist film as a mask material at an acceleration energy of 100 keV at 3 to 9 × 10 ¹⁵ atm.
/ Cm ² ions are implanted, the photoresist film is removed, and after cleaning, heat treatment is performed at 900 to 1000 ° C. for 10 to 30 minutes to form the N ^{+ type} conductive layer 16. Furthermore, CV
The BPSG film 8 serving as an interlayer insulating film is formed in a thickness of 0.8
Deposit about 1.2 μm.

Next, as shown in FIG. 1F, a contact hole is opened by photolithography, and then a laminated film of a polycrystalline silicon film 9 and an aluminum film 10 is formed by CVD and sputtering, and photolithography is performed. This laminated film is patterned by a method to form metal wiring, and PN
The junction diode and the wiring of the MOS transistor are formed and heat treatment is performed at a temperature of 400 to 500 ° C.

Thereafter, as shown in FIG. 1G, in order to protect the surface of the semiconductor device, a PSG film 11 is deposited on the entire surface by a CVD method, and a silicon nitride film 12 is further deposited on the entire surface by a CVD method. The semiconductor device of the invention is completed.

As described above, in the semiconductor device of the present invention, the concentration profile of each PN junction is shown in FIG.
And the peak concentration of the P ⁺ type conductive layer is 5 to 8
It is located at a depth of about 0.5 μm from the surface of the silicon substrate at × 10 ¹⁸ atm / cm ³ . Further, the N ⁺ type conductive layer pressed from the surface of the silicon substrate by the thermal diffusion method forms a PN junction with an impurity concentration of about 10 ¹⁷ to 10 ¹⁸ atm / cm ³ , and the junction depth is from the surface of the silicon substrate. It is configured to have a depth of 0.3 to 0.4 μm, and the PN junction is separated from the locos edge, which makes it possible to configure an ideal PN diode.

Therefore, even in a voltage clamp diode which is used in the avalanche breakdown state at the PN junction, the charges generated during the avalanche breakdown are not directly trapped in the silicon oxide film. It has a great advantage that the clamp voltage does not fluctuate even when energized and operates stably.

FIG. 2 is a sectional view of a semiconductor device for explaining the second embodiment of the present invention.

The semiconductor device manufacturing method of the second embodiment is
Since it is almost the same as the first embodiment, only the differences will be described. As shown in FIG. 2, after the buried P ⁺ type conductive layer is formed by the ion implantation method, the second layer is formed using the aluminum film as a mask.
As a buried layer of phosphorus, phosphorus of 350 to 4 is formed by an ion implantation method.
2-4 × 10 ¹⁴ atm / with acceleration energy of 00 keV
Ion implantation of about cm ² to form an N ^{+ type} conductive layer 45,
Both of the impurity layers forming the PN junction are buried from the surface of the silicon substrate to a depth of 0.3 to 0.4 μm.
In the present embodiment and the second embodiment, it is possible to adjust both impurity concentration peak values by the ion implantation only by the acceleration energy of the ion implantation, so that there is a great advantage that a desired Zener voltage can be easily obtained. Have.

[0025]

As described above, in the semiconductor device manufactured by the present invention, the PN junction surface has a poor oxide film quality, does not come into contact with the locos edge having a high charge trapping level, and
It is not exposed on the surface of the silicon substrate and is embedded at a depth of 0.2 to 0.5 μm from the surface of the silicon substrate. Therefore, even the voltage clamp diode used in the avalanche breakdown state breaks. As a result that the charges generated at the time of down are not captured directly in the silicon oxide film, the clamp voltage does not fluctuate even when the clamp diode is energized for a long time. When the time variation was measured, the voltage change was 0 to 2%, which was a great improvement over the conventional semiconductor device.

Further, in this device, since the PN junction surface is embedded in the silicon substrate, the quality of the insulating film of the upper layer of the PN junction during the manufacturing process (for example, the influence of the charged charges in the plasma nitride film, contamination, etc.). ), A stable Zener voltage could be obtained.

Furthermore, it has become possible to provide a semiconductor device which has a good long-term reliability of the semiconductor device, uniform characteristics, and high reliability.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device shown in the order of steps for explaining an embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device for explaining a second embodiment of the present invention.

FIG. 3 is an impurity concentration profile in the first example of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor element for explaining a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 P-type silicon substrate 2, 22, 32, 42 Silicon oxide film 3, 12 Silicon nitride film 4, 7 P ^{+ type} conductive layer 5, 9 Polycrystalline silicon film 16 N ^{+ type} conductive layer 8 BPSG film 10 Aluminum film 44 Embedded P ^{+ type} conductive layer 45 Embedded N ^{+ type} conductive layer 50 Photoresist film

Claims (1)

[Claims] 1. In a method of manufacturing a semiconductor device in which a junction diode and a MOS transistor are formed on the same semiconductor substrate, an impurity having the same conductivity type is selectively introduced onto the semiconductor substrate, and then a field is formed by a selective oxidation method. A step of forming an oxide film, a step of forming a gate electrode of a MOS transistor, and an impurity of the same conductivity type as the substrate are selectively ion-implanted by an ion implantation method at an acceleration energy of 150 to 300 keV to obtain a semiconductor substrate. A step of forming an embedded impurity layer at a depth of about 0.2 to 0.5 μm from the surface, a step of selectively forming an impurity of the same conductivity type as the impurity layer, and the embedded impurity layer Impurities of opposite conductivity type are selectively formed, and 900 to 100
A step of performing heat treatment at 0 ° C. for 10 to 30 minutes.