JP2020004755A - Method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

To provide a manufacturing method capable of manufacturing a highly-reliable silicon carbide semiconductor device serving as a vertical transistor using a silicon carbide semiconductor.SOLUTION: A method for manufacturing a silicon carbide semiconductor device serving as a vertical transistor comprises the steps of: depositing a polysilicon 151a on a silicon carbide epitaxial substrate including a gate trench 130 with an oxidized surface and embedding the gate trench 130 with the oxidized surface by the polysilicon 151a; removing a polysilicon 151a in a region except the gate trench 130 by chemical mechanical polishing; and oxidizing the polysilicon 151a in the gate trench 130 to a deeper position than a surface 11a of the silicon carbide epitaxial substrate.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device.

  Silicon carbide has a wider band gap than silicon which has been widely used in semiconductor devices in the past, and is therefore used in high breakdown voltage semiconductor devices and the like. In a semiconductor device using such silicon carbide, there is a so-called vertical transistor in which a source electrode is formed on a first surface and a drain electrode is formed on a second surface from the viewpoint of withstand voltage and the like.

JP-A-135-135860

  In a vertical transistor, a trench serving as a gate trench is formed on the surface of a silicon carbide epitaxial substrate, a gate insulating film is formed inside the gate trench, and a polysilicon is formed on the gate insulating film so as to fill the gate trench. A gate electrode is formed. In a vertical transistor having such a structure, breakdown may occur in the vicinity of the end of the gate electrode when a voltage is applied due to manufacturing variations or the like.

  Therefore, a highly reliable vertical transistor using a silicon carbide semiconductor is required.

  According to one aspect of the present embodiment, a method for manufacturing a silicon carbide semiconductor device to be a vertical transistor includes: forming a polysilicon film on a silicon carbide epitaxial substrate having a gate trench whose surface is oxidized; Burying the formed gate trench with polysilicon. Further, the method includes a step of removing polysilicon in a region excluding the gate trench by chemical mechanical polishing, and a step of oxidizing the polysilicon in the gate trench to a position deeper than the surface of the silicon carbide epitaxial substrate.

  According to the present disclosure, it is possible to provide a method of manufacturing a silicon carbide semiconductor device capable of manufacturing a highly reliable vertical transistor.

FIG. 1 is a structural diagram of a silicon carbide semiconductor device. FIG. 2 is an explanatory diagram of the structure of the silicon carbide semiconductor device. FIG. 3 is an explanatory diagram of the structure of the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 4 is a process diagram (1) of a method for manufacturing a silicon carbide semiconductor device according to an embodiment of the present disclosure. FIG. 5 is a process diagram (2) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 6 is a process diagram (3) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 7 is a process diagram (4) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 8 is a process diagram (5) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 9 is a process diagram (6) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 10 is a process diagram (7) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 11 is a process diagram (8) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 12 is a process diagram (9) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 13 is a process diagram (10) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 14 is a process diagram (11) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 15 is a process diagram (12) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 16 is a process diagram (13) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 17 is a process diagram (14) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 18 is a process diagram (15) of the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present disclosure.

  An embodiment for implementing the present invention will be described below.

[Description of Embodiment of the Present Disclosure]
First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements have the same reference characters allotted, and the same description will not be repeated.

  [1] A semiconductor device according to an embodiment of the present disclosure is a method for manufacturing a silicon carbide semiconductor device to be a vertical transistor, wherein polysilicon is formed on a silicon carbide epitaxial substrate having a gate trench whose surface is oxidized. Embedding the gate trench having a film and an oxidized surface with the polysilicon, removing the polysilicon in a region excluding the gate trench by chemical mechanical polishing, and carbonizing the polysilicon in the gate trench. Oxidizing to a position deeper than the surface of the silicon epitaxial substrate.

  In a vertical silicon carbide transistor, a gate trench is formed and a gate electrode is formed by filling the gate trench with polysilicon. However, due to manufacturing variations or the like, a part of the gate electrode may be formed on the silicon carbide semiconductor layer at the edge of the gate trench with the insulating film interposed therebetween. It has been found from the experience of the inventor that in the silicon carbide transistor in such a state, when a high voltage is applied, dielectric breakdown or the like is likely to occur and reliability is likely to decrease.

  The present disclosure oxidizes polysilicon for forming a gate electrode in a gate trench to a position deeper than the surface of a silicon carbide epitaxial substrate in order to reliably prevent such a breakdown from occurring. This can prevent a part of the gate electrode from climbing over the silicon carbide semiconductor layer from the edge of the gate trench, and can improve reliability.

  [2] The silicon carbide epitaxial substrate has a first conductivity type layer on the front surface side of the silicon carbide epitaxial substrate and a second conductivity type layer different from the first conductivity type layer, which is deeper than the first conductivity type layer. A conductive type layer, wherein in the oxidizing step, the polysilicon in the gate trench is oxidized to a position shallower than an interface between the first conductive type layer and the second conductive type layer. I do.

  [3] The gate trench is formed deeper than the second conductivity type layer.

  [4] a step of forming an oxide film on the surface of the silicon carbide epitaxial substrate and forming a nitride film on the oxide film; and forming an oxide film and a nitride film in a region where the gate trench is formed. Removing the silicon carbide epitaxial substrate at the opening of the oxide film and the nitride film from the surface to form a gate trench, and forming a gate trench. The polysilicon is formed in the gate trench and on the nitride film, and the removal of the polysilicon by chemical mechanical polishing is performed until the surface of the nitride film is exposed.

  [5] The thickness by which the polysilicon is oxidized is greater than the sum of the thickness of the oxide film and the thickness of the nitride film.

[Details of Embodiment of the Present Disclosure]
Hereinafter, an embodiment of the present disclosure (hereinafter, referred to as “the present embodiment”) will be described in detail, but the present embodiment is not limited thereto.

  First, description will be given on a case where a transistor which is a so-called vertical silicon carbide semiconductor device may be broken near a portion where a gate electrode is formed. In a vertical transistor, a groove serving as a gate trench is formed on the surface of a silicon carbide epitaxial substrate, a gate insulating film is formed inside the gate trench, and polysilicon is formed on the gate insulating film. Fill the trench. Thereafter, by removing the polysilicon excluding the polysilicon buried in the gate trench by etch back or the like, a gate electrode is formed from the polysilicon in the gate trench. However, when the edge of the gate trench is covered with a part of the edge of the gate electrode via the insulating film after the gate electrode is formed due to a variation in an etching amount in an etch back or a misalignment with a base in lithography. There is.

  Specifically, in the vertical transistor, as shown in FIG. 1, a first n-type layer 21, a p-type layer 22, and a second n-type layer 21 are formed on first surface 10 a of silicon carbide single crystal substrate 10. An n-type layer 23 is formed in order. Further, by removing the second n-type layer 23, the p-type layer 22, and the first n-type layer 21, a gate trench having a V-shaped cross section is formed. The second n-type layer 23, the p-type layer 22, and a part of the first n-type layer 21 are exposed. Further, the side wall of the gate trench is covered with the gate insulating film 40, and the inside of the gate trench is buried with polysilicon formed on the gate insulating film 40 to form the gate electrode 51. .

  When the gate electrode 51 is formed, the polysilicon is removed by etch back using RIE (Reactive Ion Etching) or the like except for the polysilicon inside the gate trench. However, it is extremely difficult to etch back the polysilicon uniformly over the entire wafer. For this reason, as shown in FIG. 2, in a region of the wafer, a part of the end of the gate electrode 51 is formed on the second n-type layer 23 at the edge of the gate trench via the gate insulating film 40. You may be in a state of riding.

  Note that a high-concentration p-type region 24 having a high impurity concentration is formed in a region away from the gate trench by ion-implanting a p-type impurity element, and the second n-type layer 23 and the high-concentration On a part of the p-type region 24, a source electrode 52 is formed. The source electrode 52 is formed of a Ni film, and the second n-type layer 23 and the high concentration p-type region 24 are formed of a silicon carbide semiconductor and contain Si. And Si are alloyed to form a NiSi alloy layer. With the NiSi alloy layer formed in this manner, the contact resistance between source electrode 52 and second n-type layer 23 of the silicon carbide semiconductor layer can be reduced. Drain electrode 53 is formed on second surface 10b of silicon carbide single crystal substrate 10 opposite to first surface 10a.

  As described above, when the etch back by RIE or the like is insufficient when the gate electrode 51 is formed, or when the overlay is misaligned with the base in lithography, as shown in FIGS. A part of the end of the electrode 51 is put on the second n-type layer 23 at the edge of the gate trench via the gate insulating film 40. That is, a part of the end of gate electrode 51 is located above the surface of the silicon carbide semiconductor layer, and is in a state of running over gate insulating film 40. When a high voltage is applied to such a transistor, electric field concentration occurs in a region surrounded by a dashed line 2A in FIG. 2, and the transistor may be destroyed.

  The first n-type layer 21 is a layer in which an n-type impurity element is doped at a relatively low concentration, and is an n-type drift layer. The p-type layer 22 is a p-type body layer doped with an impurity element to be p. The second n-type layer 23 is an n-type layer in which the n-type impurity element is doped at a higher concentration than the first n-type layer 21.

  In the vertical transistor, when a predetermined voltage is applied to the gate electrode 51, a channel is formed in a region of the p-type layer 22 near the gate insulating film 40, and the first n-type layer 21 and the second n-type Conduction is established between the layer 23. Thus, a current flows between the source electrode 52 and the drain electrode 53, and the semiconductor device is turned on. When a predetermined voltage is not applied to the gate electrode 51, no channel is formed in the p-type layer 22, and no current flows between the source electrode 52 and the drain electrode 53, so that the transistor is turned off. Become.

(Silicon carbide semiconductor device)
Next, a silicon carbide semiconductor device serving as a vertical transistor according to the present embodiment will be described. In the semiconductor device according to the present embodiment, as shown in FIG. 3, the position of upper surface 151f of gate electrode 151 is lower than surface 11a of the silicon carbide semiconductor layer, and p-type layer 22 and second n-type It is formed so as to be higher than the interface 23 f with the layer 23. The surface 11a of the silicon carbide semiconductor layer is a surface serving as an interface between a silicon carbide semiconductor layer described later and a silicon oxide film described later formed on the silicon carbide semiconductor layer. By forming the gate electrode 151 in this manner, even when a high voltage is applied to the transistor, electric field concentration at the end of the gate electrode 151 can be prevented, and the transistor can be prevented from being destroyed. Performance can be improved.

(Method of Manufacturing Silicon Carbide Semiconductor Device)
Next, a method for manufacturing the silicon carbide semiconductor device according to the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 4, p-type layer 22 is formed by ion-implanting Al from surface 11a of silicon carbide epitaxial layer 11 on silicon carbide single crystal substrate 10, and shallow surface 11a is formed. The second n-type layer 23 is formed by ion-implanting P into the region. Further, a high concentration p-type region 24 is formed by ion-implanting Al which is a p-type impurity element into a part of the second n-type layer 23 and the p-type layer 22. In the present application, a substrate in which silicon carbide epitaxial layer 11 as a silicon carbide semiconductor layer is formed on silicon carbide single crystal substrate 10 may be referred to as a silicon carbide epitaxial substrate. Therefore, surface 11a of silicon carbide epitaxial layer 11 is also the surface of the silicon carbide epitaxial substrate.

Second n-type layer 23 is formed to a region at a predetermined depth from surface 11a of silicon carbide epitaxial layer 11 by ion-implanting P, which is an n-type impurity element. The p-type layer 22 is formed by ion-implanting Al serving as an impurity element that becomes p-type, and is formed in a region deeper than the second n-type layer 23. The silicon carbide epitaxial layer 11 is doped with P, which is an n-type impurity element, at a concentration of about 1 × 10 ¹⁶ cm ⁻³ . Therefore, in silicon carbide epitaxial layer 11, a region excluding second n-type layer 23 and p-type layer 22 formed by ion implantation becomes first n-type layer 21.

Next, as shown in FIG. 5, a silicon oxide film 161 is formed on the surface 11a of the silicon carbide epitaxial layer 11, that is, on the surfaces of the second n-type layer 23 and the high concentration p-type region 24. A silicon nitride film 162 is formed over the film 161. Specifically, silicon oxide epitaxial film 11 is thermally oxidized from surface 11a to form silicon oxide film 161. The silicon oxide film 161 is formed by thermal oxidation heated to a temperature of 1350 ° C. in an oxygen atmosphere, and the thickness of the formed silicon oxide film 161 is 50 nm to 80 nm. Thereby, surface 11 a of silicon carbide epitaxial layer 11 recedes to the interface with silicon oxide film 161. The silicon nitride film 162 is formed on the silicon oxide film 161 by using a mixed gas of SiH ₂ Cl ₂ and NH ₃ as a source gas by low-pressure CVD (chemical vapor deposition). The thickness of the formed silicon nitride film 162 is 80 nm to 120 nm.

Next, as shown in FIG. 6, an opening 162a is formed in the silicon nitride film 162, and an opening 161a is formed in the silicon oxide film 161. Openings 161a and 162a are formed in silicon carbide epitaxial layer 11 in regions where gate trenches are to be formed. Specifically, a photoresist is applied on the silicon nitride film 162 by a spin coater or the like, and is exposed and developed by an exposure device, so that an opening is formed in a region where the opening 161a and the opening 162a are formed. (Not shown) is formed. Thereafter, in the opening of the resist pattern, an opening 162a is formed by removing the silicon nitride film 162 by RIE, and an opening 161a is formed by removing the silicon oxide film 161. 11 is exposed. The gas used for RIE is a mixed gas of CF ₄ , CHF ₃ , and Ar, which is kept until the silicon oxide film 161 is completely removed at the opening of the resist pattern. Thereafter, the resist pattern (not shown) is removed by ashing using oxygen gas, and further, sulfuric acid peroxide cleaning and RCA cleaning are performed.

  Next, as shown in FIG. 7, the gate trench 130 is formed by removing the silicon carbide epitaxial layer 11 in the openings 161a and 162a of the silicon oxide film 161 and the silicon nitride film 162. By forming the gate trench 130 in this manner, a part of the second n-type layer 23, the p-type layer 22, and a part of the first n-type layer 21 are exposed on the side wall 130a of the gate trench 130. Gate trench 130 is formed to a depth of 1.2 μm to 1.4 μm from surface 11 a of silicon carbide epitaxial layer 11, and is formed to a position deeper than p-type layer 22.

Next, as shown in FIG. 8, the silicon oxide film 41 is formed by oxidizing the surface of the silicon carbide exposed in the gate trench 130, and is further formed on the silicon oxide film 41 and the silicon nitride film 162. Then, a polysilicon film 141a is formed. Specifically, by heating to a temperature of 1100 ° C. to 1350 ° C. in a gas containing oxygen and nitrogen, the surface of silicon carbide exposed in gate trench 130 is oxidized to form silicon oxide film 41. . The thickness of the silicon oxide film 41 thus formed is 55 nm to 60 nm. Thereafter, a polysilicon film 141a is formed on the silicon oxide film 41 and the silicon nitride film 162 by low-pressure CVD. The polysilicon film 141a is formed by supplying SiH ₄ and H ₂ into a chamber of a CVD apparatus and forming the film at a film formation temperature of 600 ° C. to 650 ° C. The polysilicon film 141a thus formed has a thickness of 45 nm to 65 nm.

  Next, as shown in FIG. 9, a resist pattern 163 is formed on the polysilicon film 141a on the bottom surface 130b of the gate trench 130. Specifically, a resist is applied on the polysilicon film 141a by a spin coater or the like and cured, and then the resist is removed by RIE or the like by etch back. Thus, a resist pattern 163 having a height of 0.2 μm to 0.4 μm is formed on the polysilicon film 141 a on the bottom surface 130 b of the gate trench 130. In this etch back, oxygen gas is used, and the polysilicon exposed at the time of the etch back is not etched.

Next, as shown in FIG. 10, the exposed polysilicon film 141a is removed, leaving the polysilicon film 141a on the bottom surface 130b of the gate trench 130, and further, the resist pattern 163 is removed. Specifically, the polysilicon film 141a in which the surface of the region where the resist pattern 163 is not formed is exposed is removed by RIE using a mixed gas of SF ₆ , Ar, and O ₂ . Thereafter, the resist pattern 163 is removed by ashing using oxygen gas, and further, sulfuric acid peroxide cleaning and RCA cleaning are performed.

  Next, as shown in FIG. 11, on the bottom surface 130b of the gate trench 130, the exposed silicon oxide film 41 is removed while leaving the silicon oxide film 41 covered with the polysilicon film 141a. Specifically, the silicon oxide film 41 whose surface not covered by the polysilicon film 141a is exposed is removed by wet etching using hydrofluoric acid. Thereby, a part of the second n-type layer 23, the p-type layer 22, and a part of the first n-type layer 21 are exposed on the side wall 130a of the gate trench 130. Thereafter, sulfuric acid peroxide cleaning and RCA cleaning are performed.

  Next, as shown in FIG. 12, the polysilicon film 141a on the bottom surface 130b of the gate trench 130 and the silicon carbide on the side wall 130a of the gate trench 130 are oxidized to form a silicon oxide film 141 and a silicon oxide film 142. . Specifically, it is heated to a temperature of 1100C to 1350C in a gas containing oxygen and nitrogen. As a result, the polysilicon film 141a on the bottom surface 130b of the gate trench 130 is oxidized to form a silicon oxide film 141, and the silicon carbide surface on the side wall 130a of the gate trench 130 is oxidized to form a silicon oxide film 142. . The silicon oxide film 141 and the silicon oxide film 142 thus formed are integrated with the silicon oxide film 41, so that the gate insulating film 40 is formed.

Next, as shown in FIG. 13, the gate trench 130 is buried by forming a conductive polysilicon film 151a doped with an impurity element on the entire surface. The polysilicon film 151a is formed by supplying SiH ₄ , N ₂ , and PH ₃ into a chamber of a CVD apparatus and forming the film at a temperature of 550 ° C. to 600 ° C. The thickness of the formed polysilicon film 151a is 1.0 μm to 1.5 μm. In the gate trench 130, the polysilicon film 151 a is formed on the gate insulating film 40 and the gate trench 130 is buried.

  Next, as shown in FIG. 14, the polysilicon film 151a is removed by CMP (chemical mechanical polishing) except for the polysilicon film 151a embedded in the gate trench. The removal of the polysilicon film 151a by CMP is performed until the surface of the silicon nitride film 162 is exposed. When the surface of the silicon nitride film 162 is exposed, the removal of the polysilicon film 151a is stopped. As a result, the polysilicon film 151a buried only in the gate trench 130 remains. CMP can remove the polysilicon film 151a more uniformly than etch back. In addition, silicon nitride makes it easier to detect the end point by CMP than silicon oxide. Therefore, when removing the polysilicon film 151a by CMP, it is preferable that the silicon nitride film 162 is formed. Thereafter, sulfuric acid peroxide cleaning and RCA cleaning are performed.

  Next, as shown in FIG. 15, the exposed surface of the polysilicon film 151a is oxidized to form a silicon oxide film 164. Specifically, the exposed polysilicon film 151a is thermally oxidized from the surface at a temperature of 900 ° C. in an oxygen atmosphere to form the silicon oxide film 164. The silicon oxide film 164 is formed to a thickness of about 200 nm, and the gate electrode 151 is formed by the remaining polysilicon film 151a.

  In this state, the thickness of the silicon oxide film 161 is 50 nm to 80 nm, and the thickness of the silicon nitride film 162 is 30 nm to 70 nm. Therefore, the sum of the thickness of the silicon oxide film 161 and the thickness of the silicon nitride film 162 is 80 nm to 150 nm, and the silicon oxide film 164 is formed thicker. Therefore, the upper surface 151f of gate electrode 151, that is, the position of the interface between gate electrode 151 and silicon oxide film 164 is lower and deeper than surface 11a of the silicon carbide epitaxial layer. Further, it is higher and shallower than the interface 23f between the p-type layer 22 and the second n-type layer 23. If the position of the upper surface 151f of the gate electrode 151 does not reach this position at one time, the subsequent silicon oxide film 164 is removed, and then the thermal oxidation of the polysilicon film 151a is repeated.

  Next, as shown in FIG. 16, the silicon nitride film 162 is removed. Specifically, since the silicon nitride film 162 is slightly oxidized during the thermal oxidation of the polysilicon film 151a, the silicon nitride film 162 is removed using hydrofluoric acid and then hot phosphoric acid. Thereafter, sulfuric acid peroxide cleaning and RCA cleaning are performed.

  Next, as shown in FIG. 17, an interlayer insulating film 170 is formed on the exposed silicon oxide films 161 and 164. Specifically, an interlayer insulating film 170 is formed on the silicon oxide films 161 and 164 by forming a silicon oxide film having a thickness of 1 μm by CVD.

  Next, as shown in FIG. 18, a source electrode 52 and a drain electrode 53 are formed. Specifically, a photoresist is coated on the interlayer insulating film 170, and is exposed and developed by an exposure device, thereby forming a region including a boundary between the second n-type layer 23 and the high-concentration p-type region 24. A resist pattern (not shown) having an opening is formed immediately above the resist pattern. Thereafter, the interlayer insulating film 170 in the opening of the resist pattern is removed by RIE or the like until the surfaces of the second n-type layer 23 and the high-concentration p-type region 24 are exposed. Form. Thereafter, after removing a resist pattern (not shown) by ashing using oxygen gas or the like, a metal film is formed, and the source electrode 52 is formed by filling the opening of the interlayer insulating film 170. The source electrode 52 thus formed is in contact with the second n-type layer 23 and the high-concentration p-type region 24, and performs a heat treatment as needed. Further, a drain electrode 53 is formed on second surface 10b of silicon carbide single crystal substrate 10 by forming a metal film by sputtering or the like.

  Through the above steps, the silicon carbide semiconductor device according to the present embodiment can be manufactured. As shown in FIG. 3, the position of upper surface 151 f of gate electrode 151 is lower and deeper than surface 11 a of the silicon carbide semiconductor layer, and p It is higher and shallower than the interface 23f between the mold layer 22 and the second n-type layer 23. By forming the gate electrode 151 in this manner, even when a high voltage is applied to the transistor, electric field concentration can be prevented, the transistor can be prevented from being damaged, and reliability can be improved. .

  As described above, the embodiments have been described in detail. However, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope described in the claims.

Reference Signs List 10 silicon carbide single crystal substrate 10a first surface 10b second surface 11 silicon carbide epitaxial layer 11a surface 21 first n-type layer 22 p-type layer 23 second n-type layer 23f interface 24 high-concentration p-type region 40 Gate insulating film 41 Silicon oxide film 51 Gate electrode 52 Source electrode 53 Drain electrode 130 Gate trench 130a Side wall 130b Bottom surface 141 Silicon oxide film 141a Polysilicon film 142 Silicon oxide film 151 Gate electrode 151a Polysilicon film 151f Top surface 161 Silicon oxide film 161a Opening Portion 162 Silicon nitride film 162a Opening 163 Resist pattern 164 Silicon oxide film 170 Interlayer insulating film

Claims (5)

A method for manufacturing a silicon carbide semiconductor device to be a vertical transistor,
Forming a polysilicon film on a silicon carbide epitaxial substrate having a gate trench whose surface is oxidized, and embedding the gate trench whose surface is oxidized with the polysilicon;
Removing polysilicon by chemical mechanical polishing in the region excluding the gate trench;
Oxidizing the polysilicon in the gate trench to a position deeper than the surface of the silicon carbide epitaxial substrate;
A method for manufacturing a silicon carbide semiconductor device having: The silicon carbide epitaxial substrate has a first conductivity type layer on the surface side of the silicon carbide epitaxial substrate and a second conductivity type layer different from the first conductivity type, which is deeper than the first conductivity type layer. And a layer,
2. The silicon carbide semiconductor device according to claim 1, wherein in the oxidizing step, polysilicon in the gate trench is oxidized to a position shallower than an interface between the first conductivity type layer and the second conductivity type layer. 3. Manufacturing method.   3. The method of manufacturing a silicon carbide semiconductor device according to claim 2, wherein said gate trench is formed deeper than said second conductivity type layer. The gate trench,
Forming an oxide film on the surface of the silicon carbide epitaxial substrate and forming a nitride film on the oxide film;
Removing an oxide film and a nitride film in a region where the gate trench is formed, and forming an opening;
Removing the silicon carbide epitaxial substrate in the openings of the oxide film and the nitride film from the surface to form a gate trench;
Formed by
The polysilicon is formed in the gate trench and on the nitride film,
4. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein removal of polysilicon by chemical mechanical polishing is performed until a surface of the nitride film is exposed. 5.   5. The method of manufacturing a silicon carbide semiconductor device according to claim 4, wherein a film thickness at which said polysilicon is oxidized is larger than a sum of a film thickness of said oxide film and a film thickness of said nitride film.

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