JP2006086246A - Mounting structure of semiconductor chip - Google Patents

Mounting structure of semiconductor chip Download PDF

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Publication number
JP2006086246A
JP2006086246A JP2004267898A JP2004267898A JP2006086246A JP 2006086246 A JP2006086246 A JP 2006086246A JP 2004267898 A JP2004267898 A JP 2004267898A JP 2004267898 A JP2004267898 A JP 2004267898A JP 2006086246 A JP2006086246 A JP 2006086246A
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semiconductor chip
mounting structure
thermal conductivity
chip mounting
close contact
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Japanese (ja)
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Hideki Nagayama
英樹 永山
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Yokogawa Electric Corp
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Yokogawa Electric Corp
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Priority to JP2004267898A priority Critical patent/JP2006086246A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor chip mounting structure which has low thermal resistance, shows little variation in thermal resistance, and is provided at a lower cost than usual. <P>SOLUTION: The semiconductor chip mounting structure is equipped with a heat dissipating plate positioned at the rear of a semiconductor chip mounted in a flip-chip mounting manner. The mounting structure is characterized by the configuration wherein it is equipped with a material which is excellent in thermal conductivity and provided with one surface brought into close contact with the semiconductor chip, and another material which is shrinkable and provided with one surface brought into close contact with the other surface of the former material and the other surface brought into close with the heat dissipating plate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体チップの実装構造に関し、特に、フリップチップにおける半導体チップの実装構造に関する。   The present invention relates to a semiconductor chip mounting structure, and more particularly to a semiconductor chip mounting structure in a flip chip.

従来の半導体チップの実装構造は、半導体チップの発熱を考慮したものもある（例えば、特許文献１から特許文献３参照。）。   Some conventional semiconductor chip mounting structures take into account the heat generated by the semiconductor chip (see, for example, Patent Document 1 to Patent Document 3).

以下に図４に基づいて従来の半導体チップの実装構造を説明する。図４は、従来の半導体チップの実装構造を示す構成図である。   Hereinafter, a conventional semiconductor chip mounting structure will be described with reference to FIG. FIG. 4 is a configuration diagram showing a conventional semiconductor chip mounting structure.

図４の従来例の構成を説明する。
半導体チップ１はバンプ２を備える。半導体チップ１はバンプ２を介して、基板４にフェイスダウンでフィリップチップ接続する。さらに、半導体チップ１と基板４との間には、アンダーフィル樹脂８を充満する。 The configuration of the conventional example of FIG. 4 will be described.
The semiconductor chip 1 includes bumps 2. The semiconductor chip 1 is connected to the substrate 4 through a bump 2 in a Philip chip connection face down. Further, the underfill resin 8 is filled between the semiconductor chip 1 and the substrate 4.

また、半導体チップ１の裏面に、高熱伝導性の樹脂７を接着する。さらにまた、樹脂７と放熱板６とを接着する。詳しくは、半導体チップ１と樹脂７とは接着用の樹脂で接着し、樹脂７と放熱板６とは接着用の樹脂で接着する。   Further, a highly heat conductive resin 7 is bonded to the back surface of the semiconductor chip 1. Furthermore, the resin 7 and the heat sink 6 are bonded. Specifically, the semiconductor chip 1 and the resin 7 are bonded with an adhesive resin, and the resin 7 and the heat sink 6 are bonded with an adhesive resin.

そして、樹脂７は、一般的に、エポキシ樹脂またはシリコーン樹脂にフィラーを混入したものを用いる。   The resin 7 is generally an epoxy resin or silicone resin mixed with a filler.

さらに、基板４上に、スティフナ５を貼り付ける。また、スティフナ５と放熱板６とは接着用の樹脂で接着する。さらに、基板４の裏面にハンダボール３を搭載する。   Further, a stiffener 5 is attached on the substrate 4. Further, the stiffener 5 and the heat radiating plate 6 are bonded with an adhesive resin. Further, a solder ball 3 is mounted on the back surface of the substrate 4.

このようにして、図４の従来例は、フリップチップ型のＢＧＡパッケージを形成する。   In this way, the conventional example of FIG. 4 forms a flip chip type BGA package.

そして、半導体チップ１の発熱は、樹脂７を介して放熱板６へ伝達する。よって、半導体チップ１の熱抵抗は、樹脂７の熱伝導率と樹脂７の厚さとでほぼ決まる。   The heat generated by the semiconductor chip 1 is transmitted to the heat radiating plate 6 through the resin 7. Therefore, the thermal resistance of the semiconductor chip 1 is almost determined by the thermal conductivity of the resin 7 and the thickness of the resin 7.

特開平６−２２４３３４号公報JP-A-6-224334 特開平７−３２１２５７号公報Japanese Patent Laid-Open No. 7-32257 特許第３４５９８０４号公報Japanese Patent No. 3459804

しかしながら、従来の半導体チップの実装構造の熱抵抗が大きいという課題がある。また、従来の半導体チップの実装構造の熱抵抗のばらつきが大きいという課題がある。   However, there is a problem that the thermal resistance of the conventional semiconductor chip mounting structure is large. In addition, there is a problem that the variation in the thermal resistance of the conventional semiconductor chip mounting structure is large.

詳しくは、樹脂７を形成するエポキシ樹脂またはシリコーン樹脂にフィラーを混入したものの熱伝導率は、金属に比べて低い。   Specifically, the thermal conductivity of the epoxy resin or silicone resin forming the resin 7 mixed with a filler is lower than that of the metal.

また、一般的なスティフナ５、半導体チップ１、バンプ２等の製造ばらつきと、基板４のそり等と、を考慮すると、半導体チップ１と放熱板６との距離を小さくすることは困難である。具体的には、半導体チップ１と放熱板６との距離（樹脂７の厚さ）を数十ミクロンとすることは困難である。   Further, in consideration of manufacturing variations of the general stiffener 5, semiconductor chip 1, bump 2, etc., warpage of the substrate 4, etc., it is difficult to reduce the distance between the semiconductor chip 1 and the heat sink 6. Specifically, it is difficult to set the distance between the semiconductor chip 1 and the heat sink 6 (the thickness of the resin 7) to several tens of microns.

さらに、加工精度を上げ、製造ばらつきを抑制すると製造コストが高くなるという課題がある。   Furthermore, there is a problem that the manufacturing cost increases when the processing accuracy is increased and the manufacturing variation is suppressed.

本発明の目的は、以上説明した課題を解決するものであり、半導体チップの熱抵抗が小さく、熱抵抗のばらつきが小さく、低コストの半導体チップの実装構造を提供することにある。   An object of the present invention is to solve the above-described problems, and to provide a low-cost semiconductor chip mounting structure in which the thermal resistance of the semiconductor chip is small, the variation in thermal resistance is small.

このような目的を達成する本発明は、次の通りである。
（１）フリップチップ実装された半導体チップの裏面に放熱板を備える半導体チップの実装構造において、一方の面が前記半導体チップに密着する熱伝導性に優れた材料と、一方の面が前記熱伝導性に優れた材料の他方の面と密着し、他方の面が前記放熱板に密着する収縮性のある材料とを備えることを特徴とする半導体チップの実装構造。
（２）前記熱伝導性に優れた材料は、金属または窒化アルミニウムから形成することを特徴とする（１）記載の半導体チップの実装構造。
（３）前記熱伝導性に優れた材料の面積と前記収縮性のある材料の面積とは、前記半導体チップの裏面の面積よりも大きいことを特徴とする（２）記載の半導体チップの実装構造。
（４）前記半導体チップと前記熱伝導性に優れた材料との間に薄い接着層を備えることを特徴とする（３）記載の半導体チップの実装構造。
（５）前記熱伝導性に優れた材料は、一方の面が前記半導体チップに密着し、他方の面が前記収縮性のある材料の一方の面と前記放熱板とに密着するシート材料で形成することを特徴とする（１）記載の半導体チップの実装構造。 The present invention which achieves such an object is as follows.
(1) In a semiconductor chip mounting structure in which a heat sink is provided on the back surface of a flip chip mounted semiconductor chip, one surface has excellent thermal conductivity and the other surface has the heat conductivity. A semiconductor chip mounting structure comprising: a shrinkable material that is in close contact with the other surface of the material having excellent properties, and the other surface is in close contact with the heat radiating plate.
(2) The semiconductor chip mounting structure according to (1), wherein the material having excellent thermal conductivity is made of metal or aluminum nitride.
(3) The semiconductor chip mounting structure according to (2), wherein the area of the material having excellent thermal conductivity and the area of the shrinkable material are larger than the area of the back surface of the semiconductor chip. .
(4) The semiconductor chip mounting structure according to (3), further comprising a thin adhesive layer between the semiconductor chip and the material having excellent thermal conductivity.
(5) The material having excellent thermal conductivity is formed of a sheet material in which one surface is in close contact with the semiconductor chip and the other surface is in close contact with one surface of the shrinkable material and the heat sink. (1) The semiconductor chip mounting structure according to (1).

以上説明したことから明らかなように、本発明によれば次のような効果がある。
本発明によれば、半導体チップの熱抵抗が小さく、熱抵抗のばらつきが小さく、低コストの大きい半導体チップの実装構造を提供できる。 As is apparent from the above description, the present invention has the following effects.
ADVANTAGE OF THE INVENTION According to this invention, the thermal resistance of a semiconductor chip is small, the dispersion | variation in thermal resistance is small, and the mounting structure of a semiconductor chip with a large low cost can be provided.

以下に図１に基づいて本発明を詳細に説明する。図１は、本発明の一実施例を示す構成図である。図４の従来例と同一の要素には同一符号を付し、説明を省略する。   Hereinafter, the present invention will be described in detail with reference to FIG. FIG. 1 is a block diagram showing an embodiment of the present invention. The same elements as those in the conventional example of FIG.

図１の実施例の特徴は、熱伝導性に優れた材料（窒化アルミニウム）９と収縮性のある材料（熱伝導樹脂シート）１０とを備える点にある。   A feature of the embodiment of FIG. 1 is that a material (aluminum nitride) 9 having excellent thermal conductivity and a material (thermal conductive resin sheet) 10 having shrinkage are provided.

図１の実施例の構成を説明する。
熱伝導性に優れた材料９は、例えば、金属または窒化アルミニウムから形成する。また、窒化アルミニウム９の一方の面は、半導体チップ１に密着する。 The configuration of the embodiment of FIG. 1 will be described.
The material 9 having excellent thermal conductivity is made of, for example, metal or aluminum nitride. One surface of the aluminum nitride 9 is in close contact with the semiconductor chip 1.

また、収縮性のある材料１０は、例えば、熱伝導樹脂シートから形成する。なお、熱伝導樹脂シート１０に高熱伝導性の樹脂を使用してもよい。また、熱伝導樹脂シート１０の一方の面は、窒化アルミニウム９の他方の面と密着する。さらにまた、熱伝導樹脂シート１０の他方の面は、放熱板６に密着する。   The shrinkable material 10 is formed from, for example, a heat conductive resin sheet. In addition, you may use highly heat conductive resin for the heat conductive resin sheet 10. FIG. Further, one surface of the heat conductive resin sheet 10 is in close contact with the other surface of the aluminum nitride 9. Furthermore, the other surface of the heat conductive resin sheet 10 is in close contact with the heat sink 6.

さらに、窒化アルミニウム９の面積と、熱伝導樹脂シート１０の面積とは、半導体チップ１の裏面の面積よりも大きく形成する。   Furthermore, the area of the aluminum nitride 9 and the area of the heat conductive resin sheet 10 are formed larger than the area of the back surface of the semiconductor chip 1.

このような図１の実施例において、半導体チップ１の発熱は、窒化アルミニウム９に伝達し、さらに、熱伝導樹脂シート１０に伝達し、さらにまた、放熱板６へ伝達する。   In the embodiment of FIG. 1, the heat generated by the semiconductor chip 1 is transmitted to the aluminum nitride 9, further transmitted to the heat conductive resin sheet 10, and further transmitted to the heat radiating plate 6.

窒化アルミニウム９において、熱は、半導体チップ１の上部のみでなく、横方向へも伝達する。そして、窒化アルミニウム９の熱は、広い面積で、熱伝導樹脂シート１０を介して、放熱板６へ伝達する。   In the aluminum nitride 9, heat is transmitted not only on the top of the semiconductor chip 1 but also in the lateral direction. The heat of the aluminum nitride 9 is transmitted to the heat radiating plate 6 through the heat conductive resin sheet 10 in a wide area.

窒化アルミニウム９の熱抵抗は十分に小さいとすると、半導体チップ１の熱抵抗は、熱伝導樹脂シート１０の熱伝導率と熱伝導樹脂シート１０の厚さと熱伝導樹脂シート１０の面積でほぼ決まる。   If the thermal resistance of the aluminum nitride 9 is sufficiently small, the thermal resistance of the semiconductor chip 1 is almost determined by the thermal conductivity of the thermal conductive resin sheet 10, the thickness of the thermal conductive resin sheet 10, and the area of the thermal conductive resin sheet 10.

よって、図１の実施例は、熱伝導樹脂シート１０の面積が大きいため、熱抵抗が小さくなる。なお、熱伝導樹脂シート１０は、スティフナ５、半導体チップ１、バンプ２等の製造ばらつきを吸収する。   Therefore, since the area of the heat conductive resin sheet 10 is large in the Example of FIG. 1, thermal resistance becomes small. The heat conductive resin sheet 10 absorbs manufacturing variations of the stiffener 5, the semiconductor chip 1, the bump 2, and the like.

以上のことにより、図１の実施例は、熱伝導性に優れた材料９と収縮性のある材料１０とを備えることにより、半導体チップの熱抵抗が小さく、熱抵抗のばらつきが小さい特性となる。   As described above, the embodiment shown in FIG. 1 includes the material 9 having excellent thermal conductivity and the shrinkable material 10, so that the thermal resistance of the semiconductor chip is small and the variation in thermal resistance is small. .

さらに、図１の実施例は、特別な加工精度を必要とないため、製造コストを低くできる。   Furthermore, since the embodiment of FIG. 1 does not require special processing accuracy, the manufacturing cost can be reduced.

以下に図２に基づいて本発明を詳細に説明する。図２は、本発明の他の実施例を示す構成図である。図１の実施例と同一の要素には同一符号を付し、説明を省略する。   Hereinafter, the present invention will be described in detail with reference to FIG. FIG. 2 is a block diagram showing another embodiment of the present invention. Elements that are the same as those in the embodiment of FIG.

図２の実施例の特徴は、薄い接着層１１を備える点にある。   A feature of the embodiment of FIG. 2 is that a thin adhesive layer 11 is provided.

薄い接着層１１は、半導体チップ１と窒化アルミニウム（熱伝導性に優れた材料）９との間に形成する。   The thin adhesive layer 11 is formed between the semiconductor chip 1 and aluminum nitride (a material having excellent thermal conductivity) 9.

このような図２の実施例において、半導体チップ１の発熱は、薄い接着層１１を介して、効率的に窒化アルミニウム９に伝達する。   In the embodiment of FIG. 2, the heat generated by the semiconductor chip 1 is efficiently transmitted to the aluminum nitride 9 through the thin adhesive layer 11.

したがって、図２の実施例は、一層熱抵抗が小さく、一層熱抵抗のばらつきが小さい特性となる。   Therefore, the embodiment of FIG. 2 has characteristics that the thermal resistance is smaller and the variation in thermal resistance is smaller.

以下に図３に基づいて本発明を詳細に説明する。図３は、本発明の他の実施例を示す構成図である。図１の実施例と同一の要素には同一符号を付し、説明を省略する。また、図３の実施例における収縮性のある材料（熱伝導樹脂シート）２０は、図１の実施例における収縮性のある材料（熱伝導樹脂シート）１０に対応する。   Hereinafter, the present invention will be described in detail with reference to FIG. FIG. 3 is a block diagram showing another embodiment of the present invention. Elements that are the same as those in the embodiment of FIG. Further, the shrinkable material (thermal conductive resin sheet) 20 in the embodiment of FIG. 3 corresponds to the shrinkable material (thermal conductive resin sheet) 10 in the embodiment of FIG.

図３の実施例の特徴は、熱伝導性に優れた材料（シート材料）１９の構成にある。   The feature of the embodiment of FIG. 3 is the configuration of a material (sheet material) 19 having excellent thermal conductivity.

熱伝導性に優れた材料１９は、例えば、シート材料で形成する。また、シート材料１９の一方の面は前記半導体チップに密着する。さらに、シート材料１９の他方の面は、熱伝導樹脂シート２０の一方の面と、放熱板６とに密着する。   The material 19 having excellent thermal conductivity is formed of, for example, a sheet material. Further, one surface of the sheet material 19 is in close contact with the semiconductor chip. Furthermore, the other surface of the sheet material 19 is in close contact with one surface of the heat conductive resin sheet 20 and the heat sink 6.

また、熱伝導樹脂シート２０の面積は半導体チップ１の裏面の面積にほぼ等しくし、熱伝導樹脂シート２０は半導体チップ１の裏面のほぼ真上に配置する。   Further, the area of the heat conductive resin sheet 20 is substantially equal to the area of the back surface of the semiconductor chip 1, and the heat conductive resin sheet 20 is disposed almost directly above the back surface of the semiconductor chip 1.

このような図３の実施例において、半導体チップ１の発熱の一部分は、シート材料１９を介して、直接放熱板６に伝達する。したがって、図３の実施例は、効率的に熱を伝達し、一層熱抵抗が小さくなる。   In such an embodiment of FIG. 3, a part of the heat generated by the semiconductor chip 1 is directly transmitted to the heat sink 6 via the sheet material 19. Thus, the embodiment of FIG. 3 efficiently transfers heat and further reduces thermal resistance.

以上のように、本発明は、前述の実施例に限定されることなく、その本質を逸脱しない範囲でさらに多くの変更及び変形を含むものである。   As described above, the present invention is not limited to the above-described embodiments, and includes many changes and modifications without departing from the essence thereof.

本発明の一実施例を示す構成図である。It is a block diagram which shows one Example of this invention. 本発明の他の実施例を示す構成図である。It is a block diagram which shows the other Example of this invention. 本発明の他の実施例を示す構成図である。It is a block diagram which shows the other Example of this invention. 従来の半導体チップの実装構造を示す構成図である。It is a block diagram which shows the mounting structure of the conventional semiconductor chip.

符号の説明Explanation of symbols

１ 半導体チップ
２ バンプ
３ ハンダボール
４ 基板
５ スティフナ
６ 放熱板
７ 樹脂
８ アンダーフィル樹脂
９ 窒化アルミニウム（熱伝導性に優れた材料）
１０，２０ 熱伝導樹脂シート（収縮性のある材料）
１１ 薄い接着層
２９ シート材料（熱伝導性にす優れた材料）
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Bump 3 Solder ball 4 Board | substrate 5 Stiffener 6 Heat sink 7 Resin 8 Underfill resin 9 Aluminum nitride (material excellent in heat conductivity)
10, 20 Thermal conductive resin sheet (shrinkable material)
11 Thin adhesive layer 29 Sheet material (material with excellent thermal conductivity)

Claims (5)

フリップチップ実装された半導体チップの裏面に放熱板を備える半導体チップの実装構造において、
一方の面が前記半導体チップに密着する熱伝導性に優れた材料と、
一方の面が前記熱伝導性に優れた材料の他方の面と密着し、他方の面が前記放熱板に密着する収縮性のある材料と
を備えることを特徴とする半導体チップの実装構造。 In a semiconductor chip mounting structure including a heat sink on the back surface of a flip chip mounted semiconductor chip,
A material having one surface closely adhered to the semiconductor chip and excellent in thermal conductivity;
A semiconductor chip mounting structure comprising: a shrinkable material in which one surface is in close contact with the other surface of the material having excellent thermal conductivity, and the other surface is in close contact with the heat dissipation plate. 前記熱伝導性に優れた材料は、金属または窒化アルミニウムから形成することを特徴とする請求項１記載の半導体チップの実装構造。   2. The semiconductor chip mounting structure according to claim 1, wherein the material having excellent thermal conductivity is made of metal or aluminum nitride. 前記熱伝導性に優れた材料の面積と前記収縮性のある材料の面積とは、前記半導体チップの裏面の面積よりも大きいことを特徴とする請求項２記載の半導体チップの実装構造。   3. The semiconductor chip mounting structure according to claim 2, wherein an area of the material having excellent thermal conductivity and an area of the shrinkable material are larger than an area of a back surface of the semiconductor chip. 前記半導体チップと前記熱伝導性に優れた材料との間に薄い接着層を備えることを特徴とする請求項３記載の半導体チップの実装構造。   4. The semiconductor chip mounting structure according to claim 3, further comprising a thin adhesive layer between the semiconductor chip and the material having excellent thermal conductivity. 前記熱伝導性に優れた材料は、一方の面が前記半導体チップに密着し、他方の面が前記収縮性のある材料の一方の面と前記放熱板とに密着するシート材料で形成することを特徴とする請求項１記載の半導体チップの実装構造。
The material having excellent thermal conductivity is formed of a sheet material in which one surface is in close contact with the semiconductor chip and the other surface is in close contact with one surface of the shrinkable material and the heat radiating plate. 2. The semiconductor chip mounting structure according to claim 1, wherein:
JP2004267898A 2004-09-15 2004-09-15 Mounting structure of semiconductor chip Pending JP2006086246A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013140295A3 (en) * 2012-03-22 2014-01-23 Koninklijke Philips N.V. Thermal interface material
JP2014022577A (en) * 2012-07-19 2014-02-03 Fujitsu Semiconductor Ltd Semiconductor device and method of manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013140295A3 (en) * 2012-03-22 2014-01-23 Koninklijke Philips N.V. Thermal interface material
US9316447B2 (en) 2012-03-22 2016-04-19 Koninklijke Philips N.V. Thermal interface material
JP2014022577A (en) * 2012-07-19 2014-02-03 Fujitsu Semiconductor Ltd Semiconductor device and method of manufacturing semiconductor device

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