JP2006066490A - Thin-film transistor panel and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To further miniaturize a thin-film transistor panel having an amorphous silicon thin-film transistor, and to provide a polysilicon thin-film transistor. <P>SOLUTION: A photoelectric conversion type thin-film transistor 3 having a semiconductor thin film 41 made of an amorphous silicon is provided at an upper layer side rather than CMOS thin film transistors 21 and 22 for a drive circuit having semiconductor thin films 25 and 26 made of a polysilicon. Thereby, by comparing the semiconductor thin film 41 with the case of providing the semiconductor thin film 41 on the same layer as the semiconductor thin films 25 and 26, further miniaturization can be performed. In this case, the upper layer connecting wiring 48, 51, 54 of the part of the connection wiring for connecting the conductor layers 35 and 36 including the bottom gate electrode 9, source/drain electrodes 10 and top gate electrode 8 of the thin-film transistor 3 to the source/drain electrodes of the thin-film transistors 21 and 22 are provided on the top gate insulating film 39 provided with the top gate electrode 8. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a thin film transistor panel and a method for manufacturing the same, and more particularly to a thin film transistor panel including a polysilicon thin film transistor and an amorphous silicon thin film transistor and a method for manufacturing the same.

  In the image reading apparatus, for example, a plurality of photosensors are arranged in an image reading area in a substantially central portion on a glass substrate, and a semiconductor chip for driving the photosensors is arranged outside the image reading area on the glass substrate. (For example, refer to Patent Document 1).

  However, in such an image reading device, since the semiconductor chip arranged outside the image reading region protrudes upward, for example, when used as a fingerprint reading device, a finger as a subject touches the semiconductor chip. If contact is made, the finger cannot be brought into close contact with the image reading area as expected, and an appropriate fingerprint reading operation is not performed, which causes a malfunction such as a malfunction.

  Therefore, in order to avoid such a problem due to the upward protrusion of the semiconductor chip, it may be possible to adopt a configuration in which the semiconductor chip is arranged at a position somewhat away from the image reading area. Is not preferable when the entire apparatus becomes large and is considered to be mounted on a portable device or the like.

  On the other hand, in an active matrix type liquid crystal display device, for example, an amorphous silicon thin film is formed on a glass substrate, and only the polysilicon thin film transistor forming region is selectively crystallized to selectively form a polysilicon thin film. There is one in which an amorphous silicon thin film transistor is formed in an amorphous silicon thin film formation region and a polysilicon thin film transistor is formed in a polysilicon thin film formation region (see, for example, Patent Document 2).

  In such a liquid crystal display device, an amorphous silicon thin film transistor is formed as a switching element in an image display region in a substantially central portion on the glass substrate, and the amorphous silicon thin film transistor is driven outside the image display region on the glass substrate. When a polysilicon thin film transistor is formed as a drive circuit section for the purpose, the uppermost surface becomes substantially flat. Therefore, when such a structure is adopted in the fingerprint reading apparatus, it is not necessary to separate the drive circuit unit from the image reading area more than necessary, and the entire apparatus can be downsized.

JP-A-8-8414 (FIG. 3) Japanese Patent Publication No. 5-9794

  However, in the liquid crystal display device described in Patent Document 2, only the polysilicon thin film transistor formation region (drive circuit portion formation region) is selectively crystallized out of the amorphous silicon thin film formed on the glass substrate. Therefore, a step of partially forming a polysilicon thin film is required.

  For this reason, when crystallization of an amorphous silicon thin film is performed by laser irradiation, for example, it is necessary to control the laser irradiation position with high accuracy and to selectively crystallize the amorphous silicon thin film by scanning a thin laser beam. As a result, it is necessary to increase the precision of the manufacturing apparatus, and it takes a relatively long time for the crystallization process, resulting in an increase in manufacturing cost.

  In addition, since the amorphous silicon thin film is crystallized by heating the amorphous silicon thin film to about 600 ° C., it is difficult to clearly separate the crystallized region from the non-crystallized region. There has been a problem that it is difficult to dispose the image display region made of the amorphous silicon thin film transistor and the drive circuit portion made of the polysilicon thin film transistor sufficiently close to each other on the substrate, and there is a limit to downsizing of the entire device.

  Accordingly, an object of the present invention is to provide a thin film transistor panel and a method for manufacturing the same that can reduce the manufacturing cost and can further reduce the size of the entire apparatus.

  In order to achieve the above object, the present invention provides a polysilicon thin film transistor having a semiconductor thin film made of polysilicon and a plurality of electrodes on a substrate, and an amorphous silicon thin film transistor having a semiconductor thin film made of amorphous silicon and a plurality of electrodes. In the thin film transistor panel provided, the first wiring connected to any of the plurality of electrodes of the polysilicon thin film transistor, provided in the same layer with the same conductive material as the electrode, and having a connection pad; A semiconductor thin film made of amorphous silicon provided on an upper portion of the first wiring via an insulating film, and the same conductive material as the electrode connected to one of the plurality of electrodes of the amorphous silicon thin film transistor The material is provided in the same layer and the connection pad A plurality of second wirings provided in different layers with an insulating film interposed therebetween, and each of the first wiring and the second wiring facing each other through an insulating film, The first wiring and the second wiring are electrically connected to each other through a plurality of contact holes provided at locations corresponding to the connection pads of the first wiring and the second wiring of the insulating film. And a third wiring connected to each other.

  According to the present invention, since the semiconductor thin film of the amorphous silicon thin film transistor is provided on the upper layer side of the semiconductor thin film of the polysilicon thin film transistor, the semiconductor thin film of the amorphous silicon thin film transistor is formed on the upper layer after forming the semiconductor thin film of the polysilicon thin film transistor. Therefore, the entire amorphous silicon thin film formed may be crystallized to form a polysilicon thin film. As in the prior art, a specific region of the formed amorphous silicon thin film is selected. Therefore, a process for crystallization is unnecessary, the process can be simplified, and the manufacturing cost can be reduced.

  In addition, since the semiconductor thin film of the amorphous silicon thin film transistor is provided on the upper layer side of the semiconductor thin film of the polysilicon thin film transistor, the polysilicon thin film transistor and the amorphous silicon thin film transistor are separately formed in different layers. Can be arranged close enough to each other, and further downsizing of the entire apparatus can be achieved.

  Furthermore, it is connected to one of the plurality of electrodes of the polysilicon thin film transistor and one of the plurality of electrodes of the amorphous silicon thin film transistor, and is electrically connected through the contact hole to connect the electrodes of the polysilicon thin film transistor and the amorphous silicon thin film transistor to each other. By forming a part of each wiring in the same layer on the insulating film and forming a plurality of contact holes at the same time, the process of forming the wiring and contact holes is simplified and the manufacturing cost is reduced. can do.

(First embodiment)
FIG. 1 shows an equivalent circuit plan view of a main part of a thin film transistor panel constituting an image reading apparatus as a first embodiment of the present invention. The thin film transistor panel includes a glass substrate 1. A plurality of photoelectric conversion type thin film transistors 3 as photosensors are arranged in a matrix in the image reading region 2 in the substantially central portion on the glass substrate 1.

  On the glass substrate 1, first to third drive circuit units 4 to 6 to be described later for driving the thin film transistor 3 are provided in the adjacent regions on the right side, the left side, and the lower side of the image reading region 2. . A plurality of external connection terminals 7 are provided at the lower end portion on the glass substrate 1. As will be described later, the external connection terminal 7 is connected to the first to third drive circuit units 4 to 6 and the like via connection wiring provided on the glass substrate 1.

  The thin film transistor 3 includes a top gate electrode 8, a bottom gate electrode 9, and source / drain electrodes 10 and 10, which will be described in detail later. The top gate electrode 8 is connected to the first drive circuit unit (top gate driver) 4 via the top gate line 11 arranged in the row direction in the image reading region 2. The bottom gate electrode 9 is connected to a second drive circuit unit (bottom gate driver) 5 via a bottom gate line 12 arranged in the row direction in the image reading region 2.

  One source / drain electrode 10 is connected to a third drive circuit section (drain driver) 6 via a drain line 13 arranged in the column direction in the image reading region 2. The other source / drain electrode 10 is connected to a grounding external connection terminal of the external connection terminals 7 via a ground line (not shown) arranged in the image reading region 2 or the like.

  Next, an example of a specific structure of a part of the thin film transistor panel will be described with reference to FIG. In this case, from the left side to the right side in FIG. 2, a cross-sectional view of the portion of the external connection terminal 7, and portions of the CMOS thin film transistors 21 and 22 constituting each part of the first to third drive circuit portions 4 to 6. Sectional drawing, sectional drawing of the part of the 1st-4th interlayer contact, sectional drawing of the part of the photoelectric conversion type thin-film transistor 3 are shown.

  First, the portions of the CMOS thin film transistors 21 and 22 that constitute each part of the first to third drive circuit units 4 to 6 will be described. In the drive circuit portion forming region on the glass substrate 1, a CMOS thin film transistor including an NMOS thin film transistor 21 and a PMOS thin film transistor 22 made of, for example, a polysilicon thin film transistor is provided.

  Each of the thin film transistors 21 and 22 includes semiconductor thin films 25 and 26 made of polysilicon provided on the upper surfaces of the first and second base insulating films 23 and 24 provided on the upper surface of the glass substrate 1. In this case, the first base insulating film 23 is made of silicon nitride, and the second base insulating film 24 is made of silicon oxide.

  The NMOS thin film transistor 21 has, for example, an LDD (Lightly Doped Drain) structure. That is, the central portion of the semiconductor thin film 25 of the NMOS thin film transistor 21 is a channel region 25a made of an intrinsic region, both sides thereof are a source / drain region 25b made of an n-type impurity low concentration region, and both sides thereof are n-type impurity high The source / drain region 25c is formed of a concentration region. On the other hand, the central portion of the semiconductor thin film 26 of the PMOS thin film transistor 22 is a channel region 26a made of an intrinsic region, and both sides thereof are a source / drain region 26b made of a p-type impurity high concentration region.

  A gate insulating film 27 made of silicon oxide is provided on the upper surface of the second base insulating film 24 including the semiconductor thin films 25 and 26. Gate electrodes 28 and 29 made of molybdenum are provided on the upper surface of the gate insulating film 27 on the channel regions 25a and 26a. A first interlayer insulating film 30 made of silicon nitride is provided on the upper surface of the gate insulating film 27 including the gate electrodes 28 and 29. Contact holes 33 and 34 are provided in the first interlayer insulating film 30 and the gate insulating film 27 on the source / drain regions 25 c and 26 b of the semiconductor thin films 25 and 26.

  Conductive layers 35 and 36 made of molybdenum are connected to the source / drain regions 25c and 26b via the contact holes 33 and 34 on the upper surface of the first interlayer insulating film 30 in and near the contact holes 33 and 34, respectively. The source / drain electrodes and the wirings connected thereto are formed. Here, the conductor layers 35 and 36 include a portion formed on the first interlayer insulating film 30 and a portion filled in the contact holes 33 and 34. A second interlayer insulating film 37 made of silicon nitride, a bottom gate insulating film 38, a top gate insulating film 39, and an overcoat film 40 are provided on the upper surface of the first interlayer insulating film 30 including the conductor layers 35 and 36. ing.

  The NMOS thin film transistor 21 includes a semiconductor thin film 25, a gate insulating film 27, a gate electrode 28, and a conductor layer 35 including a source / drain electrode. The PMOS thin film transistor 22 includes a semiconductor thin film 26, a gate insulating film 27, a gate electrode 29, and a conductor layer 36 including source / drain electrodes. As a result, the CMOS thin film transistor composed of the NMOS thin film transistor 21 and the PMOS thin film transistor 22, that is, the first to third drive circuit units 4 to 6 are integrally formed on the glass substrate 1.

  Next, the photoelectric conversion type thin film transistor 3 will be described. A bottom gate made of chromium (light-shielding metal) is formed on the upper surface of the second interlayer insulating film 37 provided so as to cover the conductor layers 35 and 36 including the source / drain electrodes of the thin film transistors 21 and 22 for the driving circuit section. An electrode 9 is provided. A bottom gate insulating film 38 is provided on the upper surface of the second interlayer insulating film 37 including the bottom gate electrode 9. A semiconductor thin film 41 made of intrinsic amorphous silicon is provided on the bottom gate insulating film 38 on the bottom gate electrode 9.

  A channel protective film 42 made of silicon nitride is provided at substantially the center of the upper surface of the semiconductor thin film 41. Ohmic contact layers 43 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 42 and on the upper surface of the semiconductor thin film 41 on both sides thereof. A source / drain electrode 10 made of chromium is provided on the upper surface of the ohmic contact layer 43 and the upper surface of the bottom gate insulating film 38 in the vicinity thereof.

  A top gate insulating film 39 is provided on the upper surface of the bottom gate insulating film 38 including the source / drain electrodes 10. A top gate electrode 8 made of ITO (translucent metal) is provided on the top surface of the top gate insulating film 39 on the semiconductor thin film 41. An overcoat film 40 is provided on the top surface of the top gate insulating film 39 including the top gate electrode 8.

  The photoelectric conversion type thin film transistor 3 is a bottom-gate type selection composed of the bottom gate electrode 9, the bottom gate insulating film 38, the semiconductor thin film 41, the channel protective film 42, the ohmic contact layer 43 and the source / drain electrode 10. The thin film transistor includes a top gate electrode 8, a top gate insulating film 39, a semiconductor thin film 41, a channel protective film 42, an ohmic contact layer 43, and a source / drain electrode 10. Yes. Thus, the photoelectric conversion type thin film transistor 3 is integrally formed on the glass substrate 1.

  Next, the external connection terminal 7 will be described. The external connection terminal 7 made of molybdenum is provided on the upper surface of the first interlayer insulating film 30, and is provided on the overcoat film 40, the top gate insulating film 39, the bottom gate insulating film 38, and the second interlayer insulating film 37. It is exposed through the opening 44.

  Next, the first to fourth interlayer contact portions will be described. In the first interlayer contact portion, the first upper-layer connection wiring 45 provided on the upper surface of the first interlayer insulating film 30 and provided in the same layer as the conductor layers 35 and 36, and made of the same molybdenum, A contact hole 46 provided in the first interlayer insulating film 30 is connected to a connection pad portion of a first lower layer connection wiring 47 made of molybdenum provided on the upper surface of the gate insulating film 27. Here, the first upper layer connection wiring 45 includes a portion formed on the upper surface of the first interlayer insulating film 30 and a portion filled in the contact hole 46.

  In the second interlayer contact portion, the second upper layer connection wiring 48 made of ITO provided on the upper surface of the top gate insulating film 39 includes the top gate insulating film 39, the bottom gate insulating film 38, and the second interlayer insulating film. It is connected to the connection pad portion of the second lower layer connection wiring 50 made of molybdenum provided on the upper surface of the first interlayer insulating film 30 through the contact hole 49 provided in the film 37. Here, the second upper layer connection wiring 48 includes a portion formed on the upper surface of the top gate insulating film 39 and a portion filled in the contact hole 49.

  In the third interlayer contact portion, the third upper layer connection wiring 51 made of ITO provided on the upper surface of the top gate insulating film 39 is connected to the contact holes provided in the top gate insulating film 39 and the bottom gate insulating film 38. The connection pad portion of the third lower layer connection wiring 53 made of chromium provided on the upper surface of the second interlayer insulating film 37 is connected via 52. Here, the third upper layer connection wiring 51 includes a portion formed on the upper surface of the top gate insulating film 39 and a portion filled in the contact hole 52.

  In the fourth interlayer contact portion, the fourth upper layer connection wiring 54 made of ITO provided on the upper surface of the top gate insulating film 39 is connected to the bottom via the contact hole 55 provided in the top gate insulating film 39. It is connected to the connection pad portion of the fourth lower layer connection wiring 56 made of chromium provided on the upper surface of the gate insulating film 38. Here, the fourth upper layer connection wiring 54 includes a portion formed on the upper surface of the top gate insulating film 39 and a portion filled in the contact hole 55.

  Next, the electrical connection of each part shown in FIG. 2 will be described. The bottom gate electrode 9 of the photoelectric conversion type thin film transistor 3 is formed by connecting the conductor layers of the third lower layer connection wiring 53, the third upper layer connection wiring 51, the second upper layer connection wiring 48, and the second lower layer connection wiring 50. Via the bottom gate line 12 shown in FIG. 1, connected to the conductor layers 35 and 36 including the source / drain electrodes of the thin film transistors 21 and 22 of the second drive circuit section (bottom gate driver) 5. Yes.

  One source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected to the fourth lower layer connection wiring 56, the fourth upper layer connection wiring 54, the second upper layer connection wiring 48, and the second lower layer connection wiring 50. Via the body layer, that is, via the drain line 13 shown in FIG. 1, it is connected to the conductor layers 35 and 36 including the source / drain electrodes of the thin film transistors 21 and 22 of the third drive circuit section (drain driver) 6. ing.

  The other source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected to the fourth lower layer connection wiring 56, the fourth upper layer connection wiring 54, the second upper layer connection wiring 48, and the second lower layer connection wiring 50. It is connected to the grounding external connection terminal among the external connection terminals 7 via the body layer, that is, via a ground line (not shown in FIG. 1).

  The top gate electrode 8 of the photoelectric conversion type thin film transistor 3 is connected to each of the conductor layers of the second upper layer connection wiring 48 and the second lower layer connection wiring 50, that is, through the top gate line 11 shown in FIG. The first drive circuit section (top gate driver) 4 is connected to the conductor layers 35 and 36 including the source / drain electrodes of the thin film transistors 21 and 22.

  The gate electrodes 28 and 29 of the thin film transistors 21 and 22 for the drive circuit section are connected to the external connection terminal 7 through the respective conductor layers of the first lower layer connection wiring 47 and the first upper layer connection wiring 45. . The conductor layers 35 and 36 including the source / drain electrodes of the thin film transistors 21 and 22 for the driving circuit section are connected to each other through a connection wiring (not shown) provided on the upper surface of the first interlayer insulating film 30. Connected to terminal 7.

  Here, the conductor layers forming the second to fourth upper layer connection wirings 48, 51, 54 in this embodiment are made of the same conductive material as that of the top gate electrode 8 of the photoelectric conversion type thin film transistor 3, so that the top gate insulating film The upper surface of 39 is formed in the same layer. The second to fourth upper layer connection wirings 48, 51, 54 are connected to the bottom gate electrode 9 of the photoelectric conversion type thin film transistor 3 through the first to fourth lower layer connection wirings 47, 50, 53, 56. The source / drain electrode 10 and the top gate electrode 8 are connected to the conductor layers 35 and 36 including the source / drain electrodes of the thin film transistors 21 and 22 for the drive circuit section.

  Next, an example of a method for manufacturing this thin film transistor panel will be described. First, as shown in FIG. 3, a first base insulating film 23 (thickness of about 2000 mm) made of silicon nitride and a second base insulating film 24 made of silicon oxide are formed on the upper surface of the glass substrate 1 by plasma CVD. (A film thickness of about 1000 mm) and an amorphous silicon thin film 61 (film thickness of about 500 mm) are continuously formed. Here, the step of forming the amorphous silicon thin film 61 is performed under a temperature condition (second temperature condition) in which about 300 ° C. is the maximum temperature.

  Next, in order to remove the hydrogen contained in the amorphous silicon thin film 61 formed by plasma CVD with a high hydrogen content, a dehydrogenation process is performed for about 1 hour at a temperature of about 500 ° C. in a nitrogen gas atmosphere. This dehydrogenation treatment is performed in order to avoid the occurrence of defects due to bumping of hydrogen in the amorphous silicon thin film 61 when high energy is given to the amorphous silicon thin film 61 by excimer laser irradiation in a subsequent process. is there.

  Next, by irradiating the amorphous silicon thin film 61 with an excimer laser from the upper surface side, the amorphous silicon thin film 61 is crystallized to form a polysilicon thin film 62. Here, the step of crystallizing the amorphous silicon thin film 61 to form the polysilicon thin film 62 is performed under a temperature condition (first temperature condition) where the maximum temperature is approximately 600 ° C.

  Next, by patterning the polysilicon thin film 62 by photolithography, semiconductor thin films 25 and 26 are formed as shown in FIG. Next, as shown in FIG. 5, a gate insulating film 27 (thickness of about 1000 mm) made of silicon oxide is formed on the upper surface of the second base insulating film 24 including the semiconductor thin films 25 and 26 by plasma CVD. To do. Next, a conductor layer made of a molybdenum film (having a film thickness of about 3000 mm) formed by sputtering is patterned on the upper surface of the gate insulating film 27 by photolithography, whereby the gate electrodes 28 and 29 and the first electrode are formed. A lower layer connection wiring 47 is formed.

Next, as shown in FIG. 6, a p-type impurity is formed using a first resist pattern (not shown) formed by photolithography and having an opening in a portion corresponding to the source / drain region 26b as a mask. Inject at high concentration. As an example, boron ions are implanted under conditions of an acceleration energy of 30 keV and a dose of 3 × 10 ¹⁵ atm / cm ² . As a result, the semiconductor thin film 26 has a channel region 26a made of an intrinsic region under the gate electrode 29 and source / drain regions 26b made of p-type impurity high concentration regions on both sides thereof. Thereafter, the first resist pattern is peeled off.

Next, an n-type impurity is implanted at a high concentration using a second resist pattern (not shown) having an opening in a portion corresponding to the source / drain region 25c formed by photolithography. As an example, phosphorus ions are implanted under the conditions of an acceleration energy of 70 keV and a dose amount of 3 × 10 ¹⁵ atm / cm ² . Thereafter, the second resist pattern is peeled off.

Next, an n-type impurity is implanted at a low concentration using a third resist pattern (not shown) formed by photolithography and having an opening in a portion corresponding to the source / drain region 25b as a mask. As an example, phosphorus ions are implanted under the conditions of an acceleration energy of 70 keV and a dose of 3 × 10 ¹³ atm / cm ² . Thereafter, the third resist pattern is peeled off.

  As a result, the semiconductor thin film 25 includes a channel region 25a made of an intrinsic region under the gate electrode 28, source / drain regions 25b made of n-type impurity low concentration regions on both sides thereof, and n-type impurity high concentration regions on both sides thereof. And a source / drain region 25c.

  Next, implanted ion activation treatment is performed in a nitrogen gas atmosphere at a temperature of about 450 ° C. for about 1 hour. Here, the respective ion implantation steps using the first to third resist patterns as masks are not particularly limited to the above order, and may be performed in any order, and other methods such as gates are used. A method including an ion implantation process using the electrodes 28 and 29 as a mask may be used.

  Next, as shown in FIG. 7, on the upper surface of the gate insulating film 27 including the gate electrodes 28 and 29 and the first lower layer connection wiring 47, the first interlayer insulating film 30 ( A film thickness of about 3000 mm is formed. Next, contact holes 33 and 34 are continuously formed in the first interlayer insulating film 30 and the gate insulating film 27 on the source / drain regions 25c and 26b of the semiconductor thin films 25 and 26 by a photolithography method. A contact hole 46 is formed in the first interlayer insulating film 30 on the connection pad portion of the first lower layer connection wiring 47.

  Next, a conductor layer made of a molybdenum film (having a thickness of about 5000 mm) formed by sputtering is patterned in the contact holes 33, 34, and 46 and on the upper surface of the first interlayer insulating film 30 by photolithography. Thus, the conductor layers 35 and 36 are formed to be connected to the source / drain regions 25c and 26b through the contact holes 33 and 34, and the first upper layer connection wiring 45 is formed through the contact hole 46 to the first The external connection terminal 7 is formed by connecting to the connection pad portion of the lower layer connection wiring 47, and the external connection terminal 7, the second lower layer connection wiring 50, and the conductor layers 35 and 36 including the source / drain electrodes are connected. Connection wiring (not shown) is formed.

  Next, as shown in FIG. 8, the first interlayer insulation including the external connection terminal 7, the conductor layers 35 and 36 including the source / drain electrodes, the first upper layer connection wiring 45 and the second lower layer connection wiring 50. A second interlayer insulating film 37 (film thickness of about 3000 mm) made of silicon nitride is formed on the upper surface of the film 30 by plasma CVD. Next, a conductive layer made of a chromium film (having a film thickness of about 1000 mm) formed by sputtering is patterned on the upper surface of the second interlayer insulating film 37 by photolithography, so that the bottom gate electrode 9 and the second gate electrode 9 and the second interlayer insulating film 37 are patterned. 3 lower layer connection wiring 53 is formed.

  Next, as shown in FIG. 9, a bottom gate insulating film 38 (made of silicon nitride) is formed on the upper surface of the second interlayer insulating film 37 including the bottom gate electrode 9 and the third lower layer connection wiring 53 by plasma CVD. A semiconductor thin film forming layer 41a (film thickness of about 500 mm) made of intrinsic amorphous silicon and a channel protective film forming layer 42a (film thickness of about 1000 mm) made of silicon nitride are successively formed. In this case, the semiconductor thin film forming layer 41a made of intrinsic amorphous silicon is formed under a temperature condition of about 300 ° C. as in the case of forming the amorphous silicon thin film 61 shown in FIG.

  Next, the channel protective film forming layer 42a is patterned by photolithography to form the channel protective film 42 as shown in FIG. Next, as shown in FIG. 11, an ohmic contact layer forming layer 43a (film thickness of about 250 mm) made of n-type amorphous silicon is formed on the upper surface of the semiconductor thin film forming layer 41a including the channel protective film 42 by plasma CVD. Is deposited. Also in this case, the ohmic contact layer forming layer 43a made of n-type amorphous silicon is formed under a temperature condition of about 300 ° C. as in the case of forming the amorphous silicon thin film 61 shown in FIG.

  Next, the ohmic contact layer 43 and the semiconductor thin film 41 are continuously patterned by photolithography to form the ohmic contact layer 43 and the semiconductor thin film 41 as shown in FIG. Next, as shown in FIG. 13, a conductor layer made of a chromium film (having a thickness of about 500 mm) formed by sputtering is formed on the upper surfaces of the ohmic contact layer 43 and the bottom gate insulating film 38 by photolithography. As a result, the source / drain electrodes 10 and the fourth lower layer connection wiring 56 are formed.

  Next, as shown in FIG. 14, a top gate insulating film 39 (film) made of silicon nitride is formed on the upper surface of the bottom gate insulating film 38 including the source / drain electrodes 10 and the fourth lower layer connection wiring 56 by plasma CVD. A film having a thickness of about 3000 mm is formed.

  Next, contact holes 49 are continuously formed in the top gate insulating film 39, the bottom gate insulating film 38, and the second interlayer insulating film 37 on the connection pad portion of the second lower layer connection wiring 50 by photolithography. In addition, contact holes 52 are continuously formed in the top gate insulating film 39 and the bottom gate insulating film 38 on the connection pad portion of the third lower layer connection wiring 53, and on the connection pad portion of the fourth lower layer connection wiring 56. A contact hole 55 is formed in the top gate insulating film 39 in FIG.

  Next, a conductive layer made of an ITO film (having a thickness of about 500 mm) formed by sputtering is patterned in the contact holes 49, 52, 55 and on the top surface of the top gate insulating film 39 by photolithography. The second upper layer connection wiring 48 is formed by connecting to the connection pad portion of the second lower layer connection wiring 50 through the contact hole 49, and the third upper layer connection wiring 51 is formed through the contact hole 52. The fourth upper layer connection wiring 54 is formed to be connected to the connection pad portion of the fourth lower layer connection wiring 56 through the contact hole 55, and is further formed. A top gate electrode 8 is formed.

  Next, as shown in FIG. 2, the upper surface of the top gate insulating film 39 including the second to fourth upper layer connection wirings 48, 51, 54 and the top gate electrode 8 is formed on the upper surface made of silicon nitride by plasma CVD. A coating film 40 (film thickness of about 6000 mm) is formed. Next, the opening 44 is continuously formed in the overcoat film 40, the top gate insulating film 39, the bottom gate insulating film 38, and the second interlayer insulating film 37 on the external connection terminal 7 by photolithography. Thus, the thin film transistor panel shown in FIG. 2 is obtained.

  In the above manufacturing method, the semiconductor thin film 41 made of amorphous silicon of the photoelectric conversion type thin film transistor 3 is provided on the upper layer side of the semiconductor thin films 25 and 26 made of polysilicon of the thin film transistors 21 and 22 for the drive circuit section. After forming the semiconductor thin films 25 and 26 made of polysilicon of the thin film transistors 21 and 22 for the driving circuit section, the semiconductor thin film 41 made of amorphous silicon of the photoelectric conversion type thin film transistor 3 may be formed on the upper layer. The entire amorphous silicon thin film 61 formed may be crystallized to form the polysilicon thin film 62. As in the prior art, specific regions of the formed amorphous silicon thin film are selectively crystallized. This eliminates the need for such processes, simplifies the process, and reduces manufacturing costs. It is possible to reduce the.

  Further, in the above manufacturing method, the semiconductor thin film 41 of the photoelectric conversion type thin film transistor 3 is formed on the upper side of the semiconductor thin films 25 and 26 of the thin film transistors 21 and 22 for the drive circuit section, and the thin film transistors 21 and 22 for the drive circuit section Since the photoelectric conversion type thin film transistor 3 is formed separately in different layers, the thin film transistors 21 and 22 for the drive circuit section and the photoelectric conversion type thin film transistor 3 can be disposed sufficiently close to each other, and the entire apparatus Can be further reduced, and as a result, the entire apparatus can be further miniaturized.

  In the above manufacturing method, as shown in FIG. 3, the amorphous silicon thin film 61 is formed at a relatively low temperature condition (approximately about 300 ° C.), and then the amorphous silicon thin film 61 is crystallized to form a polysilicon thin film 62. Since the amorphous silicon thin film 41a is formed under a relatively low temperature condition (approximately 300 ° C.) as shown in FIG. 9, the process is performed under a relatively high temperature condition (approximately 600 ° C.). Each element characteristic of the thin film transistors 21 and 22 for the circuit portion and the photoelectric conversion type thin film transistor 3 can be maintained well.

  That is, contrary to the above, after the amorphous silicon thin film 41a is formed at a relatively low temperature condition (approximately 300 ° C.) and then the semiconductor thin film 41 is formed, the amorphous silicon thin film 61 is formed at a relatively low temperature condition (approximately When the step of forming the polysilicon thin film 62 by crystallizing the amorphous silicon thin film 61 and then forming the polysilicon thin film 62 at a relatively high temperature condition (approximately 600 ° C.) is performed first. Since dehydrogenation proceeds in the semiconductor thin film 41 made of amorphous silicon, sufficient electron mobility cannot be realized in the photoelectric conversion type thin film transistor 3, and there is a possibility that a phenomenon in which element characteristics are deteriorated may occur.

  On the other hand, in the above manufacturing method, the semiconductor thin film 41 made of amorphous silicon that can be formed at a relatively low temperature after the semiconductor thin films 25 and 26 made of polysilicon that require a relatively high temperature condition are formed. Since it is formed, the element characteristics of the photoelectric conversion type thin film transistor 3 can be maintained well while the element characteristics of the thin film transistors 21 and 22 for the drive circuit section are maintained well.

  Further, in the above manufacturing method, when the contact hole (including the opening) forming step is viewed, as shown in FIG. 7, the conductor layers 35 and 36 including the source and drain electrodes and the source and drain of the semiconductor thin films 25 and 26 are formed. Contact holes 33 and 34 for connecting the regions 25c and 26b and a contact hole 46 for connecting the first upper layer connection wiring 45 and the first lower layer connection wiring 47 are formed at the same time, as shown in FIG. Thus, contact holes 49, 52, 55 for connecting the second to fourth upper layer connection wirings 48, 51, 54 and the second to fourth lower layer connection wirings 50, 53, 56 are simultaneously formed, In addition, as shown in FIG. 2, since the opening 44 for exposing the external connection terminal 7 is formed, the contact hole (including the opening) forming process is relatively small as three times. It can be, to simplify the process, it is possible to reduce the manufacturing cost.

(Second Embodiment)
FIG. 15 is a sectional view similar to FIG. 2 of a thin film transistor panel according to a second embodiment of the present invention. In this thin film transistor panel, the main difference from the case shown in FIG. 2 is that the second interlayer insulating film 37 is not provided between the first interlayer insulating film 30 and the bottom gate insulating film 38, and the top gate insulating film 39. A second interlayer insulating film 37 is provided between the first interlayer insulating film 37 and the overcoat film 40 so as to cover the top gate electrode 8 of the photoelectric conversion type thin film transistor 3. The conductor layers 35 and 36 including the source and drain electrodes 21 and 22, the external connection terminals 7, and the conductor layers for forming the first to fourth upper layer connection wirings 45, 48, 51 and 54 are provided. .

  That is, in the thin film transistors 21 and 22 for the driving circuit portion, the conductor layers 35 and 36 including the source / drain electrodes made of molybdenum provided on the upper surface of the second interlayer insulating film 37 are formed on the second interlayer. The top surface of the second base insulating film 24 through the insulating film 37, the top gate insulating film 39, the bottom gate insulating film 38, the first interlayer insulating film 30 and the contact holes 33 and 34 provided in the gate insulating film 27. Are connected to the source / drain regions 25c, 26b of the semiconductor thin films 25, 26 provided on the substrate.

  In the portion of the external connection terminal 7, the external connection terminal 7 made of molybdenum provided on the upper surface of the second interlayer insulating film 37 is exposed through the opening 44 provided in the overcoat film 40.

  In the first interlayer contact portion, the first upper layer connection wiring 45 made of molybdenum provided on the upper surface of the second interlayer insulating film 37 includes the second interlayer insulating film 37, the top gate insulating film 39, and the bottom. A contact hole 46 provided in the gate insulating film 38 and the first interlayer insulating film 30 is connected to a connection pad portion of a first lower layer connection wiring 47 made of molybdenum provided on the upper surface of the gate insulating film 27. ing.

  In the second interlayer contact portion, the second upper layer connection wiring 48 made of molybdenum provided on the upper surface of the second interlayer insulating film 37 includes the second interlayer insulating film 37, the top gate insulating film 39, and the bottom. A contact hole 49 provided in the gate insulating film 38 is connected to a connection pad portion of a second lower layer connection wiring 50 made of chromium provided on the upper surface of the first interlayer insulating film 30.

  In the third interlayer contact portion, the third upper layer connection wiring 51 made of molybdenum provided on the upper surface of the second interlayer insulating film 37 is provided in the second interlayer insulating film 37 and the top gate insulating film 39. The contact pad 52 is connected to the connection pad portion of the third lower layer connection wiring 53 made of chromium provided on the upper surface of the bottom gate insulating film 38.

  In the fourth interlayer contact portion, the fourth upper layer connection wiring 54 made of molybdenum provided on the upper surface of the second interlayer insulating film 37 has a contact hole 55 provided in the second interlayer insulating film 37. And connected to the connection pad portion of the fourth lower layer connection wiring 56 made of ITO provided on the upper surface of the top gate insulating film 39.

  Next, electrical connection of each unit shown in FIG. 15 will be described. The bottom gate electrode 9 of the photoelectric conversion type thin film transistor 3 is connected to the second drive circuit via the second lower layer connection wiring 50 and the second upper layer connection wiring 48, that is, via the bottom gate line 12 shown in FIG. Connected to the conductor layers 35 and 36 including the source and drain electrodes of the thin film transistors 21 and 22 of the portion (bottom gate driver) 6.

  One source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected to the third via the third lower layer connection wiring 53 and the third upper layer connection wiring 51, that is, through the drain line 13 shown in FIG. The drive circuit section (drain driver) 6 is connected to the conductor layers 35 and 36 including the source and drain electrodes of the thin film transistors 21 and 22 of the drive circuit section (drain driver) 6.

  The other source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected to the external connection terminal via the third lower layer connection wiring 53 and the third upper layer connection wiring 51, that is, via a ground line not shown in FIG. 7 is connected to the grounding external connection terminal.

  The top gate electrode 8 of the photoelectric conversion type thin film transistor 3 is connected to the first drive circuit through the fourth lower layer connection wiring 56 and the fourth upper layer connection wiring 54, that is, through the top gate line 11 shown in FIG. Connected to the conductor layers 35 and 36 including the source and drain electrodes of the thin film transistors 21 and 22 of the portion (top gate driver) 4.

  The gate electrodes 28 and 29 of the thin film transistors 21 and 22 for the drive circuit section are connected to the external connection terminal 7 through the first lower layer connection wiring 47 and the first upper layer connection wiring 45. The conductor layers 35 and 36 including the source / drain electrodes of the thin film transistors 21 and 22 for the drive circuit section are connected to each other through a connection wiring (not shown) provided on the upper surface of the second interlayer insulating film 37. Connected to terminal 7.

  Next, in the method for manufacturing the thin film transistor panel, a process after the top gate insulating film 39 is formed will be described. First, the top gate electrode 8 and the fourth lower layer connection wiring 56 are formed on the top surface of the top gate insulating film 39 by patterning an ITO film (having a thickness of about 500 mm) formed by sputtering using photolithography. To do. Next, a second interlayer insulating film 37 (having a thickness of about 2000 mm) made of silicon nitride is formed on the upper surface of the top gate insulating film 39 including the top gate electrode 8 and the fourth lower layer connection wiring 56 by plasma CVD. Film.

  Next, the second interlayer insulating film 37, the top gate insulating film 39, the bottom gate insulating film 38, and the first interlayer insulating film 30 on the source / drain regions 25c and 26b of the semiconductor thin films 25 and 26 are formed by photolithography. In addition, contact holes 33 and 34 are continuously formed in the gate insulating film 27, and the second interlayer insulating film 37, the top gate insulating film 39, and the bottom gate insulating film on the connection pad portion of the first lower layer connection wiring 47 are formed. 38 and the first interlayer insulating film 30 are continuously formed, and the second interlayer insulating film 37, the top gate insulating film 39 and the bottom gate on the connection pad portion of the second lower layer connection wiring 50 are formed. A contact hole 49 is continuously formed in the insulating film 38, and the second interlayer insulating film 3 on the connection pad portion of the third lower layer connection wiring 53 is formed. And continuously forming the contact holes 52 to the top gate insulating film 39 is further formed a fourth contact hole 55 in the second interlayer insulating film 37 on the connection pad portions of the lower connection wiring 56.

  Next, a molybdenum film (having a thickness of about 5000 mm) formed by sputtering is patterned in the contact holes 33, 34, 46, 49, 52, 55 and on the upper surface of the second interlayer insulating film 37 by photolithography. Thus, the conductor layers 35 and 36 are formed to be connected to the source / drain regions 25c and 26b of the semiconductor thin films 25 and 26 through the contact holes 33 and 34, and the first to fourth upper layer connection wirings 45 are formed. , 48, 51, 54 are formed by connecting to the connection pad portions of the first to fourth lower layer connection wirings 47, 50, 53, 56 through contact holes 46, 49, 52, 55, and external connection terminals 7 is formed.

  Next, on the upper surface of the second interlayer insulating film 37 including the conductor layers 35 and 36 including the source / drain electrodes, the first to fourth upper layer connection wirings 45, 48, 51 and 54 and the external connection terminal 7, An overcoat film 40 (film thickness of about 6000 mm) made of silicon nitride is formed by plasma CVD. Next, an opening 44 is formed in the overcoat film 40 on the external connection terminal 7 by photolithography. Thus, the thin film transistor panel shown in FIG. 15 is obtained.

  In the above manufacturing method, when the contact hole (including the opening) forming step is viewed, the contact hole 33 for connecting the conductor layers 35 and 36 to the source / drain regions 25c and 26b of the semiconductor thin films 25 and 26 is provided. , 34 and the first to fourth upper layer connection wirings 45, 48, 51, 54 and the first to fourth lower layer connection wirings 47, 50, 53, 56, contact holes 46, 49, 52, 55 and the opening 44 for exposing the external connection terminal 7 are formed, the contact hole (including the opening) forming step is performed twice, which is more than in the case of the first embodiment. Further, it can be reduced once, and the manufacturing process can be reduced by further simplifying the process.

(Third embodiment)
FIG. 16 is a sectional view similar to FIG. 15 of a thin film transistor panel as a third embodiment of the present invention. In this thin film transistor panel, the difference from the case shown in FIG. 15 is that a fourth upper layer connection wiring 54 made of ITO is formed on the top gate insulating film 39 on the top gate insulating film 39 in the fourth interlayer contact portion. This is that the contact hole 55 provided is connected to the connection pad portion of the fourth lower layer connection wiring 56 made of chromium provided on the upper surface of the bottom gate insulating film 38. In this case, the contact hole (including the opening) forming process is performed three times because the process for forming the contact hole 55 in the top gate insulating film 39 is dedicated thereto.

  By the way, in this thin film transistor panel, the top gate electrode 8 of the photoelectric conversion type thin film transistor 3 includes the fourth upper layer connection wiring 54, the fourth lower layer connection wiring 56, the third lower layer connection wiring 53, and the third upper layer connection wiring. The conductive layers 35 and 36 including the source and drain electrodes of the thin film transistors 21 and 22 for the driving circuit section are connected via the 51.

  In this case, since the fourth upper layer connection wiring 54 made of ITO is connected to the connection pad portion of the fourth lower layer connection wiring 56 made of chrome, an ITO film formed on the upper surface of the top gate insulating film 39 is used. When the fourth upper layer connection wiring 54 and the top gate electrode 8 are formed by patterning using an etching solution for ITO, the fourth upper layer connection wiring 54 and the top gate electrode 8 made of ITO are oxidized by the battery reaction. The fourth lower layer connection wiring 56 made of chromium is reduced.

  However, since the ITO film is originally an oxide, the fourth upper layer connection wiring 54 and the top gate electrode 8 made of ITO are practically unchanged even when placed in an oxidized state. Further, the fourth lower layer connection wiring 56 made of chromium is reduced, but does not change substantially. On the other hand, the conductor layers 35 and 36 including the source / drain electrodes of the thin film transistors 21 and 22 for the driving circuit section, the first to third upper layer connection wirings 45, 48 and 51, and the external connection terminal 7 are made of ITO. 4 is not directly connected to the upper layer connection wiring 54 and the top gate electrode 8, and therefore, corrosion due to a battery reaction due to connection with the upper connection wiring 54 and the top gate electrode 8 does not occur.

  That is, when it is necessary to prevent corrosion due to the battery reaction due to the connection with the ITO film, a relatively expensive single-layer structure of a refractory metal such as Mo, Cr, W, Ta, Ti or the like and Al and Although it was necessary to have a laminated structure, according to the configuration of the present embodiment, since it is not necessary to prevent corrosion due to battery reaction, the conductor layer including the source / drain electrodes of the thin film transistors 21 and 22 for the drive circuit section 35, 36, the first to third upper layer connection wirings 45, 48, 51 and the external connection terminal 7 may have a single layer structure of Al that is inexpensive, low stress, and low resistance. Thereby, the manufacturing cost can be reduced.

(Fourth embodiment)
FIG. 17 is a sectional view similar to FIG. 15 of a thin film transistor panel as a third embodiment of the present invention. In this thin film transistor panel, the difference from the case shown in FIG. 15 is that the second interlayer insulating film 37 is not provided, and the top gate insulating film 39 has a conductive surface including an external connection terminal 7 made of molybdenum and source / drain electrodes. Body layers 35, 36 and first to fourth upper layer connection wirings 45, 48, 51, 54 are provided, and the fourth upper layer connection wiring 54 is a fourth layer made of ITO provided on the same surface. This is that the connection is made on the connection pad portion of the lower layer connection wiring 56. In this case, since the second interlayer insulating film 37 is not provided, the number of steps can be reduced accordingly.

(Fifth embodiment)
FIG. 18 is a sectional view similar to FIG. 16 of a thin film transistor panel as a fifth embodiment of the present invention. In this thin film transistor panel, the difference from the case shown in FIG. 16 is that the first interlayer insulating film 30 has a two-layer structure of a lower interlayer insulating film 30A made of silicon oxide and an upper interlayer insulating film 30B made of silicon nitride. It is.

  Here, in the case shown in FIG. 16, the contact holes 33, 34, 45, 49 and 52 are formed by dry etching using a parallel plate type RIE (reactive ion etching) apparatus which is a relatively inexpensive apparatus. Then, the etching rate of the second interlayer insulating film 37 made of silicon nitride, the top gate insulating film 39, the bottom gate insulating film 38, and the first interlayer insulating film 30 and the etching of the first lower layer connection wiring 47 made of molybdenum are performed. Since there is no difference with the speed, the connection pad portion of the first lower layer connection wiring 47 is etched.

  In order to avoid such etching of the connection pad portion of the first lower layer connection wiring 47, dry etching using an ICP (inductively coupled plasma) apparatus having a high density plasma, which is a relatively expensive apparatus. In this case, the manufacturing cost increases, which is not preferable.

  Etching of the second interlayer insulating film 37 made of silicon nitride, the top gate insulating film 39, the bottom gate insulating film 38, the first interlayer insulating film 30 and the gate insulating film 27 made of silicon oxide is made of molybdenum. There is a method of performing wet etching using buffered hydrofluoric acid in which the first lower layer connection wiring 47 is not etched, but in this case, since it is wet etching, the processing dimensions of the contact holes 33, 34, 45, 49, 52 The conversion difference increases, and as a result, the areas of the conductor layers 35 and 36 including the source / drain electrodes and the first to third upper layer connection wirings 45, 48, and 51 increase, and the circuit area increases. This is not preferable.

  On the other hand, in the case shown in FIG. 18, the first interlayer insulating film 30 includes a lower interlayer insulating film 30A (thickness of about 250 mm) made of silicon oxide and an upper interlayer insulating film 30B (thickness of about 3000 mm) made of silicon nitride. ).

  When forming the contact holes 33, 34, 45, 49, 52, first, a dry etching using a mixed gas of SF4 and O2 is performed using a parallel plate RIE apparatus which is a relatively inexpensive apparatus. The second interlayer insulating film 37 made of silicon nitride and the top gate insulating film 39 on the connection pad portions of the source / drain regions 25c, 26b of the semiconductor thin films 25, 26 and the first lower layer connection wiring 47 made of molybdenum. The contact holes 33, 34, 46 are formed in the bottom gate insulating film 38 and the upper interlayer insulating film 30B, and the second interlayer insulating film 37 made of silicon nitride on the second upper layer connection wiring 50 made of chromium, the top A contact hole 49 is formed in the gate insulating film 39 and the bottom gate insulating film 38, and a third layer made of chromium is formed. Forming a contact hole 52 in the second interlayer insulating film 37 and the top gate insulating film 39 made of silicon nitride in layer connection wiring 53.

  In this case, the etching rates of the lower interlayer insulating film 30A made of silicon oxide and the second and third lower layer connection wirings 50 and 53 made of chrome are 1/10 or less of the etching rate of the silicon nitride film. The dry etching can be reliably and easily stopped on the upper surfaces of the lower interlayer insulating film 30A and the second and third lower layer connection wirings 50 and 53.

  Next, wet etching using buffered hydrofluoric acid is performed, and contact holes 33 and 34 are formed in the lower interlayer insulating film 30A made of silicon oxide and the gate insulating film 27 on the source / drain regions 25c and 26b of the semiconductor thin films 25 and 26. The contact hole 46 is formed in the lower interlayer insulating film 30A made of silicon oxide on the connection pad portion of the first lower layer connection wiring 47 made of molybdenum.

  In this case, the etching rates of the source / drain regions 25c and 26b of the semiconductor thin films 25 and 26, the first lower layer connection wiring 47 made of molybdenum, and the second and third lower layer connection wirings 50 and 53 made of chromium are silicon oxide. Therefore, the wet etching at this time is performed on the upper surfaces of the source / drain regions 25c, 26b of the semiconductor thin films 25, 26 and the first to third lower layer connection wirings 47, 50, 53. Thus, it can be stopped reliably and easily.

  In addition, each formation of the contact hole 55 in the portion of the fourth contact and the opening 44 in the portion of the external connection terminal 7 uses a parallel plate type RIE device which is a relatively inexpensive device, and mixes SF4 and O2. This is performed by dry etching using a gas. Among these, when the material of the external connection terminal 7 is aluminum, the etching rate of the external connection terminal 7 is 1/10 or less of the etching rate of the overcoat film 40 made of silicon nitride. Etching can be reliably and easily stopped on the upper surface of the external connection terminal 7. Further, the gate electrodes 28 and 29 and the first lower layer connection wiring 47 of the thin film transistors 21 and 22 for the drive circuit may be formed of other refractory metal materials such as W, Ti and Ta instead of molybdenum.

(Sixth embodiment)
FIG. 19 is a sectional view similar to FIG. 16 of a thin film transistor panel as a sixth embodiment of the present invention. The thin film transistor panel is different from the case shown in FIG. 16 in that the first interlayer insulating film 30 is formed of silicon oxide. Thereby, the contact holes 33, 34, 46, 49, 52, 55 and the opening 44 can be formed by the same method as in the case of the fourth embodiment shown in FIG. Further, since the first interlayer insulating film 30 has a single-layer structure of silicon oxide, the number of film formation can be reduced by one compared to the case shown in FIG.

(Seventh embodiment)
FIG. 20 is a sectional view similar to FIG. 16 of a thin film transistor panel as a seventh embodiment of the present invention. In this thin film transistor panel, the main difference from the case shown in FIG. 16 is that the first interlayer insulating film 30 is not provided, and the bottom gate insulating film 38 is formed of a lower bottom gate insulating film 38A made of silicon oxide and an upper layer made of silicon nitride. The two-layer structure with the bottom gate insulating film 38B is used, and the interlayer contact portion is the first to third interlayer contact portions.

  That is, source / drain electrodes 28 and 29 made of molybdenum (thickness of about 3000 mm), first lower layer connection wiring 47 and bottom gate electrode 9 are provided on the upper surface of a gate insulating film 27 (thickness of about 1000 mm) made of silicon oxide. It has been. On the upper surface of the gate insulating film 27 including the source / drain electrodes 28 and 29, the first lower layer connection wiring 47 and the bottom gate electrode 9, a lower bottom gate insulating film 38A (thickness of about 250 mm) made of silicon oxide and silicon nitride An upper bottom gate insulating film 38B (having a thickness of about 2500 mm) is provided.

  On the upper surface of the upper layer bottom gate insulating film 38B, second and third lower layer connection wirings 50 and 53 made of chromium (film thickness of about 500 mm), the source / drain electrodes 10 and the like are provided. A top gate insulating film 39 (thickness of about 3000 mm) made of silicon nitride is provided on the upper surface of the upper bottom gate insulating film 38B including the second and third lower layer connection wirings 50 and 53 and the source / drain electrodes 10 and the like. Yes.

  On the top surface of the top gate insulating film 39, a third upper layer connection wiring 51 and a top gate electrode 8 made of ITO (film thickness of about 500 mm) are provided. In this case, the third upper layer connection wiring 51 is connected to the connection pad portion of the third lower layer connection wiring 53 through the contact hole 52 provided in the top gate insulating film 39. On the upper surface of the top gate insulating film 39 including the third upper layer connection wiring 51 and the top gate electrode 8, an interlayer insulating film 37 (about 2000 mm thick) made of silicon nitride is provided.

  On the upper surface of the interlayer insulating film 37, there are provided external connection terminals 7 made of aluminum (film thickness of about 5000 mm), conductor layers 35 and 36 including source / drain electrodes, and first and second upper layer connection wirings 45 and 48. ing. In this case, the conductor layers 35 and 36 including the source / drain electrodes are provided on the interlayer insulating film 37, the top gate insulating film 39, the upper bottom gate insulating film 38B, the lower bottom gate insulating film 38A, and the gate insulating film 27. The contact holes 33 and 34 are connected to the source / drain regions 25c and 26b of the semiconductor thin films 25 and 26, respectively.

  The first upper layer connection wiring 45 is connected to the first lower layer connection wiring 47 through contact holes 46 provided in the interlayer insulating film 37, the top gate insulating film 39, the upper layer bottom gate insulating film 38B, and the lower layer bottom gate insulating film 38A. It is connected to the connection pad part. The second upper layer connection wiring 48 is connected to the connection pad portion of the second lower layer connection wiring 50 through a contact hole 49 provided in the interlayer insulating film 37 and the top gate insulating film 39.

  An overcoat film 40 (film) made of silicon nitride is formed on the upper surface of the interlayer insulating film 37 including the external connection terminals 7, the conductor layers 35 and 36 including the source / drain electrodes, and the first and second upper layer connection wirings 45 and 48. A thickness of about 6000 mm). The external connection terminal 7 is exposed through the opening 44 provided in the overcoat film 40.

  Next, electrical connection of each unit shown in FIG. 20 will be described. The bottom gate electrode 9 of the photoelectric conversion type thin film transistor 3 is connected to the second drive circuit through the first lower layer connection wiring 47 and the first upper layer connection wiring 45, that is, through the bottom gate line 12 shown in FIG. Connected to the conductor layers 35 and 36 including the source and drain electrodes of the thin film transistors 21 and 22 of the portion (bottom gate driver) 6.

  One source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected to the third via the second lower layer connection wiring 50 and the second upper layer connection wiring 48, that is, through the drain line 13 shown in FIG. The drive circuit section (drain driver) 6 is connected to the conductor layers 35 and 36 including the source and drain electrodes of the thin film transistors 21 and 22 of the drive circuit section (drain driver) 6.

  The other source / drain electrode 10 of the photoelectric conversion type thin film transistor 3 is connected to the external connection terminal via the second lower layer connection wiring 50 and the second upper layer connection wiring 48, that is, via a ground line not shown in FIG. 7 is connected to the grounding external connection terminal.

  The top gate electrode 8 of the photoelectric conversion type thin film transistor 3 is connected via the third upper layer connection wiring 51, the third lower layer connection wiring 53, the second lower layer connection wiring 50, and the second upper layer connection wiring 48. 1 is connected to the conductor layers 35 and 36 including the source and drain electrodes of the thin film transistors 21 and 22 of the first drive circuit section (top gate driver) 4 through the top gate line 11 shown in FIG.

  The gate electrodes 28 and 29 of the thin film transistors 21 and 22 for the drive circuit section are connected to the external connection terminal 7 through the first lower layer connection wiring 47 and the first upper layer connection wiring 45. The conductor layers 35 and 36 including the source / drain electrodes of the thin film transistors 21 and 22 for the driving circuit section are connected to the external connection terminal 7 via connection wiring (not shown) provided on the upper surface of the interlayer insulating film 37. It is connected.

  In this thin film transistor panel, the bottom gate insulating film 38 has a two-layer structure of a lower bottom gate insulating film 38A made of silicon oxide and an upper bottom gate insulating film 38B made of silicon nitride, whereby contact holes 33, 34, 46, 49, 52 and the opening 44 can be formed by the same method as in the fourth embodiment shown in FIG.

(Eighth embodiment)
FIG. 21 is a sectional view similar to FIG. 2 of a thin film transistor panel as an eighth embodiment of the present invention. The thin film transistor panel is greatly different from the case shown in FIG. 2 in that the thin film transistors 21 and 22 for the drive circuit shown in FIG. 2 have a top gate structure, but a bottom gate structure. In this case, only the base insulating film 23 made of silicon nitride is provided on the upper surface of the glass substrate 1 as the base insulating film.

  Next, an example of a method for manufacturing this thin film transistor panel will be described. First, as shown in FIG. 22, a base insulating film 23 (film thickness of about 2000 mm) made of silicon nitride is formed on the upper surface of the glass substrate 1 by plasma CVD. Next, a molybdenum film (having a thickness of about 1000 mm) formed by sputtering is patterned on the upper surface of the base insulating film 23 by photolithography, whereby the gate electrodes 28 and 29 and the first lower layer connection wiring 47 are formed. Form.

  Next, on the upper surface of the base insulating film 23 including the gate electrodes 28 and 29 and the first lower layer connection wiring 47, a gate insulating film 27 (about 1000 mm thick) made of silicon oxide and an amorphous silicon thin film 61 are formed by plasma CVD. (Film thickness of about 500 mm) is continuously formed. Also in this case, the step of forming the amorphous silicon thin film 61 is performed under a temperature condition where the maximum temperature is approximately 300 ° C. Next, dehydrogenation treatment is performed for about 1 hour at a temperature of about 500 ° C. in a nitrogen gas atmosphere.

  Next, by irradiating the amorphous silicon thin film 61 with an excimer laser from the upper surface side, the amorphous silicon thin film 61 is crystallized to form a polysilicon thin film 62. Also in this case, the process of crystallizing the amorphous silicon thin film 61 to form the polysilicon thin film 62 is performed under a temperature condition where the maximum temperature is approximately 600 ° C.

Next, a p-type impurity is implanted at a high concentration using a first resist pattern (not shown) formed by photolithography and having an opening in a portion corresponding to the source / drain region 26b. As an example, boron ions are implanted under the conditions of an acceleration energy of 10 keV and a dose of 1 × 10 ¹⁵ atm / cm ² . Thereafter, the first resist pattern is peeled off.

Next, an n-type impurity is implanted at a high concentration using a second resist pattern (not shown) having an opening in a portion corresponding to the source / drain region 25c formed by photolithography. As an example, phosphorus ions are implanted under the conditions of an acceleration energy of 10 keV and a dose of 1 × 10 ¹⁵ atm / cm ² . Thereafter, the second resist pattern is peeled off.

Next, an n-type impurity is implanted at a low concentration using a third resist pattern (not shown) formed by photolithography and having an opening in a portion corresponding to the source / drain region 25b as a mask. As an example, phosphorus ions are implanted under the conditions of an acceleration energy of 10 keV and a dose of 1 × 10 ¹³ atm / cm ² . Thereafter, the third resist pattern is peeled off. Next, implanted ion activation treatment is performed in a nitrogen gas atmosphere at a temperature of about 450 ° C. for about 1 hour.

  Next, by patterning the polysilicon thin film 62 by photolithography, semiconductor thin films 25 and 26 are formed as shown in FIG. In this state, the semiconductor thin film 25 includes a channel region 25a composed of an intrinsic region on the gate electrode 28, a source / drain region 25b composed of n-type impurity low concentration regions on both sides thereof, and a high n-type impurity concentration on both sides thereof. It has a source / drain region 25c composed of a region. The semiconductor thin film 26 has a channel region 26a made of an intrinsic region on the gate electrode 29 and source / drain regions 26b made of p-type impurity high concentration regions on both sides thereof.

  Next, as shown in FIG. 24, on the upper surface of the gate insulating film 27 including the semiconductor thin films 25 and 26, a first interlayer insulating film 30 (thickness of about 3000 mm) made of silicon oxide is formed by plasma CVD. To do. Next, contact holes 33 and 34 are formed in the first interlayer insulating film 30 on the source / drain regions 25c and 26b of the semiconductor thin films 25 and 26 by photolithography, and the connection of the first lower layer connection wiring 47 is performed. Contact holes 46 are continuously formed in the first interlayer insulating film 30 and the gate insulating film 27 on the pad portion.

  Next, a molybdenum film (having a thickness of about 5000 mm) formed by sputtering is patterned in the contact holes 33, 34, and 46 and on the upper surface of the first interlayer insulating film 30 by photolithography, thereby providing a conductor. The layers 35 and 36 are formed to be connected to the source / drain regions 25 c and 26 b through the contact holes 33 and 34, and the first upper layer connection wiring 45 is connected to the first lower layer connection wiring 47 through the contact hole 46. A connection wiring (not shown) that connects the external connection terminal 7 to the external connection terminal 7, the second lower layer connection wiring 50, and the conductor layers 35 and 36 including the source / drain electrodes. Z). Since the following steps are the same as those in the first embodiment, a description thereof will be omitted.

  In the above manufacturing method, as shown in FIG. 22, since boron ions and phosphorus ions are directly implanted into the polysilicon semiconductor thin film 62, it is inexpensive without using an expensive high acceleration (up to 80 keV) ion implantation apparatus. Boron ions and phosphorus ions can be implanted using a low-acceleration (-10 keV) ion implantation apparatus.

  The ion implantation and activation treatment may be performed after the device area is formed as shown in FIG. Here, also in the first embodiment, the ion implantation and activation treatment may be performed after forming the polysilicon thin film 62 as shown in FIG. 3, and as shown in FIG. You may carry out after forming.

(Other embodiments)
In each of the above-described embodiments, the case where the drive circuit unit is constituted by a CMOS thin film transistor made of a polysilicon thin film transistor has been described. You may make it comprise by a combination with a thin-film transistor.

  In each of the above embodiments, the external connection terminal 7 has a single-layer structure made of molybdenum simultaneously with the formation of the conductor layers 35 and 36 including the source and drain electrodes made of molybdenum of the thin film transistors 21 and 22 for the drive circuit section. However, the present invention is not limited to this, and may be formed simultaneously with the formation of an electrode on another layer (for example, the bottom gate electrode 9), or may be formed simultaneously with the formation of an electrode on a plurality of layers. A laminated structure may be used.

  Further, for example, in the first embodiment (see FIG. 2), the first and second interlayer insulating films 30 and 37 may be a single layer of a silicon oxide film instead of a single layer of a silicon nitride film, Also, a plurality of types of laminated structures may be used. Further, for example, in the eighth embodiment (see FIG. 21), the gate insulating film 27 is not a single layer of a silicon oxide film, but may have a two-layer structure of a lower silicon nitride film and an upper silicon oxide film. In addition, the first interlayer insulating film 30 may not be a single layer of a silicon oxide film, but may have a two-layer structure of a lower silicon oxide film and an upper silicon nitride film. Furthermore, the second interlayer insulating film 37 may be a single layer of a silicon oxide film instead of a single layer of a silicon nitride film, or may be a multi-layered structure.

  Further, in each of the above embodiments, the case where the thin film transistor panel of the present invention is applied to an image reading apparatus has been described. However, the present invention is not limited to this. In short, a thin film transistor panel having a structure in which amorphous silicon thin film transistors are arranged in a matrix in a predetermined region on a substrate and a polysilicon thin film transistor for driving the amorphous silicon thin film transistor is disposed in a peripheral region adjacent to the predetermined region. I just need it.

  For example, a well-known display pixel including a light emitting element such as a liquid crystal capacitor or an organic EL element in a predetermined region on a substrate (specifically, a liquid crystal pixel composed of a liquid crystal capacitor and a pixel transistor, an organic EL element and a pixel driving circuit) Are arranged in a matrix, and each display pixel is set in a selected state in a peripheral region adjacent to the predetermined region, and a predetermined gradation signal is supplied to the display pixel. The present invention can also be applied to a known image display device provided with a driver (scanning driver, data driver, power supply driver, etc.) that controls to display the image information.

The equivalent circuit top view of the principal part of the thin-film transistor panel as 1st Embodiment of this invention. FIG. 2 is a cross-sectional view illustrating a specific structure of part of the thin film transistor panel illustrated in FIG. 1. FIG. 3 is a cross-sectional view of an initial process in manufacturing the thin film transistor panel shown in FIG. 2. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing similar to FIG. 2 of the thin-film transistor panel as 2nd Embodiment of this invention. Sectional drawing similar to FIG. 15 of the thin-film transistor panel as 3rd Embodiment of this invention. Sectional drawing similar to FIG. 15 of the thin-film transistor panel as 4th Embodiment of this invention. Sectional drawing similar to FIG. 16 of the thin-film transistor panel as 5th Embodiment of this invention. Sectional drawing similar to FIG. 16 of the thin-film transistor panel as 6th Embodiment of this invention. Sectional drawing similar to FIG. 16 of the thin-film transistor panel as 7th Embodiment of this invention. Sectional drawing similar to FIG. 2 of the thin-film transistor panel as 8th Embodiment of this invention. FIG. 22 is a cross-sectional view of an initial process in manufacturing the thin film transistor panel shown in FIG. 21. FIG. 23 is a sectional view of a step following FIG. 22; FIG. 24 is a sectional view of a step following FIG. 23.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Image reading area 3 Photoelectric conversion type thin-film transistor 4-6 Drive circuit part 7 External connection terminal 8 Top gate electrode 9 Bottom gate electrode 10 Source / drain electrode 11 Top gate line 12 Bottom gate line 13 Drain line 21, 22 Thin film transistors 25 and 26 for driving circuits 25 and 26 Semiconductor thin films 28 and 29 Gate electrodes 33 and 34 Contact holes 35 and 36 Conductor layers including source / drain electrodes 41 Semiconductor thin films 42 Channel protective films 43 Ohmic contact layers 44 Openings 45 and 48 , 51, 54 First to fourth upper layer connection wiring 46, 49, 52, 55 Contact hole 47, 50, 53, 56 First to fourth lower layer connection wiring

Claims (30)

On a substrate, a thin film transistor panel provided with a polysilicon thin film transistor having a semiconductor thin film made of polysilicon and a plurality of electrodes, and an amorphous silicon thin film transistor having a semiconductor thin film made of amorphous silicon and a plurality of electrodes,
A first wiring connected to any of the plurality of electrodes of the polysilicon thin film transistor, provided in the same layer with the same conductive material as the electrode, and having a connection pad;
A semiconductor thin film made of amorphous silicon provided above the first wiring via an insulating film;
The amorphous silicon thin film transistors are connected to different electrodes of the plurality of electrodes, are provided in the same layer with the same conductive material as the electrodes, have connection pads, and are different from each other through an insulating film. A plurality of second wirings provided in
Each of the first wiring and the second wiring is opposed to each other through an insulating film and is provided in the same layer and corresponds to each connection pad of the first wiring and the second wiring of the insulating film. A third wiring electrically connected to the first wiring and the second wiring through a plurality of contact holes provided in a place to be
A thin film transistor panel comprising: In the invention of claim 1,
Of the plurality of electrodes of the polysilicon thin film transistor, an electrode not connected to the first wiring is provided in the same layer as the third wiring. In the invention of claim 1,
The amorphous silicon thin film transistor comprises a double gate type thin film transistor provided with a top gate electrode and a bottom gate electrode provided above and below the semiconductor thin film via an insulating film, respectively. In the invention of claim 3,
The thin film transistor panel, wherein the third wiring is provided in the same layer as the top gate electrode of the amorphous silicon thin film transistor. In the invention of claim 4,
The thin film transistor panel, wherein an electrode not connected to the first wiring among the plurality of electrodes of the polysilicon thin film transistor is provided in the same layer as the third wiring. In the invention of claim 3,
The thin film transistor panel, wherein the third wiring is provided on an insulating film provided so as to cover a top gate electrode of the amorphous silicon thin film transistor. In the invention of claim 6,
The thin film transistor panel, wherein an electrode not connected to the first wiring among the plurality of electrodes of the polysilicon thin film transistor is provided in the same layer as the third wiring. In the invention of claim 7,
An upper part of the second wiring is connected to the top gate electrode of the amorphous silicon thin film transistor through an insulating film, and is provided in the same layer with the same conductive material as the top gate electrode. A thin film transistor panel comprising: a fourth wiring electrically connected to the second wiring through a provided contact hole. In the invention of claim 8,
The first wiring is connected to a gate electrode of the polysilicon thin film transistor,
The gate electrode and the first wiring are formed of a metal material whose dry etching rate is not different from that of silicon nitride, and are covered with a lower insulating film made of silicon oxide and an upper insulating film made of silicon nitride. A thin film transistor panel. In the invention of claim 9,
The second wiring is connected to the bottom gate electrode of the amorphous silicon thin film transistor,
The bottom gate electrode and the second wiring are formed of a metal material different from the metal material, and are provided on the upper insulating film. In the invention of claim 9,
The second wiring is connected to the bottom gate electrode of the amorphous silicon thin film transistor,
The bottom gate electrode and the second wiring are formed of a metal material different from the metal material, and are covered with the upper insulating film and the lower insulating film. In the invention of claim 9,
The second wiring is connected to the bottom gate electrode of the amorphous silicon thin film transistor,
The bottom gate electrode and the second wiring are formed of the same metal material as the gate electrode of the polysilicon thin film transistor, and are provided in the same layer as the gate electrode. In the invention of claim 1,
The thin film transistor panel, wherein the polysilicon thin film transistor is a top gate type. In the invention of claim 1,
The thin film transistor panel, wherein the polysilicon thin film transistor is a bottom gate type. In the invention of claim 1,
The amorphous silicon thin film transistors are arranged in a matrix in a predetermined region on the substrate,
The thin film transistor panel, wherein the polysilicon thin film transistor is disposed in a peripheral region adjacent to the predetermined region on the substrate to constitute a drive circuit unit for driving the amorphous silicon thin film transistor. In a method of manufacturing a thin film transistor panel in which a semiconductor thin film made of polysilicon and a polysilicon thin film transistor having a plurality of electrodes and an amorphous silicon thin film transistor having a semiconductor thin film made of amorphous silicon and a plurality of electrodes are provided on a substrate,
Forming a semiconductor thin film made of polysilicon on the substrate;
Forming the polysilicon thin film transistor using the semiconductor thin film made of polysilicon;
Forming a first wiring connected to any of the plurality of electrodes of the polysilicon thin film transistor and made of the same conductive material as the electrode and having a connection pad simultaneously with the electrode;
Forming a semiconductor thin film made of amorphous silicon over an insulating film above the first wiring;
Forming the amorphous silicon thin film transistor by using the semiconductor thin film made of amorphous silicon, and forming the plurality of electrodes in different layers through an insulating film;
Forming a plurality of second wirings connected to different ones of the plurality of electrodes of the amorphous silicon thin film transistor and made of the same conductive material as the electrodes and having connection pads simultaneously with the electrodes; ,
An insulating film is formed on each of the first wiring and the second wiring, and a plurality of contact holes provided at locations corresponding to the connection pads of the first wiring and the second wiring are simultaneously formed. Forming, and
A plurality of third wirings corresponding to each of the plurality of contact holes are simultaneously formed on the insulating film, and the third wiring, the first wiring, and the second wiring are formed through the contact holes. Electrically connecting and
A method for producing a thin film transistor panel, comprising: In the invention of claim 16,
The step of forming the semiconductor thin film made of polysilicon is performed under a first temperature condition,
The method of manufacturing a thin film transistor panel, wherein the step of forming the semiconductor thin film made of amorphous silicon is performed under a second temperature condition where a maximum temperature is lower than the first temperature condition. In the invention of claim 16,
A method of manufacturing a thin film transistor panel, comprising: forming an electrode which is not connected to the first wiring among the plurality of electrodes of the polysilicon thin film transistor simultaneously with the first wiring. In the invention of claim 16,
The method of manufacturing a thin film transistor panel, wherein the amorphous silicon thin film transistor comprises a double gate type thin film transistor having a top gate electrode and a bottom gate electrode provided above and below the semiconductor thin film via an insulating film, respectively. . The invention according to claim 19,
A method of manufacturing a thin film transistor panel, comprising: forming the third wiring simultaneously with a top gate electrode of the amorphous silicon thin film transistor. The invention according to claim 19,
A method of manufacturing a thin film transistor panel, comprising: forming an electrode that is not connected to the first wiring among the plurality of electrodes of the polysilicon thin film transistor simultaneously with the third wiring. The invention according to claim 19,
A method of manufacturing a thin film transistor panel, comprising a step of forming the third wiring on an insulating film formed so as to cover a top gate electrode of the amorphous silicon thin film transistor. In the invention of claim 22,
A method of manufacturing a thin film transistor panel, comprising: forming an electrode that is not connected to the first wiring among the plurality of electrodes of the polysilicon thin film transistor simultaneously with the third wiring. In the invention of claim 22,
Forming a fourth wiring connected to the top gate electrode of the amorphous silicon thin film transistor through an insulating film on the second wiring simultaneously with the same conductive material as the top gate electrode;
A contact hole is simultaneously formed in the insulating film at a location corresponding to the connection pad of the second wiring, and a conductive material is filled in the contact hole by the fourth wiring. Electrically connecting the second wiring;
A method for producing a thin film transistor panel, comprising: In the invention of claim 24,
The first wiring is connected to the gate electrode of the polysilicon thin film transistor, and is formed simultaneously with the gate electrode by a metal material having a dry etching rate different from that of silicon nitride. The gate electrode and the first wiring A method of manufacturing a thin film transistor panel, comprising: a step of covering the substrate with a lower insulating film made of silicon oxide and an upper insulating film made of silicon nitride. In the invention of claim 25,
Connecting the second wiring on the upper insulating film to the bottom gate electrode of the amorphous silicon thin film transistor, and forming the second wiring simultaneously with the bottom gate electrode by using a metal material different from the metal material. A method of manufacturing a thin film transistor panel. In the invention of claim 25,
Connecting the second wiring to the bottom gate electrode of the amorphous silicon thin film transistor, forming the second wiring with a metal material different from the metal material, and covering the upper wiring with the upper insulating film and the lower insulating film. A method of manufacturing a thin film transistor panel. In the invention of claim 25,
The second wiring is connected to the bottom gate electrode of the amorphous silicon thin film transistor, and on the same layer as the gate electrode of the polysilicon thin film transistor, the same metal material as the gate electrode is formed simultaneously with the formation of the gate electrode A method of manufacturing a thin film transistor panel, characterized by comprising: In the invention according to any one of claims 25 to 28,
The plurality of contact holes formed in at least one of the lower insulating film made of silicon oxide and the upper insulating film made of silicon nitride are simultaneously formed by dry etching using a parallel plate RIE apparatus. A method of manufacturing a thin film transistor panel. In the invention of claim 29,
A method of manufacturing a thin film transistor panel, wherein the plurality of contact holes formed in a lower insulating film made of silicon oxide are simultaneously formed by wet etching.

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