JP2006054398A - Resistor - Google Patents

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JP2006054398A
JP2006054398A JP2004236705A JP2004236705A JP2006054398A JP 2006054398 A JP2006054398 A JP 2006054398A JP 2004236705 A JP2004236705 A JP 2004236705A JP 2004236705 A JP2004236705 A JP 2004236705A JP 2006054398 A JP2006054398 A JP 2006054398A
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resistor
resistance value
electrode
electrodes
resistors
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Kazuyuki Fukuda
一幸 福田
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Aoi Electronics Co Ltd
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Aoi Electronics Co Ltd
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<P>PROBLEM TO BE SOLVED: To provide a resistor in which a very low resistance value is realized on an insulating substrate. <P>SOLUTION: Surface resistance objects 8a and 8b are electrically connected between electrodes 4 and 5, and 6 and 7, respectively, formed on front and rear surfaces of a ceramic substrate 1b, while facing each other. The electrode 4 provided on the front surface and the electrode 6, provided on the rear surface, are connected together with the use of a side electrode 12a. The electrode 5 formed on the front surface and the electrode 7 formed on the rear surface are connected together with the use of a side electrode 12b. The resistance object 8a on the front surface and the resistance object 8b on the rear surface are connected in parallel. With the view to limiting in the development of a material having extremely low resistance value, the very low resistance value which should be essentially demonstrated is cut by half without a specific material, and the resistor having high power ruggedness is obtained. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、低抵抗値のチップ抵抗器、ジャンパー抵抗器等の低抵抗値抵抗器に関する。   The present invention relates to low resistance resistors such as low resistance chip resistors and jumper resistors.

従来の一般的なチップ抵抗器を図4、図5、図6−A及び図6−Bを参照しながら説明する。
図4に示すような予め分割ライン2、3を縦横に施した大判のセラミック基板1等の絶縁基板において、図6−A、図6−Bに示すように分割ライン2、3で小片1aに区画された長手方向の両縁部表面及び裏面に対向する表面電極4、5、裏面電極6、7を構成する導体膜を銀又は銀系の導体ペーストを印刷・乾燥・焼成して形成する。
さらに前記電極4及び5の内側一領域の表面に重なり、ルテニウムを主成分とする抵抗体ペーストを印刷・焼成して抵抗体8をそれぞれ小片1a毎に独立して形成する。
A conventional general chip resistor will be described with reference to FIGS. 4, 5, 6 -A and 6 -B.
In an insulating substrate such as a large-sized ceramic substrate 1 in which the dividing lines 2 and 3 are provided in advance in the vertical and horizontal directions as shown in FIG. 4, the dividing lines 2 and 3 form small pieces 1a as shown in FIGS. 6A and 6B. The conductor films constituting the surface electrodes 4, 5 and the back electrodes 6, 7 facing both the front and back surfaces of the partitioned longitudinal edges are formed by printing, drying, and firing silver or a silver-based conductor paste.
Further, a resistor paste mainly composed of ruthenium is printed and fired on the surface of the inner region of the electrodes 4 and 5 to form the resistors 8 independently for each piece 1a.

その後、図5及び図6−Aに示すように、前記抵抗体8上に絶縁性保護膜、例えばガラス膜9を形成した後、レーザートリミングを施して予定の抵抗値に仕上げ、さらに前記トリミングにより生じたトリミング溝10部分を覆うように保護膜11、例えばガラス膜又は樹脂層を形成し、該保護膜11の表面に抵抗値を示す標印(図示せず)が施される。   Thereafter, as shown in FIGS. 5 and 6-A, after forming an insulating protective film, for example, a glass film 9 on the resistor 8, laser trimming is performed to finish to a predetermined resistance value, and further by the trimming. A protective film 11, for example, a glass film or a resin layer is formed so as to cover the generated trimming groove 10, and a mark (not shown) indicating a resistance value is applied to the surface of the protective film 11.

しかる後、前記セラミック基板1を分割ライン2(図4)に沿って短冊状に分割してその短冊の長手方向に配置されている破断面をNi−Cr材などによるスパッター法や導体ペーストを用いてディップ法で側面電極12を形成する。これによって前記電極4と電極6、前記電極5と電極7がそれぞれ電気的に接続される。その後、分割ライン3に沿って最小単位の小片(チップ)に分割され、ニッケルメッキ13、はんだメッキ14等の外装メッキが施されて図5に示すようなチップ抵抗器15を得る(特許文献1、特許文献2、特許文献3参照)。   Thereafter, the ceramic substrate 1 is divided into strips along the dividing line 2 (FIG. 4), and the fracture surface arranged in the longitudinal direction of the strips is sputtered by Ni—Cr material or the like using a conductor paste. The side electrode 12 is formed by dipping. Thereby, the electrode 4 and the electrode 6 and the electrode 5 and the electrode 7 are electrically connected to each other. Then, it is divided into small pieces (chips) of the smallest unit along the dividing line 3, and exterior plating such as nickel plating 13 and solder plating 14 is applied to obtain a chip resistor 15 as shown in FIG. , Patent Document 2 and Patent Document 3).

特開昭60−27104号公報JP-A-60-27104 特開平4−144203号公報JP-A-4-144203 特開2003−332101号公報JP 2003-332101 A

ジャンパー抵抗器の場合は前記抵抗体8の代わりに、セラミック基板1の表面に電極4及び電極5を形成する際、これら電極を構成する導体層を延長し一体として形成し、トリミング加工を除き前記チップ抵抗器と類似の製造方法が採用される。   In the case of a jumper resistor, instead of the resistor 8, when the electrodes 4 and 5 are formed on the surface of the ceramic substrate 1, the conductor layers constituting these electrodes are extended and formed integrally, except for the trimming process. A manufacturing method similar to a chip resistor is employed.

ハンディーターミナルやモバイルの更なる小型化に対応するには通信機器分野におけるチップ抵抗器、チップネットワーク抵抗器等も同様に小型化が指向され、短辺方向の長さ(製品幅)が0.3mmの「0603」チップ抵抗器が認知されつつ、短辺方向の長さ0.2mmの「0402」のチップ抵抗器が市場に出回りかけようとしている。   In order to cope with further miniaturization of handy terminals and mobile devices, chip resistors and chip network resistors in the field of communication equipment are similarly aimed at miniaturization, and the length (product width) in the short side direction is 0.3 mm. “0603” chip resistors are being recognized, and “0402” chip resistors having a length of 0.2 mm in the short side direction are about to enter the market.

一方、従来技術によれば、絶縁基板面の一領域にしか機能要素である抵抗体や導体配線が形成できないことより出現可能な抵抗値の下限値は以下のような制約を受けざるを得ない。
抵抗ペーストや導体ペーストのシート抵抗値ρと導体層間に形成される抵抗体の有効長さ(L)と抵抗体の幅(W)と抵抗体の膜厚(t)よる絶縁基板表面での抵抗値Rは、
R=ρ*L/(W*t)の関係にあり、何れの値も有限値であるから出現可能な抵抗値の下限値には第1の課題として数値の壁が存在する。
On the other hand, according to the prior art, the lower limit value of the resistance value that can appear due to the fact that the resistor and conductor wiring, which are functional elements, can only be formed in one region of the insulating substrate surface is subject to the following restrictions. .
Resistance on the surface of the insulating substrate according to the sheet resistance value ρ of the resistor paste or conductor paste, the effective length (L) of the resistor formed between the conductor layers, the width (W) of the resistor, and the film thickness (t) of the resistor The value R is
Since there is a relationship of R = ρ * L / (W * t) and each value is a finite value, there is a numerical wall as a first problem in the lower limit value of the resistance value that can appear.

また、小型化につれて前記小片1aの表面積が減少し、それに比例して抵抗体を形成できる領域の表面積も縮小され、形成できる抵抗体の体積も減少するため、耐久電力は小型化につれて低下するという耐電力性の低下が第2の課題として存在する。   In addition, the surface area of the small piece 1a is reduced as the size is reduced, and the surface area of the region in which the resistor can be formed is reduced in proportion thereto, and the volume of the resistor that can be formed is also reduced. A decrease in power durability exists as a second problem.

製品のサイズとその耐久電力の関係を表1に示す。表1から明らかなように、製品の小型化によって最大耐久電力の値が低下するものの、例えば電源回りの回路構成において電力に対する高耐久な製品の要請は今後とも存在しうるものであるから、前記第2の課題の解決に極めて大きな意義がある。   Table 1 shows the relationship between the product size and its durability power. As apparent from Table 1, although the value of the maximum durable power is reduced by downsizing the product, for example, there is a demand for a highly durable product for power in the circuit configuration around the power source. The resolution of the second problem is extremely significant.

Figure 2006054398
Figure 2006054398

前記表1に示す数値に対する第1の課題は製品開発の進歩により発展を遂げ、極めて低い抵抗値や従来の製品の大きさの限界を越えた耐電力特性等の様々な性能の向上を生み出す可能性を秘めている。本発明は前記周辺技術の進歩を待たずとも達成でき、且つ周辺技術の進歩の恩恵も、その効果を倍加した機能として発揮しうる極低抵抗値を実現できるチップ抵抗器、ジャンパー抵抗器を提案するものである。   The first challenge for the numerical values shown in Table 1 has evolved with the progress of product development, and it is possible to generate various performance improvements such as extremely low resistance values and power handling characteristics that exceed the limits of the size of conventional products. It has sex. The present invention proposes a chip resistor and a jumper resistor that can be achieved without waiting for the advancement of the peripheral technology, and that can realize an extremely low resistance value that can exhibit the benefits of the advancement of the peripheral technology as a function that doubles the effect. To do.

本発明の抵抗器は、絶縁基板の表面及び裏面に対向して形成された電極間にそれぞれ抵抗体を接続し、前記表面に形成された電極と前記裏面に形成された電極を介して前記抵抗体を並列接続してなる。
また、本発明のジャンパー抵抗器は、絶縁基板の表面及び裏面に対向して形成された電極間にそれぞれ導電体を接続し、前記表面に形成された電極と前記裏面に形成された電極を介して前記導電体を並列接続してなる。
The resistor of the present invention is configured such that a resistor is connected between electrodes formed to face the front and back surfaces of an insulating substrate, and the resistor is connected via the electrode formed on the front surface and the electrode formed on the back surface. The body is connected in parallel.
Further, the jumper resistor of the present invention connects a conductor between the electrodes formed opposite to the front and back surfaces of the insulating substrate, respectively, via the electrode formed on the front surface and the electrode formed on the back surface. The conductors are connected in parallel.

前記抵抗器は、銀又は銀とパラジウムを適量混合してなる電極を構成する導体層を絶縁基板の表面の対向する両端面部に印刷・焼成して設け、前記電極間に前記電極上に重なるようにルテニウムを主材とする表面の抵抗体を印刷・焼成して設ける。
さらに抵抗器は、銀又は銀とパラジウムを適量混合してなる電極を構成する導体層を絶縁基板の裏面の対向する両端面部に印刷・焼成して設け、前記電極間に前記電極に重なるようににルテニウムを主材とする裏面の抵抗体を印刷・焼成して設ける。
The resistor is formed by printing and firing conductor layers constituting an electrode formed by mixing silver or silver and palladium in an appropriate amount on opposite end surfaces of the surface of the insulating substrate, and overlapping the electrodes between the electrodes. The surface resistor, the main material of which is ruthenium, is printed and fired.
Further, the resistor is provided by printing and firing a conductive layer that constitutes an electrode formed by mixing silver or silver and palladium in an appropriate amount on opposite end surface portions of the back surface of the insulating substrate so that the electrode overlaps between the electrodes. A resistor on the back surface mainly composed of ruthenium is printed and fired.

ジャンパー抵抗器は前記表面の電極及び前記裏面の電極間にこれら電極から延長してなる銀又は銀とパラジウムを適量混合してなる一体の導体配線層を印刷・焼成して設ける。   The jumper resistor is provided by printing and baking an integral conductor wiring layer formed by mixing silver or silver and palladium in an appropriate amount between the electrodes on the front surface and the electrodes on the back surface.

前記抵抗体又は導体配線層は外装電極の引き出しを除き相互に重ならないようにすることで従来では一個の製品にひとつのの機能要素が搭載されていたが、本発明では一個の製品に2つの機能要素を搭載して並列接続することで個別に形成しうる限界の低抵抗の並列回路を構成して極低抵抗値のチップ抵抗器、ジャンパー抵抗器を構成することが可能となる。   Conventionally, one functional element is mounted on one product by preventing the resistor or conductor wiring layer from overlapping each other except for the lead-out of the outer electrode. In the present invention, two functional elements are mounted on one product. By mounting functional elements and connecting them in parallel, it becomes possible to configure a chip resistor and a jumper resistor with extremely low resistance values by configuring a parallel circuit with a low resistance that can be individually formed.

絶縁基板の表面に形成した表面の抵抗体の抵抗値をRa、絶縁基板の裏面に形成した裏面の抵抗体の抵抗値をRbとすると、これら抵抗体の実際の抵抗値を同じ抵抗値rとすると、並列接続した合成抵抗値Ra*Rb/(Ra+Rb)=r/2となる。ここで抵抗値rを設計選択可能な極限の低抵抗値とすると、抵抗値の低下を更に倍増することができる。   When the resistance value of the front surface resistor formed on the surface of the insulating substrate is Ra and the resistance value of the back surface resistor formed on the back surface of the insulating substrate is Rb, the actual resistance value of these resistors is the same resistance value r. Then, the combined resistance value Ra * Rb / (Ra + Rb) = r / 2 connected in parallel is obtained. Here, if the resistance value r is an extremely low resistance value that can be selected by design, the decrease in the resistance value can be further doubled.

一方、電力特性は、絶縁基板の表裏に形成されている前記二つの抵抗体は並列接続であるから、全体として個々の抵抗体が持つ注入可能な電流の2倍の電流を流し込むことが可能となり、結果として2倍の耐電力特性を持つこととなり、前記第2の課題の解決が図られ、更にこうした効果は表裏の抵抗値が略同等であることにより、表裏の抵抗値の不均衡がないので片側に電流密度が集中することがなく偏らず、製品として精度、信頼度の高い抵抗器を実現することができる。また、ジャンパー抵抗器についても同等の特性を得ることができる。   On the other hand, as for the power characteristics, since the two resistors formed on the front and back of the insulating substrate are connected in parallel, it is possible to inject a current twice as large as the current that each resistor can inject. As a result, it has twice the power durability characteristics, and the second problem can be solved. Further, since the resistance values on the front and back sides are substantially equal, there is no imbalance between the resistance values on the front and back sides. Therefore, the current density does not concentrate on one side and it is not biased, and a resistor with high accuracy and reliability can be realized as a product. Moreover, the same characteristic can be obtained also about a jumper resistor.

以下、前記並列接続するという技術的思想に基づく本発明の実施の形態を図1、図2−A、図2−B及び図4を参照しながら説明する。
図4に示すような予め分割ライン2、3を縦横に施した大判のセラミック基板1などの絶縁基板において、図2−A、図2−Bに示すように小片1bに区画された長手方向の両縁部表面及び裏面に表面電極4、5、裏面電極6、7を構成する導体膜を銀又は銀系の導体ペーストを印刷・乾燥・焼成して形成する。
In the following, an embodiment of the present invention based on the technical idea of parallel connection will be described with reference to FIG. 1, FIG. 2-A, FIG. 2-B and FIG.
In an insulating substrate such as a large-sized ceramic substrate 1 in which dividing lines 2 and 3 are previously provided in the vertical and horizontal directions as shown in FIG. 4, the longitudinal direction divided into small pieces 1 b as shown in FIGS. 2A and 2B. The conductive films constituting the surface electrodes 4, 5 and the back electrodes 6, 7 are formed on the front and back surfaces of both edges by printing, drying and baking silver or silver-based conductive paste.

さらに図2−Aに示すように、前記電極4と電極5間にこれら電極の内側一領域の表面に重なり、ルテニウムを主成分とする抵抗体ペーストを印刷・焼成して表面の抵抗体8aをそれぞれ小片1b毎に独立して形成する。
さらに図2−Bに示すように、前記電極6と電極7間にこれら電極の内側一領域の表面に重なり、ルテニウムを主成分とする抵抗体ペーストを印刷・焼成して裏面の抵抗体8bをそれぞれ小片1b毎に独立して形成する。
Further, as shown in FIG. 2A, the resistor 8a on the surface is formed by printing and baking a resistor paste mainly composed of ruthenium between the electrodes 4 and 5 on the surface of an inner region of these electrodes. Each is formed independently for each small piece 1b.
Further, as shown in FIG. 2B, the resistor 8b on the back surface is formed by printing and baking a resistor paste mainly composed of ruthenium between the electrodes 6 and 7 on the surface of one inner region of these electrodes. Each is formed independently for each small piece 1b.

その後、図1及び図2−Aに示すように、前記表面の抵抗体8a上に絶縁性保護膜、例えばガラス膜9aを形成した後、レーザトリミングを施して予定の抵抗値に仕上げ、更に前記トリミングにより生じたトリミング溝10a部分を覆うように保護膜11a、例えばガラス膜又は樹脂層を形成し、該保護膜11aの表面に抵抗値を示す標印(図示せず)が施される。
さらに、図1及び図2−Bに示すように、前記裏面の抵抗体8b上に絶縁性保護膜、例えばガラス膜9bを形成した後、レーザトリミングを施して予定の抵抗値に仕上げ、更に前記トリミングにより生じたトリミング溝10b部分を覆うように保護膜11b、例えばガラス膜又は樹脂層を形成する。
Thereafter, as shown in FIG. 1 and FIG. 2A, after forming an insulating protective film, for example, a glass film 9a on the resistor 8a on the surface, laser trimming is performed to finish to a predetermined resistance value. A protective film 11a, for example, a glass film or a resin layer is formed so as to cover the trimming groove 10a generated by the trimming, and a mark (not shown) indicating a resistance value is applied to the surface of the protective film 11a.
Further, as shown in FIGS. 1 and 2-B, after forming an insulating protective film, for example, a glass film 9b, on the resistor 8b on the back surface, laser trimming is performed to finish to a predetermined resistance value. A protective film 11b, for example, a glass film or a resin layer is formed so as to cover the trimming groove 10b portion generated by the trimming.

しかる後、前記セラミック基板1を分割ライン2(図4)に沿って短冊状に分割してその短冊の長手方向に配置されている破断面をNi−Cr材などによるスパッターや導体ペーストを用いてディップ方式で側面電極12aを形成する。これによって前記電極4と電極6、電極5と電極7の縁部がそれぞれ前記側面電極12aと重なることで電気的に接続される。その後、分割ライン3に沿って最小単位の小片(チップ)に分割されニッケルメッキ13、はんだメッキ14等の外装メッキが施されて図1に示すような本発明のチップ抵抗器15aを得る。   Thereafter, the ceramic substrate 1 is divided into strips along the dividing line 2 (FIG. 4), and the fractured surface arranged in the longitudinal direction of the strips is sputtered by Ni—Cr material or the like using a conductor paste. Side electrode 12a is formed by a dip method. As a result, the edges of the electrodes 4 and 6 and the electrodes 5 and 7 are electrically connected by overlapping the side electrode 12a. Thereafter, it is divided into small pieces (chips) of the smallest unit along the dividing line 3 and subjected to exterior plating such as nickel plating 13 and solder plating 14 to obtain the chip resistor 15a of the present invention as shown in FIG.

ジャンパー抵抗器の場合は前記表面の抵抗体8a、前記裏面の抵抗体8bの代わりに、セラミック基板1の表面に前記電極4及び前記電極5、前記電極6及び電極7を形成する際、これら電極間にこれら電極を構成する導体層を延長し一体として表面に形成し、トリミング加工を除き前記製造方法と類似の製造方法が採用される。   In the case of a jumper resistor, when forming the electrode 4 and the electrode 5, the electrode 6 and the electrode 7 on the surface of the ceramic substrate 1, instead of the front surface resistor 8a and the back surface resistor 8b, these electrodes In the meantime, the conductor layers constituting these electrodes are extended and formed integrally on the surface, and a manufacturing method similar to the above manufacturing method is adopted except for trimming.

前記トリミングの好適な方法について説明する。
前記表面の抵抗体8a及び前記裏面の抵抗体8bの抵抗値は、前記表面電極4と前記裏面電極6とが、前記表面電極5と前記裏面電極7とがそれぞれ前記側面電極12a、12bによって接続され、前記二つの抵抗体が並列接続されることを考慮して、各々独立して形成される前記抵抗体8a、8bの抵抗値をトリミング前に完成品の目標抵抗値の2倍の仮の目標抵抗値を定め、トリミングにより前記抵抗体8aの初期抵抗値を前記仮の目標抵抗値になるまで抵抗値を上昇させ、次に前記抵抗体8bの抵抗値も同様に上昇させる。
A suitable trimming method will be described.
The resistance values of the front surface resistor 8a and the back surface resistor 8b are as follows. The front surface electrode 4 and the back surface electrode 6 are connected to the front surface electrode 5 and the back surface electrode 7 by the side surface electrodes 12a and 12b, respectively. In consideration of the fact that the two resistors are connected in parallel, the resistance values of the resistors 8a and 8b, which are formed independently of each other, are temporarily set to twice the target resistance value of the finished product before trimming. A target resistance value is determined, and the initial resistance value of the resistor 8a is increased by trimming until the temporary target resistance value is reached, and then the resistance value of the resistor 8b is also increased.

ここで、前記抵抗体8aと前記抵抗体8bの抵抗値が略同等の値とするために、トリミング前の初期合成抵抗値をR0、目標合成抵抗値をRとすると、差(R−R0)をトリミングにより縮めるべく、まず前記抵抗体8aの抵抗値が(1/2)*(R−R0)になるまで上昇させ、次に前記抵抗体8bが(1/2)*(R−R0)の抵抗値になるまで上昇させる。これによって前記抵抗体8aと前記抵抗体8bが共に略同程度のトリミングの状態を再現でき、抵抗値が略同等に仕上がる。   Here, in order to make the resistance values of the resistor 8a and the resistor 8b substantially equal, assuming that the initial combined resistance value before trimming is R0 and the target combined resistance value is R, the difference (R−R0) First, the resistance value of the resistor 8a is increased to (1/2) * (R-R0), and then the resistor 8b is (1/2) * (R-R0). Increase until the resistance value becomes. As a result, both the resistor 8a and the resistor 8b can reproduce substantially the same trimming state, and the resistance values are almost equal.

前記トリミングの例を数値を用いて具体的に説明する。
例えばチップ抵抗器の完成品の抵抗値を1Ωとすると、前記抵抗体8a、前記抵抗体8bの抵抗値を同等の値とすることで抵抗体が並列接続されるので完成品の抵抗値は前記抵抗体8a、前記抵抗体8bの抵抗値の略1/2となることを想定し、トリミング時点にて各抵抗体の抵抗値は完成品の抵抗値の2倍に設定した仮の目標抵抗値2Ωを定める。
ここでトリミングによる抵抗値の上昇率を1.2倍に設定すると、トリミング前の抵抗値2Ω÷1.2≒1.67Ωの抵抗体を作り込む。
An example of the trimming will be specifically described using numerical values.
For example, if the resistance value of the finished chip resistor is 1Ω, the resistance values of the resistor 8a and the resistor 8b are set to the same value so that the resistors are connected in parallel. Assuming that the resistance value of the resistor 8a and the resistor 8b is approximately ½, the resistance value of each resistor is set to twice the resistance value of the finished product at the time of trimming. Set 2Ω.
Here, if the rate of increase in resistance value due to trimming is set to 1.2 times, a resistor having a resistance value 2Ω ÷ 1.2≈1.67Ω before trimming is formed.

その後、レーザトリミングにより前記抵抗体8aの初期抵抗値1.67Ωを前記仮の目標抵抗値2Ωになるまで抵抗値を上昇させる。次に、レーザトリミングにより前記抵抗体8bの初期抵抗値1.67Ωを前記仮の目標抵抗値2Ωになるまで抵抗値を上昇させる。このように前記ふたつの抵抗体の抵抗値をレーザトリミングにより調整することで、前記二つの抵抗体は共に同等の目標抵抗値2Ωが作り込まれ、また両抵抗体は同等のトリミング痕跡10a、10b(トリミング長さ)を有することとなり、図3に示すように抵抗体の未トリミングとなる残幅16が共に略同程度確保されることとなり、完成品の表裏の抵抗体の抵抗値が同等になることで両抵抗体の合成抵抗1Ωとなるように表裏夫々のユニット間で偏りなく仕上げることができる。なお、図3では抵抗体上に設けられるガラス膜の図示は省略している。   Thereafter, the resistance value is increased by laser trimming until the initial resistance value of 1.67Ω of the resistor 8a becomes the temporary target resistance value of 2Ω. Next, the resistance value is increased by laser trimming until the initial resistance value of 1.67Ω of the resistor 8b becomes the temporary target resistance value of 2Ω. Thus, by adjusting the resistance values of the two resistors by laser trimming, the two resistors have the same target resistance value of 2Ω, and both resistors have the same trimming traces 10a, 10b. As shown in FIG. 3, both of the remaining widths 16 that are not trimmed of the resistors are secured to approximately the same level, and the resistance values of the resistors on the front and back of the finished product are equal. As a result, it is possible to finish without unevenness between the front and back units so that the combined resistance of both resistors is 1Ω. In FIG. 3, the illustration of the glass film provided on the resistor is omitted.

かくして、前記抵抗体8a、8bが並列接続されると、前記仮の目標抵抗値2Ωから完成品の抵抗値は1/2の1Ωに置き換わる。
つまり、製品としての各々のチップ抵抗器の一対の側面電極を端子として2つの抵抗体を見ると、一対の側面電極間で2つの抵抗体による並列回路が形成される。
Thus, when the resistors 8a and 8b are connected in parallel, the resistance value of the finished product is replaced by 1Ω, which is 1/2, from the temporary target resistance value 2Ω.
That is, when the two resistors are viewed using the pair of side electrodes of each chip resistor as a product as a terminal, a parallel circuit including the two resistors is formed between the pair of side electrodes.

ジャンパー抵抗器の場合は、前記抵抗体の代わりに、表裏の電極4、5、6及び7を形成する際に、電極となる導体層を延長して導体配線層を形成する。
現在、極抵抗値材料の開発に限界があり、本発明の抵抗器やジャンパー抵抗部品は従来の製造プロセスの範囲で実施可能であり且つ特別の材料を必要とすることなく従来の材料で本来発揮すべき極低抵抗の値をさらに半減でき、電力耐久性に対しても同製品サイズの略2倍の特性を有し、これによって軽薄短小の性質を壊さず、かつワンサイズ小型の外形でありながら極めて低い抵抗値と高い電力耐久性を有するチップ部品を提供することができる。
In the case of a jumper resistor, instead of the resistor, when forming the front and back electrodes 4, 5, 6 and 7, the conductor layer serving as an electrode is extended to form a conductor wiring layer.
Currently, there is a limit to the development of extreme resistance materials, and the resistors and jumper resistance components of the present invention can be implemented within the range of conventional manufacturing processes, and are inherently demonstrated in conventional materials without the need for special materials. The value of the extremely low resistance to be reduced can be further halved, and it has approximately twice the size of the product with respect to power durability. However, a chip component having an extremely low resistance value and high power durability can be provided.

前記本発明の抵抗器の一例として、抵抗体が厚膜印刷法で具現化される厚膜型チップ抵抗器の例で示したが、本発明の技術思想に基づく抵抗器は、抵抗体をNiCrやTa系の薄膜抵抗体で形成した薄膜型抵抗器にも転用することができる。   As an example of the resistor of the present invention, a thick film chip resistor in which the resistor is embodied by a thick film printing method is shown. However, the resistor based on the technical idea of the present invention is a NiCr resistor. It can also be diverted to a thin film resistor formed of a Ta-based thin film resistor.

本発明抵抗器の断面図である。It is sectional drawing of this invention resistor. 本発明抵抗器の表面の要部平面図である。It is a principal part top view of the surface of this invention resistor. 本発明抵抗器の裏面の要部平面図である。It is a principal part top view of the back surface of this invention resistor. 本発明抵抗器の抵抗体のトリミング状態を説明する要部平面図である。It is a principal part top view explaining the trimming state of the resistor of this invention resistor. 本発明抵抗器及び従来の抵抗器の製造に供する大判セラミック基板の平面図である。It is a top view of the large format ceramic substrate with which it uses for manufacture of this invention resistor and the conventional resistor. 従来の抵抗器の断面図である。It is sectional drawing of the conventional resistor. 従来の抵抗器の表面の要部平面図である。It is a principal part top view of the surface of the conventional resistor. 従来の抵抗器の裏面の要部平面図である。It is a principal part top view of the back surface of the conventional resistor.

符号の説明Explanation of symbols

4、5・・表面電極 6、7・・裏面電極 8a・・表面の抵抗体 8b・・裏面の抵抗体 12a、12b・・表面の抵抗体と裏面の抵抗体を並列接続する側面電極 4, 5 .. Front electrode 6, 7, .. Back electrode 8a .. Front resistor 8b .. Back resistor 12a, 12b .. Side electrode for connecting front resistor and back resistor in parallel

Claims (5)

絶縁基板の表面及び裏面にそれぞれ形成した抵抗体を並列接続してなることを特徴とする抵抗器。   A resistor comprising resistors formed on the front and back surfaces of an insulating substrate, respectively, connected in parallel. 絶縁基板の表面及び裏面に対向して形成された電極間にそれぞれ抵抗体を接続し、前記表面に形成された電極と前記裏面に形成された電極を介して前記抵抗体を並列接続したことを特徴とする抵抗器。   A resistor is connected between the electrodes formed opposite to the front and back surfaces of the insulating substrate, and the resistors are connected in parallel via the electrode formed on the front surface and the electrode formed on the back surface. Feature resistor. 前記絶縁基板の表面及び裏面に形成された抵抗体の抵抗値を略等しくトリミングしてなる
ことを特徴とする請求項1又は2の抵抗器。
3. The resistor according to claim 1, wherein the resistance values of the resistors formed on the front surface and the back surface of the insulating substrate are trimmed approximately equally.
絶縁基板の表面及び裏面にそれぞれ形成した導電体を並列接続してなることを特徴とするジャンパー抵抗器。   A jumper resistor comprising conductors respectively formed on the front and back surfaces of an insulating substrate connected in parallel. 絶縁基板の表面及び裏面に対向して形成された電極間にそれぞれ導電体を接続し、前記表面に形成された電極と前記裏面に形成された電極を介して前記導電体を並列接続したことを特徴とするジャンパー抵抗器。   Conductors are connected between the electrodes formed facing the front and back surfaces of the insulating substrate, respectively, and the conductors are connected in parallel via the electrodes formed on the front surface and the electrodes formed on the back surface. Characteristic jumper resistor.
JP2004236705A 2004-08-16 2004-08-16 Resistor Pending JP2006054398A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101058606B1 (en) 2009-09-04 2011-08-22 삼성전기주식회사 Array Type Chip Resistor
US8179226B2 (en) 2009-09-04 2012-05-15 Samsung Electro-Mechanics Co., Ltd. Array type chip resistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101058606B1 (en) 2009-09-04 2011-08-22 삼성전기주식회사 Array Type Chip Resistor
US8179226B2 (en) 2009-09-04 2012-05-15 Samsung Electro-Mechanics Co., Ltd. Array type chip resistor

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