WO2020009051A1 - Network chip resistor - Google Patents

Network chip resistor Download PDF

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Publication number
WO2020009051A1
WO2020009051A1 PCT/JP2019/026034 JP2019026034W WO2020009051A1 WO 2020009051 A1 WO2020009051 A1 WO 2020009051A1 JP 2019026034 W JP2019026034 W JP 2019026034W WO 2020009051 A1 WO2020009051 A1 WO 2020009051A1
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Prior art keywords
pair
electrodes
electrode
insulating substrate
film
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PCT/JP2019/026034
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French (fr)
Japanese (ja)
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野村　豊
淳一 沢井
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北陸電気工業株式会社
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Priority to JP2020528846A priority Critical patent/JPWO2020009051A1/en
Publication of WO2020009051A1 publication Critical patent/WO2020009051A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/142—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals or tapping points being coated on the resistive element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material

Definitions

  • the present invention relates to a network chip resistor that can constitute a voltage dividing circuit with one chip.
  • JP-A-10-208901 Patent Document 1
  • JP-A-2018-6726 Patent Document 2
  • JP-A-64-37002 Patent Document 3
  • a network chip resistor that forms a voltage dividing circuit by forming a film-shaped resistor across the voltage dividing circuit electrode on the surface of an insulating substrate is disclosed.
  • an end face electrode covering both end faces in the longitudinal direction of the substrate is connected to a pair of terminal electrodes.
  • An object of the present invention is to provide a network chip resistor that does not cause a Manhattan phenomenon at the time of soldering and can form a voltage dividing circuit with one chip.
  • a network chip resistor includes an elongated insulating substrate having a front surface and a rear surface, a pair of terminal electrodes provided at both ends of the front surface of the insulating substrate in a longitudinal direction, and a position in a width direction orthogonal to the longitudinal direction of the insulating substrate.
  • a pair of side electrodes at least provided on a pair of side surfaces to be electrically connected to the pair of terminal electrodes; an intermediate electrode provided between the pair of terminal electrodes on the surface of the insulating substrate;
  • a pair of intermediate side electrodes provided at least on the side surfaces of the pair and electrically connected to the intermediate electrode, a pair of resistors provided between the pair of terminal electrodes and the intermediate electrode, and having plating liquid resistance.
  • a pair of protective layers formed of a material and provided on the pair of resistors.
  • one or more plating layers formed on the pair of terminal electrodes and the two pairs of side electrodes, and the intermediate electrode and the pair of intermediate side electrodes, respectively. It has.
  • each electrode can be formed by printing. Further, when the pair of side electrodes and the pair of intermediate side electrodes are constituted by the pair of thin film side electrodes and the pair of thin film intermediate side surfaces, the formation of each side electrode is facilitated and the size of the resistor is easily reduced.
  • the semiconductor device further includes an intermediate extension electrode extending from the intermediate side surface electrode and extending on the back surface of the insulating substrate.
  • the back surface of the insulating substrate is formed of a material having plating solution resistance, and is formed at least at the center of the intermediate extension electrode.
  • a backside protective layer extending in the longitudinal direction of the insulating substrate may be provided so as to cover the portion. When such a configuration is employed, one or more plating layers are likely to adhere.
  • the continuous portion of the intermediate side surface electrode and the intermediate extension electrode exists at the corner of the insulating substrate corresponding to the intermediate electrode, it is possible to prevent the adhered plating layer from peeling off from the portion corresponding to the corner of the corresponding insulating substrate. If the intermediate extension electrode is constituted by the thick film intermediate extension electrode, the formation of the intermediate extension electrode becomes easy.
  • FIG. 2 is a cross-sectional view taken along the line II-II of FIG. (A) is a sectional view taken along the line IIIA-IIIA of FIG. 1 (B), and (B) is a sectional view taken along the line IIIB-IIIB of FIG. 1 (B).
  • FIGS. 1A to 1C are a front view, a bottom view, and a plan view of a network chip resistor according to the present embodiment
  • FIG. 2 is a cross-sectional view taken along line II-II of FIG. 3 (A) is a sectional view taken along the line IIIA-IIIA of FIG. 1 (B)
  • FIG. 3 (B) is a sectional view taken along the line IIIB-IIIB of FIG. 1 (B).
  • hatching indicating a cross section is omitted.
  • the network chip resistor of the present embodiment is mounted in the reverse direction so that the resistor faces the mounting circuit board, the network chip resistor is insulated in FIGS. 1 (A), 2 and 3 (A) (B).
  • the display is such that the surface of the substrate faces downward.
  • reference numeral 1 denotes an insulating substrate having a front surface 1A and a back surface 1B formed in a ceramic elongated rectangular shape.
  • a pair of thick film terminal electrodes 2 and 2 corresponding to a pair of terminal electrodes are provided on the surface 1A of the insulating substrate 1, and a thickness corresponding to an intermediate electrode is provided between the pair of thick film terminal electrodes 2 and 2.
  • a membrane intermediate electrode 3 is provided.
  • the thick-film terminal electrodes 2 and 2 and the thick-film intermediate electrode 3 are each formed by firing an electrode pattern formed by screen printing using a conductive paste containing silver and palladium.
  • a pair of resistors R1 and R2 are provided between the pair of thick-film terminal electrodes 2 and 2 and the thick-film intermediate electrode 3.
  • the resistors R1 and R2 are formed by firing a printing pattern screen-printed on the surface of the insulating substrate 1 using a resistance paste containing ruthenium oxide as a material.
  • the resistance values of the resistors R1 and R2 are the same.
  • FIG. 4 is an equivalent circuit of the network chip resistor of this embodiment including the resistors R1 and R2.
  • the insulating substrate 1 is provided on a pair of side surfaces 1C and 1D located in a width direction orthogonal to the longitudinal direction of the insulating substrate 1, and is electrically connected to the pair of thick film terminal electrodes 2 and 2 sets. It has a pair of thin film side electrodes 4, 4, 5 and 5 corresponding to a pair of side electrodes [see FIG. 3 (A)]. Further, on the pair of side surfaces 1C and 1D, a pair of thin film intermediate side electrodes 6, 6 corresponding to a pair of intermediate side electrodes electrically connected to the thick film intermediate electrode 3 are formed [FIG. )reference].
  • the thin film side electrodes 4, 4 and 5, 5 and the pair of thin film intermediate side electrodes 6, 6 are each formed by sputtering, and in this embodiment, are formed of a material such as titanium, nickel, aluminum, copper, or the like. Have been.
  • the protective layer 7 includes a first protective layer 7A made of a glass material and a second protective layer 7B made of an epoxy material.
  • the plating layer 8 is composed of a first plating layer 8A made of nickel (Ni) and a second plating layer 8B made of tin (Sn).
  • the plating layer 8 is formed by barrel plating.
  • the thick film intermediate extension electrode 9 corresponding to the intermediate extension electrode extending on the back surface 1B of the insulating substrate 1 is connected to the pair of thin film intermediate side electrodes 6 and 6 so as to be continuous. Have more.
  • This thick film intermediate extension electrode 9 is also formed by firing an electrode pattern formed by screen printing with a conductive paste containing silver and palladium.
  • the back surface 1B of the insulating substrate 1 is made of an epoxy resin or the like which is formed of a material having plating liquid resistance and extends in the longitudinal direction of the insulating substrate 1 so as to cover at least the central portion of the thick film intermediate extension electrode 9.
  • a backside protective layer 10 is provided.
  • the thick film intermediate extension electrode 9 is provided in this manner, one or more plating layers 8 are easily attached.
  • the adhered plating layer 8 is peeled off from the corresponding portions of the insulating substrate 1. Can be prevented.
  • the backside protective layer 10 constitutes a suction surface of the suction nozzle to prevent wear of the tip surface of the suction nozzle.
  • the network chip resistor according to the present embodiment includes a pair of thick film terminal electrodes 2 and 2, resistors R 1 and R 2 bridging between both thick film terminal electrodes 2 and 2, and a resistor R 1
  • a voltage dividing circuit can be constituted by one chip.
  • the mounting area is reduced, and the electronic component can be further downsized.
  • soldering and the like can be reduced, and the efficiency of the mounting operation can be increased.
  • the thick-film intermediate extension electrode 9 is provided.
  • the thick-film intermediate extension electrode 9 may not be provided, or may be cut in the middle.
  • the thick film intermediate extension electrode 9 may of course be covered with a thin film electrode.
  • the surface 1A of the insulating substrate 1 faces the circuit board, and two pairs of thin film side electrodes 4, 4 and Solder is applied via the plating layer 8 on the thick-film terminal electrodes 2 and 2 and the thick-film intermediate electrode 3 so that a solder fillet is formed halfway between the thin-film intermediate electrodes 5 and 5 and the pair of thin-film intermediate side electrodes 6 and 6.
  • a solder fillet is formed halfway between the thin-film intermediate electrodes 5 and 5 and the pair of thin-film intermediate side electrodes 6 and 6.
  • the resistance values of the resistors R1 and R2 are 10 ohms to 1 megohm.
  • the ceramic substrate is used as the insulating substrate 1, but it goes without saying that another insulating substrate may be used.
  • the thin film side electrodes 4, 4, and 5, and the pair of thin film intermediate side electrodes 6, 6 are formed by sputtering, but they may be formed by other thin film forming techniques such as vapor deposition. Of course.
  • the pair of terminal electrodes and the intermediate electrode are constituted by the pair of thick-film terminal electrodes and the thick-film intermediate electrode.
  • these electrodes may be formed by thin-film electrodes.
  • the pair of side electrodes and the pair of intermediate side electrodes are constituted by the pair of thin film side electrodes and the pair of thin film intermediate side electrodes, but these electrodes may be formed by thick films.
  • the intermediate extension electrode is formed of a thick film, but this electrode may of course be formed of a thin film.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Non-Adjustable Resistors (AREA)
  • Details Of Resistors (AREA)

Abstract

Provided is a network chip resistor in which the Manhattan phenomenon does not occur during soldering and a voltage dividing circuit can be configured with a single chip. A pair of thick-film terminal electrodes 2, 2 are provided on a surface 1A of an insulation substrate 1, and a thick-film intermediate electrode 3 is provided between the pair of thick-film terminal electrodes 2, 2. One or more plating layers 8 are provided on the pair of thick-film terminal electrodes 2, 2 and two sets of thin-film side electrodes 4, 4 and 5, 5, and on the thick-film intermediate electrode 3 and a pair of thin-film intermediate side electrodes 6, 6. Thin-film intermediate extension electrodes 9 are further provided which extend from the pair of thin-film intermediate side electrodes 6, 6 and which extend on a rear surface 1B of the insulation substrate 1.

Description

ネットワークチップ抵抗器Network chip resistors
　本発明は、ワンチップで分圧回路を構成することができるネットワークチップ抵抗器に関するものである。 The present invention relates to a network chip resistor that can constitute a voltage dividing circuit with one chip.
　特開平１０－２０８９０１号公報（特許文献１）、特開２０１８－６７２６号公報（特許文献２）、実開昭６４－３７００２号公報（特許文献３）等には、絶縁基板の表面及び裏面の対向する両端部に一対の端子電極を形成し、その一対の端子電極間に分圧回路用電極をそれぞれ分離形成した後、絶縁基板の表面の対向する一対の端子電極間を橋絡し、かつ、絶縁基板の表面の分圧回路用電極を横断するように膜状抵抗体を形成して分圧回路を構成するネットワークチップ抵抗器が開示されている。これらのチップ抵抗器では、いずれも一対の端子電極に対して基板の長手方向の両端面を覆う端面電極を接続している。 JP-A-10-208901 (Patent Document 1), JP-A-2018-6726 (Patent Document 2), and JP-A-64-37002 (Patent Document 3) disclose the front and rear surfaces of an insulating substrate. After forming a pair of terminal electrodes at opposite ends, and separately forming a voltage dividing circuit electrode between the pair of terminal electrodes, bridging between the pair of terminal electrodes facing each other on the surface of the insulating substrate, and A network chip resistor that forms a voltage dividing circuit by forming a film-shaped resistor across the voltage dividing circuit electrode on the surface of an insulating substrate is disclosed. In each of these chip resistors, an end face electrode covering both end faces in the longitudinal direction of the substrate is connected to a pair of terminal electrodes.
特開平１０－２０８９０１号公報JP-A-10-208901 特開２０１８－６７２６号公報JP 2018-6726A 実開昭６４－３７００２号公報Japanese Utility Model Publication No. 64-37002
　絶縁基板の長さが長くなればなるほど、絶縁基板の長手方向の両端に端面電極を設けた場合には、半田が硬化する際にチップ抵抗器が立ち上がる、いわゆるマンハッタン現象が発生する可能性が高くなる。 The longer the length of the insulating substrate, the more likely it is that the so-called Manhattan phenomenon will occur when the end resistors are provided at both ends in the longitudinal direction of the insulating substrate, when the solder hardens, the chip resistor rises. Become.
　本発明の目的は、半田付けの際にマンハッタン現象が起こらない、ワンチップで分圧回路を構成することができるネットワークチップ抵抗器を提供することにある。 An object of the present invention is to provide a network chip resistor that does not cause a Manhattan phenomenon at the time of soldering and can form a voltage dividing circuit with one chip.
　本発明のネットワークチップ抵抗器は、表面と裏面を有する細長い絶縁基板と、絶縁基板の表面の長手方向の両端に設けられた一対の端子電極と、絶縁基板の長手方向と直交する幅方向に位置する一対の側面上に少なくとも設けられ、一対の端子電極と電気的に接続された２組の一対の側面電極と、絶縁基板の表面の一対の端子電極の間に設けられた中間電極と、一対の側面上に少なくとも設けられ、中間電極と電気的に接続された一対の中間側面電極と、一対の端子電極と中間電極との間に設けられた一対の抵抗体と、耐メッキ液性を有する材料により形成されて、一対の抵抗体の上に設けられた一対の保護層とを有している。本発明のネットワークチップ抵抗器においては、特に、一対の端子電極及び２組の一対の側面電極の上と、中間電極及び一対の中間側面電極の上にそれぞれ形成された１層以上のメッキ層とを備えている。 A network chip resistor according to the present invention includes an elongated insulating substrate having a front surface and a rear surface, a pair of terminal electrodes provided at both ends of the front surface of the insulating substrate in a longitudinal direction, and a position in a width direction orthogonal to the longitudinal direction of the insulating substrate. A pair of side electrodes at least provided on a pair of side surfaces to be electrically connected to the pair of terminal electrodes; an intermediate electrode provided between the pair of terminal electrodes on the surface of the insulating substrate; A pair of intermediate side electrodes provided at least on the side surfaces of the pair and electrically connected to the intermediate electrode, a pair of resistors provided between the pair of terminal electrodes and the intermediate electrode, and having plating liquid resistance. And a pair of protective layers formed of a material and provided on the pair of resistors. In the network chip resistor of the present invention, in particular, one or more plating layers formed on the pair of terminal electrodes and the two pairs of side electrodes, and the intermediate electrode and the pair of intermediate side electrodes, respectively. It has.
　本発明のように、２組の一対の側面電極と一対の中間側面電極を設けると、長い絶縁基板の側面が片側３カ所で半田で固定されるため、マンハッタン現象が起こり難くなる。また絶縁基板の長手方向の両端に側面電極がなければ、チップ抵抗器を長手方向が直線状に並ぶように配置しても、隣り合うチップ抵抗器間の間隔を短くすることができ、実装密度を高くすることができる。 (4) When two pairs of side electrodes and a pair of intermediate side electrodes are provided as in the present invention, the side surfaces of the long insulating substrate are fixed by solder at three places on one side, so that the Manhattan phenomenon hardly occurs. Also, if there are no side electrodes at both ends in the longitudinal direction of the insulating substrate, even if the chip resistors are arranged so that the longitudinal direction is linear, the distance between adjacent chip resistors can be shortened, and the mounting density can be reduced. Can be higher.
　一対の端子電極及び中間電極を、一対の厚膜端子電極及び厚膜中間電極により構成すると、印刷により各電極を形成することができる。また一対の側面電極及び一対の中間側面電極を、一対の薄膜側面電極及び一対の薄膜中間側面により構成すると、各側面電極の形成が容易である上、抵抗器の小型化が容易になる。 (4) When the pair of terminal electrodes and the intermediate electrode are composed of the pair of thick-film terminal electrodes and the thick-film intermediate electrode, each electrode can be formed by printing. Further, when the pair of side electrodes and the pair of intermediate side electrodes are constituted by the pair of thin film side electrodes and the pair of thin film intermediate side surfaces, the formation of each side electrode is facilitated and the size of the resistor is easily reduced.
　また中間側面電極から延びて、絶縁基板の裏面上に延びる中間延長電極をさらに有しており、絶縁基板の裏面には、耐メッキ液性を有する材料により形成されて、少なくとも中間延長電極の中央部を覆うようにして絶縁基板の長手方向に延びる裏面側保護層が設けられていてもよい。このような構成を採用すると、１層以上のメッキ層が付着しやすくなる。しかも中間電極に対応する絶縁基板の角部に中間側面電極と中間延長電極の連続部が存在するため、付着したメッキ層が対応する絶縁基板の角部に対応する部分から剥がれるのを防止できる。なお中間延長電極が厚膜中間延長電極により構成されていれば、中間延長電極の形成が容易になる。 Further, the semiconductor device further includes an intermediate extension electrode extending from the intermediate side surface electrode and extending on the back surface of the insulating substrate. The back surface of the insulating substrate is formed of a material having plating solution resistance, and is formed at least at the center of the intermediate extension electrode. A backside protective layer extending in the longitudinal direction of the insulating substrate may be provided so as to cover the portion. When such a configuration is employed, one or more plating layers are likely to adhere. In addition, since the continuous portion of the intermediate side surface electrode and the intermediate extension electrode exists at the corner of the insulating substrate corresponding to the intermediate electrode, it is possible to prevent the adhered plating layer from peeling off from the portion corresponding to the corner of the corresponding insulating substrate. If the intermediate extension electrode is constituted by the thick film intermediate extension electrode, the formation of the intermediate extension electrode becomes easy.
（Ａ）乃至（Ｃ）は、本実施の形態のネットワークチップ抵抗器の正面図、底面図及び平面図である。(A) to (C) are a front view, a bottom view, and a plan view of the network chip resistor of the present embodiment. 図１（Ｂ）のII－II線断面である。FIG. 2 is a cross-sectional view taken along the line II-II of FIG. （Ａ）は図１（Ｂ）のIIIＡ－IIIＡ線断面図であり、（Ｂ）は図１（Ｂ）のIIIＢ－IIIＢ線断面図である。(A) is a sectional view taken along the line IIIA-IIIA of FIG. 1 (B), and (B) is a sectional view taken along the line IIIB-IIIB of FIG. 1 (B). 抵抗体Ｒ１及びＲ２を含む本実施の形態のネットワークチップ抵抗器の等価回路である。It is an equivalent circuit of the network chip resistor of the present embodiment including resistors R1 and R2.
　以下、図面を参照して、本発明のネットワークチップ抵抗器の実施の形態の一例を詳細に説明する。図１（Ａ）乃至（Ｃ）は、本実施の形態のネットワークチップ抵抗器の正面図、底面図及び平面図であり、図２は図１（Ｂ）のII－II線断面であり、図３（Ａ）は図１（Ｂ）のIIIＡ－IIIＡ線断面図であり、図３（Ｂ）は図１（Ｂ）のIIIＢ－IIIＢ線断面図である。なお図２及び図３（Ａ）及び（Ｂ）においては、断面であることを示すハッチングを省略してある。また本実施の形態のネットワークチップ抵抗器は、抵抗体が実装回路基板側に向くように逆向きに実装されるため、図１（Ａ），図２及び図３（Ａ）（Ｂ）では絶縁基板の表面が下を向く姿勢で表示してある。 Hereinafter, an example of an embodiment of a network chip resistor of the present invention will be described in detail with reference to the drawings. 1A to 1C are a front view, a bottom view, and a plan view of a network chip resistor according to the present embodiment, and FIG. 2 is a cross-sectional view taken along line II-II of FIG. 3 (A) is a sectional view taken along the line IIIA-IIIA of FIG. 1 (B), and FIG. 3 (B) is a sectional view taken along the line IIIB-IIIB of FIG. 1 (B). In FIGS. 2, 3A, and 3B, hatching indicating a cross section is omitted. Further, since the network chip resistor of the present embodiment is mounted in the reverse direction so that the resistor faces the mounting circuit board, the network chip resistor is insulated in FIGS. 1 (A), 2 and 3 (A) (B). The display is such that the surface of the substrate faces downward.
　これらの図において、１はセラミック製の細長い矩形状に形成された表面１Ａと裏面１Ｂを有する絶縁基板である。絶縁基板１の表面１Ａの上に、一対の端子電極に相当する一対の厚膜端子電極２，２が設けられ、また一対の厚膜端子電極２，２の間には中間電極に相当する厚膜中間電極３が設けられている。厚膜端子電極２，２及び厚膜中間電極３は、それぞれ、銀、パラジウムを含む導電ペーストによりスクリーン印刷をして電極パターンを形成したものを焼成して形成されている。一対の厚膜端子電極２，２と厚膜中間電極３との間には、一対の抵抗体Ｒ１及びＲ２が設けられている。抵抗体Ｒ１及びＲ２は、酸化ルテニウムを含む抵抗ペーストを材料として、絶縁基板１の表面にスクリーン印刷した印刷パターンを焼成することにより形成されている。本実施の形態では、抵抗体Ｒ１及びＲ２の抵抗値は同じである。 に お い て In these figures, reference numeral 1 denotes an insulating substrate having a front surface 1A and a back surface 1B formed in a ceramic elongated rectangular shape. A pair of thick film terminal electrodes 2 and 2 corresponding to a pair of terminal electrodes are provided on the surface 1A of the insulating substrate 1, and a thickness corresponding to an intermediate electrode is provided between the pair of thick film terminal electrodes 2 and 2. A membrane intermediate electrode 3 is provided. The thick- film terminal electrodes 2 and 2 and the thick-film intermediate electrode 3 are each formed by firing an electrode pattern formed by screen printing using a conductive paste containing silver and palladium. A pair of resistors R1 and R2 are provided between the pair of thick- film terminal electrodes 2 and 2 and the thick-film intermediate electrode 3. The resistors R1 and R2 are formed by firing a printing pattern screen-printed on the surface of the insulating substrate 1 using a resistance paste containing ruthenium oxide as a material. In the present embodiment, the resistance values of the resistors R1 and R2 are the same.
　図４は、抵抗体Ｒ１及びＲ２を含む本実施の形態のネットワークチップ抵抗器の等価回路である。 FIG. 4 is an equivalent circuit of the network chip resistor of this embodiment including the resistors R1 and R2.
　また絶縁基板１は、絶縁基板１の長手方向と直交する幅方向に位置する一対の側面１Ｃ及び１Ｄ上に設けられ、一対の厚膜端子電極２，２と電気的に接続された２組の一対の側面電極に相当する一対の薄膜側面電極４，４及び５，５を有している［図３（Ａ）参照］。また一対の側面１Ｃ及び１Ｄ上には、厚膜中間電極３と電気的に接続された一対の中間側面電極に相当する一対の薄膜中間側面電極６，６が形成されている［図３（Ｂ）参照］。薄膜側面電極４，４及び５，５及び一対の薄膜中間側面電極６，６は、それぞれスパッタリングにより形成されたものであり、本実施の形態では、チタン、ニッケル、アルミ、銅等の材料で形成されている。 The insulating substrate 1 is provided on a pair of side surfaces 1C and 1D located in a width direction orthogonal to the longitudinal direction of the insulating substrate 1, and is electrically connected to the pair of thick film terminal electrodes 2 and 2 sets. It has a pair of thin film side electrodes 4, 4, 5 and 5 corresponding to a pair of side electrodes [see FIG. 3 (A)]. Further, on the pair of side surfaces 1C and 1D, a pair of thin film intermediate side electrodes 6, 6 corresponding to a pair of intermediate side electrodes electrically connected to the thick film intermediate electrode 3 are formed [FIG. )reference]. The thin film side electrodes 4, 4 and 5, 5 and the pair of thin film intermediate side electrodes 6, 6 are each formed by sputtering, and in this embodiment, are formed of a material such as titanium, nickel, aluminum, copper, or the like. Have been.
　そして一対の抵抗体Ｒ１及びＲ２の上には、耐メッキ液性を有する材料により形成されて、一対の抵抗体Ｒ１及びＲ２を保護する一対の保護層７が形成されている。保護層７は、ガラス材料からなる第１の保護層７Ａとエポキシ材料からなる第２の保護層７Ｂとから構成されている。 {Circle around (2)} On the pair of resistors R1 and R2, a pair of protective layers 7 formed of a material having plating solution resistance and protecting the pair of resistors R1 and R2 are formed. The protective layer 7 includes a first protective layer 7A made of a glass material and a second protective layer 7B made of an epoxy material.
　本実施の形態のネットワークチップ抵抗器においては、特に、一対の厚膜端子電極２，２及び２組の一対の薄膜側面電極４，４及び５，５の上と、厚膜中間電極３及び一対の薄膜中間側面電極６，６の上にそれぞれ形成された１層以上のメッキ層８とを備えている。本実施の形態では、メッキ層８は、ニッケル（Ｎｉ）からなる第１のメッキ層８Ａと錫（Ｓｎ）からなる第２のメッキ層８Ｂとから構成されている。メッキ層８はバレルメッキにより形成されている。 In the network chip resistor according to the present embodiment, in particular, the pair of thick film terminal electrodes 2 and 2 and the pair of thin film side electrodes 4, 4 and 5 and the pair of thin film side electrodes 4 and 4 and the thick film intermediate electrode 3 and the pair And one or more plating layers 8 respectively formed on the thin-film intermediate side surface electrodes 6, 6. In the present embodiment, the plating layer 8 is composed of a first plating layer 8A made of nickel (Ni) and a second plating layer 8B made of tin (Sn). The plating layer 8 is formed by barrel plating.
　また本実施の形態のネットワークチップ抵抗器においては、一対の薄膜中間側面電極６，６と連続するように、絶縁基板１の裏面１Ｂ上に延びる中間延長電極に相当する厚膜中間延長電極９をさらに有している。この厚膜中間延長電極９も、銀、パラジウムを含む導電ペーストによりスクリーン印刷をして電極パターンを形成したものを焼成して形成されている。 In the network chip resistor according to the present embodiment, the thick film intermediate extension electrode 9 corresponding to the intermediate extension electrode extending on the back surface 1B of the insulating substrate 1 is connected to the pair of thin film intermediate side electrodes 6 and 6 so as to be continuous. Have more. This thick film intermediate extension electrode 9 is also formed by firing an electrode pattern formed by screen printing with a conductive paste containing silver and palladium.
　さらに絶縁基板１の裏面１Ｂには、耐メッキ液性を有する材料により形成されて、少なくとも厚膜中間延長電極９の中央部を覆うようにして絶縁基板１の長手方向に延びるエポキシ樹脂等からなる裏面側保護層１０が設けられている。このように厚膜中間延長電極９を設けると、１層以上のメッキ層８が付着しやすくなる。しかも絶縁基板１の角部に薄膜中間側面電極６，６と厚膜中間延長電極９の連続部が存在するため、付着したメッキ層８が対応する絶縁基板１の角部に対応する部分から剥がれるのを防止できる。 Further, the back surface 1B of the insulating substrate 1 is made of an epoxy resin or the like which is formed of a material having plating liquid resistance and extends in the longitudinal direction of the insulating substrate 1 so as to cover at least the central portion of the thick film intermediate extension electrode 9. A backside protective layer 10 is provided. When the thick film intermediate extension electrode 9 is provided in this manner, one or more plating layers 8 are easily attached. Moreover, since the continuous portions of the thin-film intermediate side surface electrodes 6 and 6 and the thick-film intermediate extension electrode 9 are present at the corners of the insulating substrate 1, the adhered plating layer 8 is peeled off from the corresponding portions of the insulating substrate 1. Can be prevented.
　また半田付けの際に、一対の薄膜中間側面電極６，６が剥がれることを防止できるという効果が得られる。また裏面側保護層１０は、ネットワークチップ抵抗器を吸着ノズルで吸着して回路基板に実装する際に、吸着ノズルの吸着面を構成して、吸着ノズルの先端面の摩耗を防止している。 (4) The effect of preventing the pair of thin-film intermediate side surface electrodes 6 and 6 from peeling off during soldering can be obtained. When the network chip resistor is sucked by the suction nozzle and mounted on the circuit board, the backside protective layer 10 constitutes a suction surface of the suction nozzle to prevent wear of the tip surface of the suction nozzle.
　本実施の形態のネットワークチップ抵抗器は、絶縁基板１に、一対の厚膜端子電極２，２と、両厚膜端子電極２，２間を橋絡する抵抗体Ｒ１及びＲ２と、抵抗体Ｒ１及びＲ２に接続する厚膜中間電極３と、薄膜中間側面電極６，６を、分圧回路用の電極として設けることにより、ワンチップで分圧回路を構成することができる。その結果、実装面積が小さくなって電子部品のさらなる小型化が可能となる。また、半田付けなどが削減でき、実装作業の効率化が図れる。 The network chip resistor according to the present embodiment includes a pair of thick film terminal electrodes 2 and 2, resistors R 1 and R 2 bridging between both thick film terminal electrodes 2 and 2, and a resistor R 1 By providing the thick-film intermediate electrode 3 connected to R2 and R2 and the thin-film intermediate side surface electrodes 6 and 6 as electrodes for a voltage dividing circuit, a voltage dividing circuit can be constituted by one chip. As a result, the mounting area is reduced, and the electronic component can be further downsized. In addition, soldering and the like can be reduced, and the efficiency of the mounting operation can be increased.
　本実施の形態では、厚膜中間延長電極９を設けたが、この厚膜中間延長電極９は設けなくてもよいし、途中で切断されていてもよいのは勿論である。また厚膜中間延長電極９を薄膜電極で覆ってもよいのは勿論である。 In the present embodiment, the thick-film intermediate extension electrode 9 is provided. However, the thick-film intermediate extension electrode 9 may not be provided, or may be cut in the middle. Also, the thick film intermediate extension electrode 9 may of course be covered with a thin film electrode.
　本実施の形態のネットワークチップ抵抗器を回路基板に実装する際には、図２に示すように絶縁基板１の表面１Ａを回路基板側に向け、２組の一対の薄膜側面電極４，４及び５，５及び一対の薄膜中間側面電極６，６の途中まで半田フィレットが形成されるように、厚膜端子電極２，２及び厚膜中間電極３の上にメッキ層８を介して半田が付けられる。このようにすると絶縁基板１の長手方向の両端面に、半田フィレットが形成されることがないので、半田付け時にチップ抵抗器が立つマンハッタン現象の発生を防止することができる。 When mounting the network chip resistor of the present embodiment on a circuit board, as shown in FIG. 2, the surface 1A of the insulating substrate 1 faces the circuit board, and two pairs of thin film side electrodes 4, 4 and Solder is applied via the plating layer 8 on the thick- film terminal electrodes 2 and 2 and the thick-film intermediate electrode 3 so that a solder fillet is formed halfway between the thin-film intermediate electrodes 5 and 5 and the pair of thin-film intermediate side electrodes 6 and 6. Can be In this manner, since no solder fillet is formed on both end surfaces in the longitudinal direction of the insulating substrate 1, it is possible to prevent the occurrence of the Manhattan phenomenon in which the chip resistor rises during soldering.
　なお本実施の形態のネットワークチップ抵抗器の具体的基準寸法は、Ｌ＝０．６ｍｍ、Ｗ＝０．３ｍｍ、Ｔ＝０．２２ｍｍ、Ａ＝０．１ｍｍ。Ｂ＝０．９５ｍｍ、Ｃ＝０．１６ｍｍである。また抵抗体Ｒ１及びＲ２の抵抗値は、１０オーム～１メグオームである。 Specific reference dimensions of the network chip resistor according to the present embodiment are L = 0.6 mm, W = 0.3 mm, T = 0.22 mm, and A = 0.1 mm. B = 0.95 mm and C = 0.16 mm. The resistance values of the resistors R1 and R2 are 10 ohms to 1 megohm.
　上記実施の形態では、絶縁基板１としてセラミック基板を用いたが、その他の絶縁基板を用いてもよいのは勿論である。また上記実施の形態では、薄膜側面電極４，４及び５，５及び一対の薄膜中間側面電極６，６をスパッタリングにより形成したが、これらを蒸着等のその他の薄膜形成技術により形成してもよいのは勿論である。 In the above embodiment, the ceramic substrate is used as the insulating substrate 1, but it goes without saying that another insulating substrate may be used. In the above embodiment, the thin film side electrodes 4, 4, and 5, and the pair of thin film intermediate side electrodes 6, 6 are formed by sputtering, but they may be formed by other thin film forming techniques such as vapor deposition. Of course.
　また上記実施の形態では、一対の端子電極及び中間電極は、一対の厚膜端子電極及び厚膜中間電極により構成しているが、これらの電極を薄膜電極により形成してもよい。また本実施の形態では、一対の側面電極及び一対の中間側面電極は、一対の薄膜側面電極及び一対の薄膜中間側面電極により構成しているが、これらの電極を厚膜により形成してもよいのは勿論である。さらに本実施の形態では中間延長電極を厚膜により形成しているが、この電極を薄膜により形成してもよいのは勿論である。 In the above embodiment, the pair of terminal electrodes and the intermediate electrode are constituted by the pair of thick-film terminal electrodes and the thick-film intermediate electrode. However, these electrodes may be formed by thin-film electrodes. Further, in the present embodiment, the pair of side electrodes and the pair of intermediate side electrodes are constituted by the pair of thin film side electrodes and the pair of thin film intermediate side electrodes, but these electrodes may be formed by thick films. Of course. Further, in the present embodiment, the intermediate extension electrode is formed of a thick film, but this electrode may of course be formed of a thin film.
　本発明のように、２組の一対の側面電極と一対の中間側面電極を設けると、長い絶縁基板の側面が片側３カ所で半田で固定されるため、マンハッタン現象が起こり難くなる。また絶縁基板の長手方向の両端に側面電極がなければ、チップ抵抗器を長手方向が直線状に並ぶように配置しても、隣り合うチップ抵抗器間の間隔を短くすることができ、実装密度を高くすることができる。 (4) When two pairs of side electrodes and a pair of intermediate side electrodes are provided as in the present invention, the side surfaces of the long insulating substrate are fixed by solder at three places on one side, so that the Manhattan phenomenon hardly occurs. Also, if there are no side electrodes at both ends in the longitudinal direction of the insulating substrate, even if the chip resistors are arranged so that the longitudinal direction is linear, the distance between adjacent chip resistors can be shortened, and the mounting density can be reduced. Can be higher.
　１　絶縁基板
　２　厚膜端子電極
　３　厚膜中間電極
　４　薄膜側面電極
　５　薄膜側面電極
　６　薄膜中間側面電極
　７　保護層
　８　メッキ層
　９　厚膜中間延長電極
　１０　裏面側保護層 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Thick film terminal electrode 3 Thick film intermediate electrode 4 Thin film side electrode 5 Thin film side electrode 6 Thin film middle side electrode 7 Protective layer 8 Plating layer 9 Thick film middle extension electrode 10 Back side protective layer

Claims (5)

  1. 　表面と裏面を有する細長い絶縁基板と、
    　前記絶縁基板の前記表面の長手方向の両端に設けられた一対の端子電極と、
    　前記絶縁基板の前記長手方向と直交する幅方向に位置する一対の側面上に少なくとも設けられ、前記一対の端子電極と電気的に接続された２組の一対の側面電極と、
    　前記絶縁基板の前記表面の前記一対の端子電極の間に設けられた中間電極と、
    　前記一対の側面上に少なくとも設けられ、前記中間電極と電気的に接続された一対の中間側面電極と、
    　前記一対の端子電極と前記中間電極との間に設けられた一対の抵抗体と、
    　耐メッキ液性を有する材料により形成されて、前記一対の抵抗体の上に設けられた一対の保護層と、
    　前記一対の端子電極及び前記２組の一対の側面電極の上と、前記中間電極及び前記一対の中間側面電極の上にそれぞれ形成された１層以上のメッキ層とを備えてなるネットワークチップ抵抗器。     An elongated insulating substrate having a front surface and a back surface,
    A pair of terminal electrodes provided at both ends in the longitudinal direction of the surface of the insulating substrate,
    Two pairs of side electrodes provided at least on a pair of side surfaces positioned in a width direction orthogonal to the longitudinal direction of the insulating substrate, and electrically connected to the pair of terminal electrodes,
    An intermediate electrode provided between the pair of terminal electrodes on the surface of the insulating substrate,
    A pair of intermediate side electrodes provided at least on the pair of side surfaces and electrically connected to the intermediate electrode,
    A pair of resistors provided between the pair of terminal electrodes and the intermediate electrode,
    A pair of protective layers formed of a material having plating liquid resistance and provided on the pair of resistors,
    A network chip resistor comprising: the pair of terminal electrodes and the two pairs of side electrodes; and one or more plating layers formed on the intermediate electrode and the pair of intermediate side electrodes, respectively. .
  2. 　前記一対の端子電極及び前記中間電極は、一対の厚膜端子電極及び厚膜中間電極により構成されている請求項１に記載のネットワークチップ抵抗器。 The network chip resistor according to claim 1, wherein the pair of terminal electrodes and the intermediate electrode are constituted by a pair of thick-film terminal electrodes and a thick-film intermediate electrode.
  3. 　前記一対の側面電極及び前記一対の中間側面電極は、一対の薄膜側面電極及び一対の薄膜中間側面電極により構成されている請求項１に記載のネットワークチップ抵抗器。 The network chip resistor according to claim 1, wherein the pair of side electrodes and the pair of intermediate side electrodes are formed by a pair of thin film side electrodes and a pair of thin film intermediate side electrodes.
  4. 　前記中間側面電極から延びて、前記絶縁基板の前記裏面上に延びる中間延長電極をさらに有しており、
    　前記絶縁基板の前記裏面には、耐メッキ液性を有する材料により形成されて、少なくとも前記中間延長電極の中央部を覆うようにして前記絶縁基板の長手方向に延びる裏面側保護層が設けられている請求項１乃至３のいずれか１項に記載のネットワークチップ抵抗器。     An intermediate extension electrode extending from the intermediate side electrode and extending on the back surface of the insulating substrate,
    On the back surface of the insulating substrate, there is provided a back surface side protective layer formed of a material having plating solution resistance and extending in a longitudinal direction of the insulating substrate so as to cover at least a central portion of the intermediate extension electrode. The network chip resistor according to any one of claims 1 to 3, wherein
  5. 　前記中間延長電極は厚膜中間延長電極により構成されている請求項４に記載のネットワークチップ抵抗器。 The network chip resistor according to claim 4, wherein the intermediate extension electrode comprises a thick film intermediate extension electrode.
PCT/JP2019/026034 2018-07-02 2019-07-01 Network chip resistor WO2020009051A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984802U (en) * 1982-11-29 1984-06-08 株式会社村田製作所 chip resistor
JPS6381901A (en) * 1986-09-26 1988-04-12 株式会社日立製作所 Chip resistor
JPH11317301A (en) * 1998-04-30 1999-11-16 Taiyosha Denki Kk Chip-type part and manufacture of the same
JP2009295813A (en) * 2008-06-05 2009-12-17 Hokuriku Electric Ind Co Ltd Chip-like electric component and method of manufacturing the same
JP2018006726A (en) * 2016-06-27 2018-01-11 サムソン エレクトロ−メカニックス カンパニーリミテッド． Resistive element and mounting substrate of the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984802U (en) * 1982-11-29 1984-06-08 株式会社村田製作所 chip resistor
JPS6381901A (en) * 1986-09-26 1988-04-12 株式会社日立製作所 Chip resistor
JPH11317301A (en) * 1998-04-30 1999-11-16 Taiyosha Denki Kk Chip-type part and manufacture of the same
JP2009295813A (en) * 2008-06-05 2009-12-17 Hokuriku Electric Ind Co Ltd Chip-like electric component and method of manufacturing the same
JP2018006726A (en) * 2016-06-27 2018-01-11 サムソン エレクトロ−メカニックス カンパニーリミテッド． Resistive element and mounting substrate of the same

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