KR101058606B1 - Array Type Chip Resistor - Google Patents

Abstract

The present invention relates to an array type chip resistor.

An array type chip resistor of the present invention comprises a substrate composed of a rectangular parallelepiped; Lower electrodes disposed on both sides of the lower surface of the substrate at equal intervals; A side electrode extending from a lower electrode formed at both ends of the lowermost electrode among the lower electrodes to a side surface of the substrate; A resistor interposed between the lower electrodes on the lower surface of the substrate; A protective layer covered on the resistor and having both sides covering a portion of the lower electrode at the same time; A leveling electrode in contact with the lower electrode exposed to the outside of the protective layer; And a plating layer formed on the leveling electrode, and since the resistor is printed inside the lower electrode of the lower surface of the substrate, there is an advantage of preventing damage of the resistor due to external impact when mounting the substrate.

Chip Resistor, Resistor, Electrode, Plating Layer, Insulation Layer, Short

Description

Array type chip resistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array type chip resistor, and more particularly, to an array type chip resistor in which a resistor is disposed under a substrate to prevent breakage of the resistor due to external impact.

In general, a chip resistor refers to a resistor manufactured in the form of a semiconductor package by mounting several resistors in one body in order to increase the degree of integration of electronic products.

Such chip resistors are mainly mounted on semiconductor modules. Personal computers (PCs) and servers are gradually smaller in size, whereas semiconductor modules, such as memory modules, mounted on personal computers or servers are limited in reducing their size. There is.

Therefore, in order to increase the degree of integration, the chip resistor mounted on the memory module is an array type chip resistor in which a plurality of resistors are integrated.

Such an array type chip resistor is mainly used to reduce noise of signal waves reflected from a semiconductor package in which a memory module is mounted. However, conventional chip resistors may generate various quality problems due to external environment when mounted on a printed circuit board. The problem is pointed out.

That is, the conventional chip resistor comprises a substrate, a resistor formed on the upper surface of the substrate, and an external electrode connected to the resistor and extending from the upper surface to the side and the lower surface of the substrate. At this time, the external electrode is composed of a terminal of the conductor and is used as an electrical connection means when mounting the printed circuit board of the chip resistor.

The conventional chip resistors configured as described above are broken when the edges of the substrate and the substrate are broken by the external impact due to the carelessness of the operator when the printed circuit board is mounted or transported for mounting. Problems that may damage the resistor may occur.

In addition, the conventional chip resistor may cause a scratch phenomenon in which the coating material of the external electrode printed on the side is peeled off by external friction or contact between the chip resistors, and an electrode during soldering work to mount the chip resistor by scratching. Short liver can occur.

On the other hand, in order to prevent the short-circuit caused by scratching the external electrode of the chip resistor, the barrier layer is formed between the electrodes when the upper electrode connected to the resistor is formed, but the short prevention effect is only minimal.

Accordingly, the present invention was devised to solve the above-mentioned disadvantages and problems in the conventional chip resistor, and the resistor is disposed on the bottom surface of the substrate to prevent the resistor from being exposed to the outside when the substrate is mounted. It is an object of the invention to provide an array type chip resistor so that breakage can be prevented.

In addition, another object of the present invention is to provide an array type chip resistor to prevent the occurrence of short circuit due to scratches by minimizing the area of the side electrode and the top electrode exposed to the outside of the substrate.

The object of the present invention, the substrate consisting of a rectangular parallelepiped; Lower electrodes disposed on both sides of the lower surface of the substrate at equal intervals; A side electrode extending from the outermost bottom electrode of the bottom electrodes to the side of the substrate; A resistor interposed between the lower electrodes on the lower surface of the substrate; A protective layer covered on the resistor and having both sides covering a portion of the lower electrode at the same time; A leveling electrode in contact with the lower electrode exposed to the outside of the protective layer; And a plating layer formed on the leveling electrode.

According to a preferred embodiment of the present invention, the substrate is composed of alumina of anodized insulating material of the surface of aluminum serves to dissipate heat generated from the resistor to the outside.

In addition, the lower electrode is in electrical contact with the pad formed on the main substrate when mounting the main substrate of the chip resistor according to the invention, from the lower electrode formed on the outermost of the lower electrodes, that is, from the lower electrode formed on both ends of the substrate The side electrode extends to the side of the substrate.

In this case, the side electrode may be formed with an electrode formation height of 50% to 100% compared to the side height of the substrate.

In addition, the protective layer covered by the resistor may be made of silicon or glass, and may be covered up to an inner portion of the lower electrode exposed to both sides of the resistor to completely cover the resistor.

In this case, the resistor may be formed with a groove in which a portion of the resistor is cut by trimming using a laser in order to realize an accurate resistance value after the protection layer is covered.

In addition, the leveling electrode is an electrode for extending the effective area of the lower electrode, the effective contact area can be reduced by the protective layer is preferably formed on the lower electrode exposed to the outside of the protective layer.

In addition, the plating layer grows a plating layer of nickel-tin on the leveling electrode so as to be exposed to the outside of the chip resistor according to the present invention to form an external electrode simultaneously with protecting the lower electrode.

In addition, the chip resistor of the present invention may further include an insulating layer covering the outside of the protective layer, the insulating layer is composed of a polymer to finally protect the resistor and to form a plating layer to form a plating layer for forming the external electrode to the resistor Penetration can be prevented.

At this time, the plating height of the plating layer is preferably formed to be higher than the height of the insulating layer.

Chip resistor according to another embodiment of the present invention for achieving the technical problem is a substrate consisting of a rectangular parallelepiped; Lower electrodes disposed at both sides of the lower surface of the substrate at equal intervals, and electrodes disposed at both ends of the substrate extending to edges of the substrate; A resistor interposed between the lower electrodes on the lower surface of the substrate; A protective layer covered on the resistor and having both sides covering a portion of the lower electrode at the same time; A leveling electrode in contact with the lower electrode exposed to the outside of the protective layer; And a plating layer formed on the leveling electrode, the plating layer having one side extending to contact the edge side of the substrate to correspond to the lower electrode extending toward the edge of the substrate.

In this case, the lower electrode may extend to the side of the substrate to form a side electrode, and the side electrode may be formed at an electrode formation height within 20% of the side height when formed on the side of the substrate.

As described above, according to the present invention, since the resistor is printed inside the lower electrode of the lower surface of the substrate, the chip resistor has an advantage of preventing damage to the resistor due to external impact when mounting the substrate.

In addition, the present invention has a side electrode formed on the side of the substrate is formed extending from the lower electrode of the outer side can be produced an effect that can prevent the generation of short between the electrodes due to scratches during soldering.

In addition, according to the present invention, the side electrode is minimized and the upper electrode is not formed separately, thereby reducing the amount of use of the electrode forming paste. There is an advantage to enabling mounting.

Matters relating to the operational effects, including the technical configuration for the above object of the chip resistor according to the present invention, will be clearly understood by the following detailed description with reference to the drawings in which preferred embodiments of the present invention are shown.

First, FIG. 1 is a perspective view of an embodiment chip resistor according to the present invention, FIG. 2 is a bottom perspective view of an embodiment chip resistor according to the present invention, and FIG. 3 is a plan view of an embodiment chip resistor according to the present invention. 4 is a back view of a chip resistor according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along line II ′ and II ′ of FIG. 1.

As shown, the chip resistor 100 according to the present embodiment includes a substrate 110 composed of a rectangular parallelepiped, a plurality of lower electrodes electrically connected to the resistor 120 and the resistor 120 formed on the bottom surface of the substrate 110. It consists of 130.

The substrate 110 may be configured in a thin plate shape having a rectangular parallelepiped shape, and may be formed of an alumina material insulated from an anodized surface. In addition, since the substrate 110 is formed of a material having excellent thermal conductivity, the substrate 110 serves as a heat diffusion passage for dissipating heat generated by the resistor 120 to the outside when the surface of the chip resistor 100 is mounted.

A plurality of lower electrodes 130 are formed on both sides of the substrate 110 at predetermined intervals. In addition, a resistor 120 containing mainly ruthenium oxide (RuO) as a main component is printed at the center of the lower surface of the substrate 110 inside the lower electrode 130. In this case, the resistor 120 and the plurality of lower electrodes 130 disposed outside thereof are electrically connected to each other.

When the resistor 120 is printed inside the lower electrode 130 formed at both sides of the lower surface of the substrate 110, the resistor 120 is connected to the lower electrode 130 for stable electrical connection between the resistor 120 and the lower electrode 130. The resistor 120 may be printed to partially cover the resistor 120.

In addition, the lower electrodes 130 may have the same size and are disposed at equal intervals, and the lower electrodes 130 disposed at equal intervals when the main substrate (not shown) of the chip resistor 100 is mounted on the main substrate. The pads are electrically joined together to face the formed pads.

The lower electrode 130 may extend to the side of the substrate 110 to form a side electrode 140, and the side electrode 140 may be disposed at the outermost side of the bottom surface of the substrate 110 among the lower electrodes 130. The lower electrode 130, that is, the four lower electrodes 130 formed at the edges of both ends of the substrate 110, extends to the side surface of the substrate 110.

At this time, the side electrode 140 is preferably formed with an electrode formation height of 50% to 100% compared to the side height of the substrate 110. In addition, the side electrode 140 may be formed of the same material as the bottom electrode 130 after the bottom electrode 130 is formed, but may extend from the bottom electrode. The electrode 140 may be formed.

The side electrode 140 is formed to improve the adhesion strength which is insufficient when soldering only the lower electrode 130 when the main substrate is mounted on the chip resistor 100, and is formed on the side of the substrate 110 when soldering the chip resistor 100. Side bonding of the solder may be performed on the side electrodes 140 formed at both ends, thereby improving bonding performance of the chip resistor 100.

Since the side electrodes 140 are disposed at both end sides of the side surfaces of the substrate 110, even if scratches are generated in the chip resistor 100 itself, the solder bonded to the side electrodes 140 may not invade the adjacent electrodes. Shorting by electrical contact between electrodes can be prevented.

On the other hand, a protective layer 160 for protecting the resistor 120 from external impact is covered on the resistor 120 printed between the lower electrodes 130 to have a predetermined thickness. In this case, the protective layer 160 is preferably made of silicon (SiO ₂ ) or glass (glass) material, and may be formed on the protective layer 160 by overcoating.

The protective layer 160 is formed on the exposed entire surface of the resistor 120 for the purpose of protecting the resistor 120, but the lower electrode provided outside the resistor 120 to completely seal the resistor 120. It is preferred that the inner portion of 130 also be covered at the same time.

The resistor 120 on which the protective layer 160 is formed is to prevent the flow of current through the chip resistor 100 when the surface is mounted so that the resistance characteristics are realized. An appropriate capacitance value must be realized and the protective layer 160 is formed. Afterwards, it is possible to have the resistance value of the appropriate capacity by performing the trimming process through the laser so that the proper capacity value can be implemented.

That is, if the resistance value that can be implemented in the chip resistor 100 is 100 Ω, since the resistor 120 having exactly 100 Ω cannot be formed when the resistor 120 is printed, the resistor 120 may have a resistance value of about 80 to 90 Ω. And forming a recessed groove by trimming the resistor 120 with a laser to increase the resistance value so that 100 Ω of the design value can be realized.

At this time, the protective layer 160 is formed on the resistor 120 and the reason why the trimming of the resistor 120 is formed is such that the crack of the resistor 120 is prevented by the protector 160 during the trimming process through the laser. To do this.

After the protective layer 160 covering the resistor 120 is formed, the leveling electrode 170 is in contact with the lower electrode 130. The leveling electrode 170 may be formed on an edge portion of the protective layer 160 covering the lower electrode 130 and a portion of the lower electrode 130, and extends the smaller effective area of the lower electrode 130. It serves to enable stable electrode contact.

In addition, the leveling electrode 170 is formed at a predetermined height on the lower electrode 130. The reason for forming the leveling electrode 170 in addition to the lower electrode 130 is that a resistor printed on the bottom surface of the substrate 110 is provided. This is to increase the height of the final electrode rather than the height of the insulating layer (described below) including the 120 and the protective layer 160.

That is, the leveling electrode 170 adjusts the height of the electrode to a height substantially equal to the height of the resistor 120 formed on the bottom surface of the substrate 110 and the protective layer 160, and the resistor 120 and the protective layer 160. When forming, it is in contact with the smaller effective area of the lower electrode 130 to expand the area of the electrode to ensure the stability of the electrode and to facilitate the subsequent formation of the plating layer.

On the other hand, the plating layer 180 for the final external electrode formation is formed on the leveling electrode 170. The plating layer 180 may be sequentially nickel (Ni) plating and tin (Sn) plating, the plating layer 180 may be formed through electrolytic plating or electroless plating.

At this time, the nickel plating layer is a plating layer for protecting the leveling electrode 170 when soldering, the tin plating layer is formed for easy soldering when soldering.

In addition, the chip resistor 100 of the present exemplary embodiment may further include an insulating layer 190 covering the entirety of the protective layer 160 when the external electrode is formed by the plating layer 180. Like the protective layer 160, the insulating layer 190 is preferably made of glass or polymer material, and finally serves to protect the resistor 120.

In addition, the insulating layer 190 thoroughly blocks the external exposure of the resistor 120 to protect the resistor 120 from external shocks, and also the leveling electrode, which is an entire electrode and an additional electrode of the protective layer 120. By covering a portion of the 170, the plating liquid may be prevented from penetrating into the resistor 120 when the plating layer 180 for forming the external electrode is formed.

At this time, the plating layer 180 formed on both sides of the insulating layer 190 is preferably formed higher than the height of the center portion of the insulating layer 190. The reason why the height of the plating layer 180 on both sides of the insulating layer 190 is high is to enable stable mounting when mounting the main board (PCB) of the chip resistor 100 according to the present embodiment. When the convex center portion of the layer 190 is formed higher than the plating layer 180, the tombstone defect in which the chip resistor 110 is inclined to one side and mounted on the main substrate by the convex portion of the center when soldering the chip resistor 110 is prevented. This is to prevent the occurrence.

Next, Figure 6 is a perspective view of the main board mounting of the chip resistor according to the embodiment.

As shown, the chip resistor 100 according to the present embodiment has an insulating layer 190 and a plating layer 180 surrounding the lower electrode 130 and the resistor 120 when the chip resistor 100 is mounted on the main substrate PCB. ) Is mounted so as to be in contact with the resistor 120 to prevent external exposure of the resistor 120.

After the chip resistor 100 is mounted, the bonding with the main board (PCB) is performed by soldering, and the molten solder (S) during the soldering bonding of the chip resistor 100 is the bottom electrode 130 of the chip resistor 100. And the side electrode 140 are bonded in the form as shown in FIG. 6.

At this time, the solder (S) is bonded on the four side electrodes 140 formed on both side ends of the chip resistor 100 can improve the bonding strength of the main substrate (PCB) and the chip resistor (100).

As described above, when the chip resistor 100 is bonded to the main board PCB, the gap between the side electrodes 140 formed on the side surface of the substrate 110 is relatively wide. Even if scratches are generated on the side surface, the occurrence of a short may be prevented by the interference of the solder S between the adjacent electrodes.

Next, Figures 7 to 11 are views of another embodiment of a chip resistor according to the invention, Figure 7 is a perspective view of another embodiment chip resistor according to the present invention, Figure 8 is another embodiment chip resistor according to the present invention 9 and 10 are a plan view and a rear view of another embodiment chip resistor according to the present invention, and FIG. 11 is a cross-sectional view of the chip resistor of another embodiment according to the present invention.

In the detailed description of the present embodiment, overlapping descriptions of the same technical configuration as the above-described embodiment are avoided, and the same reference numerals refer to the same technical components.

As shown, the chip resistor 100 according to the present embodiment includes a substrate 110 composed of a rectangular parallelepiped, a plurality of lower electrodes electrically connected to the resistor 120 and the resistor 120 formed on the bottom surface of the substrate 110. The lower electrode 130, which is disposed at the outer side of the lower electrode 130, extends to the corner side of the substrate 110.

Since the substrate 110 may be formed of an alumina material having an anodized surface and insulated and having excellent thermal conductivity, the substrate 110 may dissipate heat generated by the resistor 120 to the outside when the chip resistor 100 is mounted on the surface. It will act as a passageway.

A plurality of lower electrodes 130 are formed on both sides of the substrate 110 at predetermined equal intervals. In addition, a resistor 120 containing mainly ruthenium oxide (RuO) as a main component is printed at the center of the lower surface of the substrate 110 inside the lower electrode 130. In this case, the resistor 120 and the plurality of lower electrodes 130 disposed outside thereof are electrically connected to each other.

In addition, the lower electrode 130 is formed at the outermost side of the lower surface of the substrate 110, that is, the lower electrode 130 disposed at both ends of the lower surface of the substrate 110 to extend to each corner of the substrate 110. The lower electrodes 130 are disposed at equal intervals of the same size.

In other words, the four lower electrodes 130 formed at each corner side of the lower surface of the substrate 110 among the eight lower electrodes 110 formed on the lower surface of the substrate 110 may extend to contact each corner and one end thereof. Four lower electrodes 130 provided therein may be formed in a general size.

When the lower electrode 130 is mounted on the main substrate (not shown) of the chip resistor 100, the lower electrodes 130 disposed at equal intervals face the pads formed on the main substrate and are electrically connected to each other through solder.

At this time, by forming the lower electrode formed on the edge side of the substrate 110 of the lower electrode 130 to be larger than the other lower electrodes, the bonding area of the edge side of the substrate 110 is kept wide, thereby providing a chip resistor 100 on the main substrate. To maintain a constant fixation strength.

Although not shown in the drawings below, a side electrode (not shown) may be formed from the lower electrode 130 to the side of the substrate 110. The height is lower than the side height of the side of the substrate 110. That is, the side electrodes may be formed to have an electrode formation height of less than 20% of the substrate side height.

Such a side electrode may further improve the main substrate adhesion strength of the chip resistor 100 by allowing the solder to be bonded to the side of the substrate 110 when soldering the chip resistor 100.

In the chip resistor 100 according to the present exemplary embodiment, the side electrode and the upper electrode exposed to the outside of the substrate 110 are not formed separately, and the chip resistor 100 may be mounted on the substrate 110 using only the lower electrode 130. ) Even if a scratch is generated on its own, shortening due to electrical contact between electrodes can be prevented by minimizing solder bonded to the outside of the substrate 110.

On the other hand, a protective layer 160 for protecting the resistor 120 from external impact is covered on the resistor 120 printed between the lower electrodes 130 to have a predetermined thickness.

The protective layer 160 is formed on the exposed entire surface of the resistor 120 for the purpose of protecting the resistor 120, but the lower electrode provided outside the resistor 120 to completely seal the resistor 120. It is preferred that the inner portion of 130 also be covered at the same time.

The resistor 120 on which the protective layer 160 is formed is to prevent the flow of current through the chip resistor 200 when the surface is mounted so that the resistance characteristics are realized. An appropriate capacitance value must be realized and the protective layer 160 is formed. Afterwards, it is possible to have the resistance value of the appropriate capacity by performing the trimming process through the laser so that the proper capacity value can be implemented.

After the protective layer 160 covering the resistor 120 is formed, the leveling electrode 170 is in contact with the lower electrode 130. The leveling electrode 170 may be formed on an edge portion of the protective layer 160 covering the lower electrode 130 and a portion of the lower electrode 130, and extends the smaller effective area of the lower electrode 130. It serves to enable stable electrode contact.

On the other hand, the plating layer 180 for the final external electrode formation is formed on the leveling electrode 170. The plating layer 180 may be sequentially nickel (Ni) plating and tin (Sn) plating, the plating layer 180 may be formed through electrolytic plating or electroless plating.

In addition, the chip resistor 200 according to the present exemplary embodiment may further include an insulating layer 190 covering the entirety of the protective layer 160 when the external electrode is formed by the plating layer 180. Like the protective layer 160, the insulating layer 190 is preferably made of glass or polymer material, and finally serves to protect the resistor 120.

At this time, the plating layer 180 formed on both sides of the insulating layer 190 is preferably formed higher than the height of the center portion of the insulating layer 190.

In the chip resistor 200 according to the present exemplary embodiment, the insulating layer 190 and the plating layer 180 surrounding the lower electrode 130 and the resistor 120 are brought into contact with the main substrate PCB when the chip resistor 200 is mounted on the main substrate. Mounted to prevent external exposure.

After the chip resistor 200 is mounted, the bonding with the main board PCB is performed through soldering. During the soldering bonding of the chip resistor 200, the molten solder S is lower electrode 130 of the chip resistor 200. Is bonded).

At this time, if the solder (S) is not exposed to the outside of the chip resistor 200, by extending the contact area of the lower electrode 130 extending to the corner side only by solder bonding of the lower electrode 130 to the main board (PCB) ) And the chip strength of the chip 200 can be maintained.

As such, when the chip resistor 200 of the present embodiment is bonded to the main board PCB, even if scratches are generated in the upper edge of the board, short circuit between the electrodes during the soldering operation can be prevented.

The chip resistors 100 and 200 of the present invention configured as described above are disposed so that the resistor 120 is not exposed to the outside when the main board PCB is mounted as the resistor 120 is disposed at the center of the bottom surface of the substrate 110. In addition, even when an external shock is applied to the chip resistors 100 and 200, the resistor 120 may be protected and not damaged, and the resistance of the resistor 120 may be prevented from being damaged to maintain its inherent resistance characteristics.

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It will be possible, but such substitutions, changes and the like should be regarded as belonging to the following claims.

1 is a perspective view of an embodiment of a chip resistor in accordance with the present invention.

2 is a bottom perspective view of an embodiment chip resistor in accordance with the present invention;

3 is a plan view of an embodiment chip resistor according to the present invention;

4 is a back view of a chip resistor of one embodiment according to the present invention;

5 is a cross-sectional view taken along line II ′ and II-II ′ of FIG. 1.

Figure 6 is a perspective view of the main board mounting of the chip resistor according to the embodiment.

7 to 11 are views of another embodiment of a chip resistor according to the present invention.

Figure 7 is a perspective view of another embodiment chip resistor according to the present invention.

8 is a bottom perspective view of another embodiment chip resistor according to the present invention;

9 and 10 are a plan view and a rear view of another embodiment chip resistor according to the invention.

11 is a cross-sectional view of a chip resistor of another embodiment according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100,200. Chip Resistor 110. Board

120. Resistor 130. Lower electrode

140. Side electrode 160. Protective layer

170. Leveling electrode 180. Plating layer

190. Insulation Layer S. Solder

Claims (10)

A substrate composed of a cuboid; Lower electrodes disposed on both sides of the lower surface of the substrate at equal intervals; A side electrode extending from a lower electrode formed at both ends of the lower end of the substrate to the side of the substrate among the lower electrodes; A resistor interposed between the lower electrodes on the lower surface of the substrate; A protective layer covered on the resistor and having both sides covering a portion of the lower electrode at the same time; A leveling electrode in contact with the lower electrode exposed to the outside of the protective layer; And A plating layer formed on the leveling electrode; An insulating layer covering an outer portion of the protective layer and an inner portion of the leveling electrode; Array type chip resistor comprising a. The method of claim 1, The substrate is an array type chip resistor consisting of alumina of insulating material anodized aluminum surface. The method of claim 1, The side electrode is an array type chip resistor formed with an electrode formation height of 50% to 100% compared to the side height of the substrate. The method of claim 3, wherein The side electrode may be formed at the same time when the lower electrode is formed of the same material as the lower electrode, and may be formed at the same time when forming the plating layer. The method of claim 1, The protective layer may be formed of a silicon or glass material, the array type chip resistor is covered to the inner portion of the lower electrode exposed to both sides of the resistor. The method of claim 1, And the leveling electrode is formed on an edge portion of the protective layer in contact with an effective area of the lower electrode and covering a portion of the lower electrode. The method of claim 1, The plating layer is an array type chip resistor to form an external electrode by growing a plating layer of nickel-tin on the leveling electrode. delete The method of claim 1, The insulating layer is an array type chip resistor composed of a polymer. The method of claim 1, And the plating layer has a plating height higher than that of the insulating layer.

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