JP2006049896A - ハイパフォーマンスメタライゼーションキャップ層 - Google Patents

ハイパフォーマンスメタライゼーションキャップ層 Download PDF

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Publication number
JP2006049896A
JP2006049896A JP2005218707A JP2005218707A JP2006049896A JP 2006049896 A JP2006049896 A JP 2006049896A JP 2005218707 A JP2005218707 A JP 2005218707A JP 2005218707 A JP2005218707 A JP 2005218707A JP 2006049896 A JP2006049896 A JP 2006049896A
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JP
Japan
Prior art keywords
cap layer
conductive
layer
semiconductor device
conductive line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005218707A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006049896A5 (https=
Inventor
Hsien-Ming Lee
顯銘 李
Toshinari Hayashi
俊成 林
Shing-Chyang Pan
興強 潘
Ching-Hua Hsieh
静華 謝
Chao-Hsien Peng
兆賢 彭
Cheng-Lin Huang
震麟 黄
Li-Lin Su
莉玲 蘇
曉林 ▲すい▼
Shau-Lin Shue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of JP2006049896A publication Critical patent/JP2006049896A/ja
Publication of JP2006049896A5 publication Critical patent/JP2006049896A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/055—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP2005218707A 2004-08-03 2005-07-28 ハイパフォーマンスメタライゼーションキャップ層 Pending JP2006049896A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/909,980 US7253501B2 (en) 2004-08-03 2004-08-03 High performance metallization cap layer

Publications (2)

Publication Number Publication Date
JP2006049896A true JP2006049896A (ja) 2006-02-16
JP2006049896A5 JP2006049896A5 (https=) 2008-01-24

Family

ID=35756619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005218707A Pending JP2006049896A (ja) 2004-08-03 2005-07-28 ハイパフォーマンスメタライゼーションキャップ層

Country Status (4)

Country Link
US (1) US7253501B2 (https=)
JP (1) JP2006049896A (https=)
CN (2) CN2793923Y (https=)
TW (1) TWI251300B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006203197A (ja) * 2005-01-18 2006-08-03 Internatl Business Mach Corp <Ibm> １ないし５ｎｍの厚さの金属キャップを用いる改良されたオンチップＣｕ相互接続

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KR100808601B1 (ko) * 2006-12-28 2008-02-29 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법
DE102007004867B4 (de) * 2007-01-31 2009-07-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erhöhen der Zuverlässigkeit von kupferbasierten Metallisierungsstrukturen in einem Mikrostrukturbauelement durch Anwenden von Aluminiumnitrid
US8525339B2 (en) 2011-07-27 2013-09-03 International Business Machines Corporation Hybrid copper interconnect structure and method of fabricating same
US9312203B2 (en) 2013-01-02 2016-04-12 Globalfoundries Inc. Dual damascene structure with liner
US9490209B2 (en) 2013-03-13 2016-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Electro-migration barrier for Cu interconnect
US20150087144A1 (en) * 2013-09-26 2015-03-26 Taiwan Semiconductor Manufacturing Company Ltd. Apparatus and method of manufacturing metal gate semiconductor device
US9659857B2 (en) 2013-12-13 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method making the same
US20150206798A1 (en) * 2014-01-17 2015-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structure And Method of Forming
US9437484B2 (en) 2014-10-17 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Etch stop layer in integrated circuits
CN108573942B (zh) * 2017-03-09 2021-09-14 联华电子股份有限公司 内连线结构及其制作方法
US11075113B2 (en) 2018-06-29 2021-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Metal capping layer and methods thereof
US12408414B2 (en) * 2021-07-14 2025-09-02 Micron Technology, Inc. Transistor and memory circuitry comprising strings of memory cells

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0148325B1 (ko) * 1995-03-04 1998-12-01 김주용 반도체 소자의 금속 배선 형성방법
US5892281A (en) * 1996-06-10 1999-04-06 Micron Technology, Inc. Tantalum-aluminum-nitrogen material for semiconductor devices
US6153519A (en) * 1997-03-31 2000-11-28 Motorola, Inc. Method of forming a barrier layer
US6074960A (en) * 1997-08-20 2000-06-13 Micron Technology, Inc. Method and composition for selectively etching against cobalt silicide
US6255217B1 (en) * 1999-01-04 2001-07-03 International Business Machines Corporation Plasma treatment to enhance inorganic dielectric adhesion to copper
US6727588B1 (en) * 1999-08-19 2004-04-27 Agere Systems Inc. Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics
US6165891A (en) * 1999-11-22 2000-12-26 Chartered Semiconductor Manufacturing Ltd. Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer
JP3851752B2 (ja) * 2000-03-27 2006-11-29 株式会社東芝 半導体装置の製造方法
US6709874B2 (en) * 2001-01-24 2004-03-23 Infineon Technologies Ag Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation
US6566242B1 (en) * 2001-03-23 2003-05-20 International Business Machines Corporation Dual damascene copper interconnect to a damascene tungsten wiring level
JP2003068848A (ja) * 2001-08-29 2003-03-07 Fujitsu Ltd 半導体装置及びその製造方法
US6680500B1 (en) * 2002-07-31 2004-01-20 Infineon Technologies Ag Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers
US7105429B2 (en) * 2004-03-10 2006-09-12 Freescale Semiconductor, Inc. Method of inhibiting metal silicide encroachment in a transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006203197A (ja) * 2005-01-18 2006-08-03 Internatl Business Mach Corp <Ibm> １ないし５ｎｍの厚さの金属キャップを用いる改良されたオンチップＣｕ相互接続

Also Published As

Publication number Publication date
CN2793923Y (zh) 2006-07-05
CN1734760A (zh) 2006-02-15
US7253501B2 (en) 2007-08-07
TWI251300B (en) 2006-03-11
CN100452385C (zh) 2009-01-14
TW200607042A (en) 2006-02-16
US20060027922A1 (en) 2006-02-09

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