JP2006041090A - ボンディング装置 - Google Patents
ボンディング装置 Download PDFInfo
- Publication number
- JP2006041090A JP2006041090A JP2004217123A JP2004217123A JP2006041090A JP 2006041090 A JP2006041090 A JP 2006041090A JP 2004217123 A JP2004217123 A JP 2004217123A JP 2004217123 A JP2004217123 A JP 2004217123A JP 2006041090 A JP2006041090 A JP 2006041090A
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- chip
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- 230000002950 deficient Effects 0.000 claims description 23
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000003909 pattern recognition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Length Measuring Devices By Optical Means (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
【解決手段】 ピックアップ位置の画像をカメラで取得し、この取得画像からチップの周縁を示すエッジの有無をエッジ認識する(S2)。取得画像にエッジが存在する場合、チップ有りと判断し(S2)、チップの良否を二値化データを用いた二値化認識で判断する(S3)。このチップが良品チップの場合、チップの位置認識処理を行う(S4)。この位置認識処理では、チップ画像を基準となるテンプレートに合わせるパターンマッチングを行い、チップ画像とテンプレートとの相似度を示す相関値を求めるとともにチップの中心座標を求める。そして、相関値が閾値より高い場合には(S5)、当該チップを良品チップとして前記中心座標をウェーハテーブルに出力する(S6)。
【選択図】 図2
Description
4 チップ
4a 良品チップ
4b 不良チップ
11 ウェーハ
14 画像認識システム
21 取得画像
22 エッジ
23 チップ画像
41 テンプレート
51 中心座標
61 NGチップ
Claims (1)
- 対象箇所の画像を取得し、この取得画像を用いて前記対象箇所でのチップの状態を認識する機能を備えたボンディング装置において、
前記取得画像から前記チップの周縁を示すエッジの有無をエッジ認識してチップの有無を判断する有無判断手段と、
前記対象箇所にチップが有ると判断した際に、前記取得画像の二値化データを用いる二値化認識によって当該チップが良品チップであるか不良チップであるかを判断する良否判断手段と、
前記チップが良品チップであると判断した際に、前記取得画像において前記チップを示すチップ画像を基準となるテンプレートに合わせるパターンマッチングによって当該チップの位置を認識する位置認識手段と、
を備えたことを特徴とするボンディング装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004217123A JP4206061B2 (ja) | 2004-07-26 | 2004-07-26 | ボンディング装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004217123A JP4206061B2 (ja) | 2004-07-26 | 2004-07-26 | ボンディング装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006041090A true JP2006041090A (ja) | 2006-02-09 |
JP4206061B2 JP4206061B2 (ja) | 2009-01-07 |
Family
ID=35905782
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004217123A Expired - Fee Related JP4206061B2 (ja) | 2004-07-26 | 2004-07-26 | ボンディング装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4206061B2 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008066452A (ja) * | 2006-09-06 | 2008-03-21 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2012191237A (ja) * | 2012-06-13 | 2012-10-04 | Renesas Electronics Corp | 半導体装置の製造方法 |
CN116313971A (zh) * | 2023-05-17 | 2023-06-23 | 拓荆键科(海宁)半导体设备有限公司 | 通过边缘检测来进行晶圆键合对准的方法 |
-
2004
- 2004-07-26 JP JP2004217123A patent/JP4206061B2/ja not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008066452A (ja) * | 2006-09-06 | 2008-03-21 | Renesas Technology Corp | 半導体装置の製造方法 |
US8574933B2 (en) | 2006-09-06 | 2013-11-05 | Renesas Electronics Corporation | Fabrication method of semiconductor device |
JP2012191237A (ja) * | 2012-06-13 | 2012-10-04 | Renesas Electronics Corp | 半導体装置の製造方法 |
CN116313971A (zh) * | 2023-05-17 | 2023-06-23 | 拓荆键科(海宁)半导体设备有限公司 | 通过边缘检测来进行晶圆键合对准的方法 |
CN116313971B (zh) * | 2023-05-17 | 2023-10-20 | 拓荆键科(海宁)半导体设备有限公司 | 通过边缘检测来进行晶圆键合对准的方法 |
Also Published As
Publication number | Publication date |
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JP4206061B2 (ja) | 2009-01-07 |
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