JP2006024646A - Testing method of semiconductor integrated circuit, and the semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the testing method of a semiconductor integrated circuit which can more easily and accurately test an integrated circuit on a semiconductor wafer, while eliminating post-processes, etc. after testing as well as a testing substrate, and to provide a semiconductor integrated circuit that is used in the method. <P>SOLUTION: Prior to testing a plurality of integrated circuits 12 formed on the semiconductor wafer 11, a feeder pad 13 and feeder interconnections 14 for electrically connecting the feeder pad 13 and individual feeders of the integrated circuits 12 are formed, in advance, in a region on the semiconductor wafer 11 except for the regions where the integrated circuits 12 are formed. Then, by applying voltage of a prescribed value to the feeder pad 13, each integrated circuit 12 on the semiconductor wafer 11 is checked for continuity via the feeder interconnections 14. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for inspecting a semiconductor integrated circuit in which a current test is performed on a plurality of semiconductor integrated circuits formed on a semiconductor wafer and the quality of the plurality of semiconductor integrated circuits is determined, and to the implementation of the inspection method. The present invention relates to a semiconductor integrated circuit used.

  As is well known, in a semiconductor device manufacturing process, a plurality of integrated circuits are formed on a semiconductor wafer through a photolithography process, an etching process, and the like. When a plurality of integrated circuits are thus formed on the semiconductor wafer, the semiconductor wafer is cut into the integrated circuit units in a subsequent dicing process. Each of these semiconductor integrated circuits is further individually packaged through a wire bonding process or a resin sealing process, and finally shipped as a finished product (semiconductor device).

  By the way, in the manufacturing process of such a semiconductor device, an energization test (burn-in test) for inspecting whether or not an initial failure has occurred for each semiconductor integrated circuit is usually performed in order to maintain the quality of the shipped product. . This burn-in test is performed in a state where the plurality of integrated circuits are formed on a semiconductor wafer, and specifically, a so-called acceleration in which a high voltage is applied to these integrated circuits for a short time in a high temperature atmosphere. Performed as a test. After the burn-in test is completed, the quality of each semiconductor integrated circuit is determined. For example, for a semiconductor integrated circuit determined to be defective, this is performed in a normal dicing process performed thereafter. The quality of the shipped product is maintained by disposing it separately from the circuit.

Heretofore, as a method for inspecting a semiconductor integrated circuit for performing such a test and determination, for example, a method as disclosed in Patent Document 1 has been proposed.
In the method described in Patent Document 1, a testing substrate for applying a high voltage to a plurality of integrated circuits provided on a semiconductor wafer is separately prepared. The testing substrate and the semiconductor wafer are electrically connected to face each other, and in this state, the voltage is applied to the integrated circuits through the testing substrate. However, in the semiconductor integrated circuit inspection method described in Patent Document 1, it is necessary to separately prepare the above-described testing substrate for the semiconductor wafer, and an increase in inspection cost is inevitable.

Conventionally, a method for inspecting without using such a testing substrate has also been proposed, such as the method found in Patent Document 2.
That is, in this method, when a plurality of integrated circuits to be inspected are formed on a semiconductor wafer, a protective film is further laminated on one surface of the wafer. A contact hole for forming a power supply terminal and a power supply wiring on the surface of the protective film and electrically connecting the power supply wiring and the power supply portions of the plurality of integrated circuits to a part of the protective film Form. A high voltage is applied to each of the plurality of integrated circuits through the power supply terminal, the power supply wiring, and the contact hole.
JP-A-8-148533 JP-A-8-31889

  As described above, in the semiconductor integrated circuit inspection method described in Patent Document 2, the high voltage is applied to a plurality of integrated circuits formed on a semiconductor wafer without using the testing substrate. Can do. However, in this method, in order to finally ship the plurality of integrated circuits as a finished product (semiconductor device) after the inspection of the plurality of integrated circuits, it becomes unnecessary in addition to the original manufacturing process. A process of removing the protective film and the power supply wiring, that is, a post-processing after inspection is necessary. Such post-processing complicates the inspection of the semiconductor integrated circuit itself.

  The present invention has been made in view of such circumstances, and its purpose is to inspect an integrated circuit on a semiconductor wafer more easily and accurately while not requiring a post-inspection after inspection, as well as a testing substrate. An object of the present invention is to provide a method for inspecting a semiconductor integrated circuit that can be used, and a semiconductor integrated circuit used for carrying out the method.

  In order to achieve such an object, in the method for inspecting a semiconductor integrated circuit according to claim 1, a pass / fail test of the plurality of integrated circuits is performed by conducting an energization test on the plurality of integrated circuits formed on the semiconductor wafer. As a method for inspecting a semiconductor integrated circuit, a power supply wiring electrically connected to each power supply unit of the plurality of integrated circuits in a region excluding a region where the plurality of integrated circuits are formed on the semiconductor wafer, A power supply terminal and a power supply terminal as a ground terminal of the power supply wiring are laid and formed in advance, and a predetermined voltage is applied between the power supply terminal and the ground terminal, whereby the plurality of integrated circuits are passed through the power supply wiring. It was decided to conduct an energization test on

  In the above method, basically, the power supply wiring and the power supply wiring are simply laid and formed in advance in a region (scribe region) where the plurality of integrated circuits are not formed on the semiconductor wafer. Through this, it is possible to perform an energization test (burn-in test) on the plurality of integrated circuits. Moreover, since both the power supply terminal and the power supply wiring are formed and installed in the scribe region, it is not necessary to remove the power supply wiring and the power supply terminal after the inspection, and post-processing after the inspection is not necessary.

  In such a method, as in the invention according to claim 2, the laying of the power supply wiring and the formation of the power supply terminal are the same as the formation of the wiring pattern in each integrated circuit on the semiconductor wafer. If it is performed in the process, the plurality of integrated circuits can be inspected more easily.

  Incidentally, in the method for inspecting a semiconductor integrated circuit described in Patent Document 2, when a plurality of integrated circuits are formed on a semiconductor wafer, a process of laminating and laying a protective film and a power supply wiring on the semiconductor wafer is performed. Do. However, this process is also performed in addition to the original manufacturing process for finally shipping a plurality of integrated circuits as a finished product (semiconductor device), and the inspection of the semiconductor integrated circuit is complicated. It becomes one cause. In this regard, in the above method, the laying of the power supply wiring and the formation of the power supply terminal are performed in the same process as the formation of the wiring pattern in each integrated circuit on the semiconductor wafer. For this reason, the power supply terminal and the power supply wiring that are used only for carrying out the inspection can be formed on the semiconductor wafer only by performing the original manufacturing process as usual, that is, without adding any new process to the original manufacturing process. It can be formed in advance.

  Further, in the semiconductor integrated circuit inspection method according to claim 1 or 2, according to the invention of claim 3, the power supply terminal is formed at an edge on the semiconductor wafer, and the power supply wiring is formed. If the semiconductor wafer is laid along the cutting line when the semiconductor wafer is cut into the integrated circuit unit in the dicing process, most of the power supply terminals and the power supply wiring are naturally removed in the dicing process. Will come to be. In other words, the power supply terminals and the power supply wiring that are no longer necessary after the inspection of the integrated circuit can be removed without adding any new process to the original manufacturing process.

  Moreover, in the inspection method of the semiconductor integrated circuit according to any one of claims 1 to 3, according to the invention of claim 4, the integrated circuit applies the voltage applied to the power supply unit to the voltage Constant voltage means having a constant voltage mode for constant voltage to two voltages, an operating voltage of the integrated circuit and a test voltage higher than the operating voltage, and a voltage applied to the power supply unit are defined as the operating voltage. A control circuit that determines whether the voltage is to be the test voltage or the test voltage and switches the constant voltage mode by the constant voltage means, and sets the test voltage to the power supply terminal. If the energization test is performed on each integrated circuit through the constant voltage mode switching control by the control circuit when a power voltage is applied, the burn-in is performed on the integrated circuit including the constant voltage means. It is possible to perform the test more accurately.

  That is, as described above, in the inspection of the plurality of integrated circuits on the semiconductor wafer, usually, a voltage (high load) higher than the operating voltage of the integrated circuit is applied to each integrated circuit to the power feeding unit. It is determined whether an initial failure has occurred. However, when each integrated circuit to be inspected includes a constant voltage means, the high voltage applied to the power feeding unit is also made constant by the constant voltage means, Therefore, it becomes difficult to apply a voltage higher than that during operation.

  In this regard, in the above method, the constant voltage has a constant voltage mode in which the voltage applied to the power supply unit is constant to two kinds of voltages, that is, an operating voltage of the integrated circuit and a test voltage higher than the operating voltage. And a control for switching and controlling the constant voltage mode by the constant voltage means by determining whether the voltage applied to the power supply unit is the voltage to be the operating voltage or the test voltage. And a circuit. For this reason, even in an integrated circuit including constant voltage means, a high voltage suitable for the acceleration test described above can be applied to the integrated circuit through constant voltage mode switching control by the control circuit. .

  In this case, in particular, as in the invention described in claim 5, the voltage to be used as the test voltage is modulated in a predetermined manner and applied to the power supply unit of each integrated circuit, and the control circuit If the modulated voltage is demodulated and the constant voltage mode is switched and controlled so that the voltage applied to the constant voltage means is constant as the test voltage, the constant voltage by the control means is obtained. Mode control can be easily realized.

  Further, in the invention according to any one of claims 1 to 5, as in the invention according to claim 6, each integrated circuit is self-assessed according to the result of the energization test. If a determination circuit for determination is further provided, the inspection of the semiconductor integrated circuit is further simplified.

  Further, according to the invention of claim 7, if the result of self-determination by the determination circuit is stored in the storage means included in each integrated circuit, it becomes easy to determine the defect of the integrated circuit, For example, an integrated circuit determined to be defective after inspection can be easily separated from other normal integrated circuits.

  Further, in the invention according to claim 6 or claim 7, as in the invention according to claim 8, when each of the integrated circuits is determined to be defective by the determination circuit, the power from the power feeding unit is If a switching element that cuts off the supply of power is further provided, an integrated circuit that is determined to be defective as a result of the above pass / fail determination is electrically connected to another normal integrated circuit through on / off of the switching element. Can be separated.

  That is, in a state in which a plurality of integrated circuits formed on the semiconductor wafer are inspected, the power feeding portions of the plurality of integrated circuits are electrically connected to each other through the power feeding wiring. For this reason, when any one of the integrated circuits is short-circuited, the voltage applied to each power supply unit of these integrated circuits also becomes unstable, making it difficult to inspect each integrated circuit on the semiconductor wafer. In this regard, in the above method, when an integrated circuit failure is determined, each integrated circuit on the semiconductor wafer can be stably separated by electrically separating the integrated circuit from other normal integrated circuits. It becomes possible to inspect.

  Further, such an inspection method is practically adopted when each integrated circuit is formed of a sensor processing circuit formed through a CMOS process, as in the invention described in claim 9. More desirable. In other words, such a circuit is usually a relatively small circuit, and it is possible to sufficiently determine its quality even with a simple inspection. In addition, a fine circuit formed through a CMOS process is likely to have an initial failure and is highly inspected. For this reason, it is more desirable to employ the method in which the inspection is basically performed through the power supply terminal and the power supply wiring when the integrated circuit to be inspected is such a circuit.

  On the other hand, in the semiconductor integrated circuit according to claim 10, the voltage applied to the power supply terminal is set to a constant voltage that makes the voltage constant to two kinds of voltages, that is, an operating voltage of the integrated circuit and a test voltage higher than the operating voltage. A constant voltage means having a mode, and a constant voltage mode by the constant voltage means by judging whether the voltage applied to the power supply terminal is the voltage to be the operating voltage or the test voltage And a control circuit for switching and controlling. With such a configuration, even a semiconductor integrated circuit including constant voltage means can be accurately inspected using the above-described inspection method for a semiconductor integrated circuit.

  Further, in the semiconductor integrated circuit according to claim 10, as described in the invention according to claim 11, the semiconductor integrated circuit described above is further provided with a determination circuit that determines an operation result of the circuit based on the test voltage. In the inspection using the circuit inspection method, the semiconductor integrated circuit itself can self-determine whether or not the result of the energization test is good.

  Further, in the semiconductor integrated circuit according to claim 11, as in the invention according to claim 12, a switching element for switching on / off of energization is provided on the power supply line from the power supply terminal to the constant voltage means. If further provided, it is possible to electrically separate the integrated circuit determined to be defective as a result of the inspection using the above-described semiconductor integrated circuit inspection method from other normal integrated circuits.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit inspection method according to the present invention and an embodiment of a semiconductor integrated circuit used for carrying out the inspection method will be described below in detail with reference to FIGS. Even in the semiconductor integrated circuit inspection method according to this embodiment, as shown in FIG. 1, whether or not an initial failure has occurred for each of the plurality of integrated circuits 12 formed on the semiconductor wafer 11. An energization test (burn-in test) is performed to inspect the above. After the burn-in test is completed, the quality of each integrated circuit 12 is determined. However, in the method according to this embodiment, prior to such tests and determinations, the power supply pad (power supply terminal) 13 and the power supply that electrically connects the power supply pad 13 and the power supply units of the plurality of integrated circuits 12 are connected. The wiring 14 is formed and laid in advance in a region (scribe region) where the plurality of integrated circuits 12 are not formed on the semiconductor wafer 11.

  In such a method, basically, the power supply pad 13 and the power supply wiring 14 are simply laid and formed in advance in the scribe region on the semiconductor wafer 11, and the plurality of the power supply pads 13 and the power supply wiring 14 can be used. A burn-in test can be performed on the integrated circuit 12. For example, a probe for energization is brought into contact with a power pad 13a (power terminal) and a ground pad 13b (ground terminal) constituting the power supply pad 13, and a voltage is applied between the pads 13a and 13b through the probe. . As a result, a burn-in test is performed on the plurality of integrated circuits 12 through the power supply wiring 14.

  In addition, in this embodiment, the formation of the power supply pad 13 and the laying of the power supply wiring 14 are performed in the same process as the formation of the wiring pattern in each integrated circuit 12 on the semiconductor wafer 11. . For this reason, the power supply pad 13 and the power supply wiring 14 that are used only when the inspection is performed can be performed only by performing the original manufacturing process as usual, that is, without adding any new process to the original manufacturing process. It can be formed in advance on the semiconductor wafer 11.

  Further, in this embodiment, the power supply pad 13a and the ground pad 13b constituting the power supply pad 13 are formed so as to face each other at the edge on the semiconductor wafer 11, and the power supply wiring 14 is formed in the semiconductor in the dicing process. The wafer 11 is laid along a cutting line SL when the wafer 11 is cut into the integrated circuit 12 units. For this reason, most of the power supply pad 13 and the power supply wiring 14 are naturally removed in the dicing process, and after this, without adding any new process to the original manufacturing process. Most of the power supply pad 13 and the power supply wiring 14 that are no longer required can be removed. Although a part of the power supply pad 13 and the power supply wiring 14 remain without being removed in the dicing process, the power supply pad 13 and the power supply wiring 14 are both formed and laid in the scribe region, so that they remain. The influence on the integrated circuit 12 due to this is negligible.

  By the way, each integrated circuit 12 on the semiconductor wafer 11 to be inspected in this embodiment includes a sensor processing circuit formed through a CMOS process, more specifically, a movable part having a structure supported by a beam. For example, it is configured as a processing circuit that processes a detection signal by a semiconductor dynamic quantity sensor that detects a dynamic quantity such as acceleration or angular velocity.

  That is, as shown in FIG. 2, the general configuration of such a semiconductor integrated circuit 12 includes a power supply terminal T1 and a grounding terminal T2 that constitute the power feeding unit. And an output terminal T3 from which a signal processed by the circuit 12 is extracted. Among these, the power supply and grounding terminals T1 and T2 are a reference voltage generating circuit 21 that converts the voltage applied between the terminals T1 and T2 to a reference voltage that is a predetermined constant voltage, and the reference voltage. Each of them is electrically connected to a constant voltage circuit 22 that generates an arbitrary constant voltage “+ V” (for example, “5V”) by amplifying a reference voltage by the generation circuit 21. In the semiconductor integrated circuit 12, power is supplied to each element or circuit that processes the detection signal from the semiconductor dynamic quantity sensor based on the constant voltage “+ V” from the constant voltage circuit 22. In this embodiment, the reference voltage generating circuit 21 and the constant voltage circuit 22 constitute constant voltage means.

On the other hand, the detection signal from the semiconductor dynamic quantity sensor is taken into the C (capacitance) -V (voltage) conversion circuit 23 via the detection terminal T4 in the semiconductor integrated circuit 12.
That is, FIG. 3 shows the circuit 100 as an equivalent circuit of the semiconductor dynamic quantity sensor and the circuit configurations of the CV conversion circuit 23, respectively. The conversion circuit 23 is provided as a separate chip. In the circuit 100 constituting the semiconductor mechanical quantity sensor, the displacement of the movable portion of the structure supported by the beam accompanying the change in the mechanical quantity such as acceleration and angular velocity is detected as the change in the capacitances CS1 and CS2. . Such changes in the capacitances CS1 and CS2 are taken out from the terminal P0 as the detection signal and taken into the CV conversion circuit 23 through the detection terminal T4. In this circuit 100, between the terminals P1 and P2, there is an alternating signal (voltage) having a frequency of, for example, 50 kHz to 150 kHz and alternating in a phase opposite to each other between the voltage “0” V and the voltage Vcc. Applied constantly.

  In contrast to the circuit 100 configured as described above, the CV conversion circuit 23 includes an operational amplifier OP and a switched capacitor circuit including a capacitor Cf and a switch SW connected in parallel to the feedback path of the operational amplifier OP. It is configured as. A detection signal from the semiconductor dynamic quantity sensor is input to the operational amplifier OP at its inverting input terminal, and a voltage half the voltage Vcc applied between the terminals P1 and P2 of the circuit 100 is input to the non-inverting input terminal. That is, a voltage of “Vcc / 2” is applied. In the CV conversion circuit 23, the switch SW is controlled to be ON (ON) / OFF (OFF) in synchronization with the alternating cycle of each alternating signal (voltage). Further, a constant voltage “+ V” by the constant voltage circuit 22 is used as a power source for the operational amplifier OP.

  With such a configuration, detection signals from the semiconductor dynamic quantity sensor, that is, changes in the capacitances CS1 and CS2 are converted into voltage values by the CV conversion circuit 23, and dynamic quantities such as acceleration and angular velocity are converted. A voltage signal corresponding to the change is obtained. The voltage signal is sequentially taken into the filter circuit 24 configured as a switched capacitor filter and further to the amplifier circuit 25 in the semiconductor integrated circuit 12 shown in FIG. That is, the switching frequency component of the switch SW is mainly removed and amplified by the amplifier circuit 25. The amplified signal by the amplifier circuit 25 is taken into an A / D conversion circuit 26 that performs A (analog) / D (digital) conversion, and converted into a parallel digital signal. This digital signal is further taken into a digital processing circuit 27 that performs parallel / serial conversion, and converted into serial data in accordance with a predetermined communication protocol. The serial data converted in the digital processing circuit 27 is taken out from the output terminal T3 through the communication buffer 28, and taken in, for example, a central processing unit (CPU) or the like and processed appropriately.

  In the semiconductor integrated circuit 12, the constant voltage “+ V” from the constant voltage circuit 22 is applied to the circuits 24 to 27 including the CV conversion circuit 23. The switching frequency of the switches provided in the CV conversion circuit 23 and the filter circuit 24 is controlled by the control circuit 30. In the semiconductor integrated circuit 12, the operational amplifier OP (FIG. 3) of the CV conversion circuit 23 and the amplifier circuit 25 are connected through a memory circuit (storage means) 31 formed of a nonvolatile memory (EPROM). Adjustment of output offset, temperature characteristics, and the like of an operational amplifier (not shown) to be configured is achieved. Further, the semiconductor integrated circuit 12 is provided with a booster circuit 32 that applies a high voltage to the memory circuit 31 when data is written to the memory circuit 31.

  Here, as described above, the integrated circuit 12 to be inspected in this embodiment includes the reference voltage generation circuit 21 and the constant voltage circuit 22 that constitute constant voltage means. For this reason, it is difficult to perform a burn-in test on the integrated circuit 12 as it is.

  That is, in the method for inspecting a semiconductor integrated circuit according to this embodiment, as described above, in a state where a plurality of integrated circuits 12 are formed on the semiconductor wafer 11, the power supply pads 13 and A burn-in test is performed through the power supply wiring 14. In this burn-in test, a voltage (high load) higher than the operating voltage of the integrated circuit 12 is usually applied. However, when each integrated circuit 12 to be inspected includes a reference voltage generating circuit 21 and a constant voltage circuit 22 that constitute constant voltage means, the voltage is applied between the power supply terminal T1 and the ground terminal T2. The constant voltage circuit 22 also makes the constant voltage to be a constant voltage “+ V”. For this reason, it becomes difficult to apply a voltage higher than the operating voltage (for example, “5 V”) to the semiconductor integrated circuit 12, that is, the circuits 23 to 27 that process the detection signals from the semiconductor dynamic quantity sensor.

  Therefore, in this embodiment, the voltage applied between the power supply terminal T1 and the grounding terminal T2 is set to the operating voltage (for example, “5 V”) of the integrated circuit 12 and a test voltage higher than the operating voltage ( For example, the constant voltage circuit 22 is provided with a constant voltage mode in which constant voltages are set to two types of voltages such as “7 V”. Further, each integrated circuit 12 on the semiconductor wafer 11 has a voltage applied between the power supply terminal T1 and the ground terminal T2 as the operating voltage or the test voltage. It is further provided with a burn-in control circuit 33 which is a control circuit for determining whether or not there is and controlling to switch the constant voltage mode by the constant voltage circuit 22. Thus, even if each integrated circuit 12 on the semiconductor wafer 11 to be inspected includes the reference voltage generation circuit 21 and the constant voltage circuit 22 that constitute the constant voltage means, the constant voltage generation mode by the burn-in control circuit 33 is achieved. A high voltage can be applied to the integrated circuit 12 through the switching control. The switching of the constant voltage mode by the constant voltage circuit 22 is realized, for example, by adjusting the amplification factor when the constant voltage circuit 22 amplifies the reference voltage by the reference voltage generation circuit 21.

  FIG. 4 is a block diagram showing an outline of the internal configuration of the burn-in control circuit 33. Next, referring to FIG. 4, the configuration of the burn-in control circuit 33 and the constant voltage generation by the burn-in control circuit 33 are shown. Mode switching control will be described.

  As shown in FIG. 4, the burn-in control circuit 33 has a voltage to be applied between the power supply terminal T1 and the ground terminal T2 as an operating voltage or a voltage to be used as a test voltage. The control signal generation circuit 33a that selects one of the two constant voltage conversion modes is determined.

  In other words, in this burn-in control circuit 33, the control signal generation circuit 33a uses a different reference voltage for the voltage applied between the power supply terminal T1 and the ground terminal T2, that is, the voltage applied to the power feeding section. The two comparators 33b and 33c to be binarized are electrically connected to each other.

  Here, the first comparator 33b takes in the voltage applied between the power supply terminals T1 and T2 as a divided value by the resistors R1 and R2 and R3, and takes this as the first reference voltage Vth1. (For example, “8V”) is binarized. On the other hand, the second comparator 33c takes in the voltage applied between the power supply terminals T1 and T2 as a divided value by the resistors R1 and R2 and the resistor R3, and takes this as a second reference voltage Vth2 ( For example, binarization is performed based on “7V”). A constant voltage generated by the reference voltage generation circuit 21 (FIG. 2) is used for the first reference voltage Vth1 and the second reference voltage Vth2.

  With such a configuration, when a DC voltage from, for example, a battery mounted on the vehicle is applied to the power feeding unit, the two comparators 33b, 33b, from the relationship between the magnitude of the DC voltage and the reference voltages Vth1 and Vth2 Each binarized signal generated at 33c is maintained or fixed at “0” or “1”. The control signal generation circuit 33a thus takes in each of the two binarized signals that are binarized separately, and selects one of the two constant voltage modes based on the mutual change pattern of these binarized signals. select. That is, here, a constant voltage mode for selecting a constant voltage to the operating voltage is selected based on a change pattern in which each binarized signal does not change.

  On the other hand, when a burn-in test is performed on the plurality of integrated circuits 12 (FIG. 1), a voltage signal modulated in a predetermined manner as illustrated in FIG. 4 is applied to the power supply pad 13 (FIG. 1). Is applied. Thereby, this voltage signal is applied to each power supply section of the plurality of integrated circuits 12 through the power supply wiring 14 (FIG. 1). After that, the same voltage signal is taken into the burn-in control circuit 33 and demodulated into the respective binary signals that change in the patterns illustrated in FIG. 4 by the two comparators 33b and 33c. Become. That is, in this embodiment, the voltage signal is demodulated into a mode signal indicating a constant voltage mode of the test voltage in the comparator 33b and a clock signal in the comparator 33c. For this reason, the control signal generation circuit 33a takes in each of these signals, and here selects the constant voltage mode of the test voltage based on the change pattern of the mode signal with respect to the clock signal. Then, the control signal generation circuit 33a outputs a control signal to the constant voltage circuit 22 based on this selection, whereby the constant voltage mode switching control by the burn-in control circuit 33 is executed.

  After the burn-in test is performed, the quality of each integrated circuit 12 on the semiconductor wafer 11 is determined. The burn-in control circuit 33 performs the burn-in test based on the frequency of the demodulated clock signal. And a period during which pass / fail judgment is performed are automatically switched every predetermined period. In addition, each integrated circuit 12 on the semiconductor wafer 11 further includes a burn-in determination circuit (determination means) 34 that self-determines the quality of the integrated circuit 12 according to the result of the burn-in test. Self-determination is executed for each integrated circuit 12.

  Therefore, in the semiconductor integrated circuit inspection method according to this embodiment, the modulated voltage signal is simply applied to the power supply pad 13 (FIG. 1) on the semiconductor wafer 11 using the energization probe or the like. In addition to the burn-in test for each integrated circuit 12 on the semiconductor wafer 11, it is possible to determine the quality. Note that the burn-in determination circuit 34 can be configured by a simple logic circuit.

  In this embodiment, each integrated circuit 12 on the semiconductor wafer 11 controls the power supplied to the constant voltage circuit 22 via the power supply terminal T1, as shown in FIG. For example, a switching element 35 composed of a P-type MOS transistor or the like is provided. For this reason, when the defect of the semiconductor integrated circuit 12 is determined as a result of the self-determination, the switching element 35 is controlled to be in an off state, whereby the constant voltage circuit 22 applies to each element or circuit. Power supply can be stopped.

  That is, as shown in FIG. 1, in a state in which each integrated circuit 12 on the semiconductor wafer 11 is inspected, the power feeding units of the plurality of integrated circuits 12 are electrically connected to each other through the power feeding wiring 14. It is connected. For this reason, when any one of the integrated circuits 12 is short-circuited, the voltage applied to each power supply unit of these integrated circuits 12, that is, the modulated voltage signal becomes unstable, and each of the integrated circuit 12 on the semiconductor wafer 11 is unstable. It becomes difficult to inspect the integrated circuit 12. In this regard, in the above configuration, the switching element 35 included in the integrated circuit 12 determined to be defective is controlled to be in an off state, and the integrated circuit 12 determined to be defective is electrically separated from other normal integrated circuits 12. As a result, the other integrated circuits 12 on the semiconductor wafer 11 can be inspected stably.

  Here, FIG. 5 shows an example of an inspection mode (inspection procedure) of the semiconductor integrated circuit 12 by the burn-in control circuit 33 and the burn-in determination circuit 34 as a time chart. Hereinafter, an example of an inspection mode (inspection procedure) of the semiconductor integrated circuit 12 will be described with reference to FIG.

  As shown in FIG. 5, if a modulated voltage signal is applied between the power supply terminal T1 and the grounding terminal T2 at timing t, the burn-in control circuit 33 at this timing t The voltage signal is demodulated. That is, the burn-in control circuit 33 generates a mode signal and a clock signal based on the voltage signal, and a period during which a burn-in test is performed and a period during which pass / fail judgment is performed based on the frequency of the clock signal is a predetermined period. It can be switched alternately every time. During the burn-in test, the above-described constant voltage mode switching control is performed by the burn-in control circuit 33 while the semiconductor integrated circuit 12 is in a high temperature state. Through this control, the burn-in test for the semiconductor integrated circuit 12 is performed. Done.

  On the other hand, in the period during which the pass / fail judgment is performed, the constant voltage by the constant voltage circuit 22 is controlled in a constant voltage mode in which the operation voltage is constant through the constant voltage mode switching control. Also, the burn-in control circuit 33 outputs a pass / fail judgment start signal indicating that the semiconductor integrated circuit 12 is judged pass / fail to the control circuit 30 and the burn-in determination circuit 34. As a result, the control circuit 30 switches the switches provided in the CV conversion circuit 23 and the filter circuit 24 at a predetermined frequency. Then, when the semiconductor integrated circuit 12 is in a state of operating as a detection signal processing circuit by the semiconductor dynamic quantity sensor, the quality determination of the semiconductor integrated circuit 12 is started.

  Specifically, first, as the dark current measurement stage, it is determined whether or not a leak current is generated for each integrated circuit 12 due to, for example, a defect in the semiconductor wafer 11 or the like. Next, as a sensor output measurement stage, for example, when a predetermined offset voltage is applied to the detection terminal T4 (FIGS. 1 and 2), does this offset appear in the digital signal taken into the digital processing circuit 27? It is determined whether or not. Next, as a digital circuit measurement stage, it is determined whether or not the logic circuit constituting the digital processing circuit 27 is correct. In the semiconductor integrated circuit inspection method according to this embodiment, the memory circuit 31 is used, and the determination result is written into the memory circuit 31 each time the quality is determined at each measurement stage. By storing the pass / fail judgment result in the memory circuit 31 in this way, it becomes easy to identify normal or defective for each integrated circuit 12 after the inspection.

  The quality determination result data stored in the memory circuit 31 is read by the burn-in determination circuit 34. As a result, if the burn-in determination circuit 34 recognizes that any one of the three measurement stages has been determined to be defective, the semiconductor integrated circuit 12 is determined to be defective.

  Further, when a failure of the semiconductor integrated circuit 12 is determined, the switching element is used to electrically isolate the semiconductor integrated circuit 12 determined to be defective from other integrated circuits 12 on the semiconductor wafer 11. 35 is turned off. Thereafter, the period during which the burn-in test is performed and the period during which the quality determination is performed are alternately switched, and the above-described burn-in test and quality determination are repeatedly performed.

  On the other hand, as a result of reading the determination result data, if the burn-in determination circuit 34 recognizes that the semiconductor integrated circuit 12 is normal, the switching element 35 is maintained in the ON state. The burn-in test and pass / fail judgment are repeatedly executed.

  As described above, according to the semiconductor integrated circuit inspection method and the semiconductor integrated circuit inspected by this method according to this embodiment, the following excellent effects can be obtained.

  (1) The power supply pad 13 and the power supply wiring 14 are formed in advance in a region (scribe region) excluding the region where the plurality of integrated circuits 12 are formed on the semiconductor wafer 11. Therefore, an energization test (burn-in test) can be performed on the plurality of integrated circuits 12 through the power supply pad 13 and the power supply wiring 14.

  (2) The formation of the power supply pad 13 and the laying of the power supply wiring 14 are performed in the same process as the formation of the wiring pattern in each integrated circuit 12 on the semiconductor wafer 11. Therefore, the plurality of integrated circuits 12 can be inspected more easily.

  (3) The power supply pad 13 is formed on the edge of the semiconductor wafer 11, and the power supply wiring 14 is formed along the cutting line SL when the semiconductor wafer 11 is cut into the integrated circuit 12 in the dicing process. It was laid with. For this reason, most of the power supply pad 13 and the power supply wiring 14 that are no longer necessary after the inspection can be removed in the dicing process. Further, coupled with the effect (1), post-processing after inspection, which has been conventionally required, can be omitted.

  (4) The voltage applied between the power supply terminal T1 and the grounding terminal T2 is made constant to two voltages, that is, an operating voltage of the semiconductor integrated circuit 12 and a test voltage higher than the operating voltage. The constant voltage circuit 22 has a constant voltage mode. Further, each integrated circuit 12 on the semiconductor wafer 11 has a voltage applied between the power supply terminal T1 and the ground terminal T2 as the operating voltage or the test voltage. A burn-in control circuit 33, which is a control circuit for determining whether there is a constant voltage and switching the constant voltage mode by the constant voltage circuit 22, is provided. Thus, even if each integrated circuit 12 on the semiconductor wafer 11 to be inspected includes the reference voltage generation circuit 21 and the constant voltage circuit 22 that constitute the constant voltage means, the constant voltage generation mode by the burn-in control circuit 33 is achieved. A high voltage can be applied to each integrated circuit 12 through the switching control.

  (5) Since each integrated circuit 12 on the semiconductor wafer 11 is further provided with a burn-in determination circuit 34 for determining the quality of the integrated circuit 12, the inspection of the semiconductor integrated circuit 12 is further simplified.

(6) Since the result of self-determination is written in the memory circuit 31, it becomes easy to distinguish between normal and defective for each integrated circuit 12 after the inspection.
(7) Each integrated circuit 12 on the semiconductor wafer 11 is further provided with a switching element 35 for controlling the power supplied to the constant voltage circuit 22 via the power supply terminal T1. For this reason, each integrated circuit 12 on the semiconductor wafer 11 can be inspected more stably.

  (8) Each integrated circuit 12 on the semiconductor wafer 11 is a sensor processing circuit formed through a CMOS process. In other words, such a circuit is usually a relatively small circuit, and it is possible to sufficiently determine its quality even with a simple inspection. In addition, a fine circuit formed through a CMOS process is likely to have an initial failure and is highly inspected. For this reason, the method in which the inspection is basically performed only through the power supply terminal and the power supply wiring is particularly desirable when employed in such a circuit.

In addition, the said embodiment can also be changed and implemented as follows.
Each integrated circuit 12 on the semiconductor wafer 11 may be a circuit including a circuit 100 that is an equivalent circuit of a semiconductor dynamic quantity sensor. In this case, in the sensor output measurement stage, the sensitivity of the detection signal by the circuit 100 can be measured.

-The manufacturing process and application of the semiconductor integrated circuit 12 are not limited.
Each integrated circuit 12 on the semiconductor wafer 11 may not necessarily include a memory circuit 31. In this case, although the effects (6) and (7) cannot be obtained, if the burn-in determination circuit 34 determines that the semiconductor integrated circuit 12 is defective, the switching element 35 is directly turned off. The effect (7) can be obtained.

A fuse or the like may be used instead of the switching element 35.
The switching element 35 and the burn-in determination circuit 34 may be omitted. Even in this case, each integrated circuit 12 on the semiconductor wafer 11 can be burned in through the power supply pad 13 and the power supply wiring 14.

  The configurations of the constant voltage circuit 22 and the burn-in control circuit 33 are not necessarily limited to the configurations described above. The point is that any burn-in test can be performed on each integrated circuit 12 on the semiconductor wafer 11 through the constant voltage mode switching control by the burn-in control circuit 33.

  As each integrated circuit 12 on the semiconductor wafer 11, a configuration in which the constant voltage means and the burn-in control circuit 33 are omitted may be employed. That is, in this case, a voltage higher than the operating voltage of the semiconductor integrated circuit 12 is directly applied to the power supply pad 13. Even in this case, a burn-in test can be performed on the plurality of integrated circuits 12 through the power supply wiring 14.

The top view which shows the semiconductor wafer in which the several integrated circuit used as the test object is formed about one Embodiment of the test | inspection method of the semiconductor integrated circuit concerning this invention. 2 is a block diagram showing a configuration of a semiconductor integrated circuit to be inspected in the embodiment. FIG. The circuit diagram which shows the circuit structure of the equivalent circuit of a semiconductor dynamic quantity sensor, and a CV conversion circuit, respectively. The block diagram which shows the structural example of a burn-in control circuit. The time chart which shows an example of the test | inspection aspect (inspection procedure) of a semiconductor integrated circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Semiconductor wafer, 12 ... Semiconductor integrated circuit, 13 ... Power supply pad, 13a ... Power supply pad, 13b ... Ground pad, 14 ... Power supply wiring, 21 ... Reference voltage generation circuit, 22 ... Constant voltage circuit, 23 ... CV conversion Circuit, 24 ... Filter circuit, 25 ... Amplifier circuit, 26 ... A / D conversion circuit, 27 ... Digital processing circuit, 28 ... Communication buffer, 30 ... Control circuit, 31 ... Memory circuit, 32 ... Booster circuit, 33 ... Burn-in control Circuit 33a... Control signal generation circuit 33b first comparator 33c second comparator 34 burn-in determination circuit 35 switching element 100 circuit equivalent circuit of semiconductor dynamic quantity sensor Cf ... capacitor, OP ... operational amplifier, SW ... switch, T1 ... power supply terminal, T2 ... grounding terminal, T3 ... output terminal, T4 ... detection terminal.

Claims (12)

An inspection method for a semiconductor integrated circuit that performs pass / fail tests on a plurality of integrated circuits formed on a semiconductor wafer to determine whether the plurality of integrated circuits are good or bad,
In a region excluding the region where the plurality of integrated circuits are formed on the semiconductor wafer, a power supply wiring electrically connected to each power supply unit of the plurality of integrated circuits, and a power supply terminal and a ground terminal of the power supply wiring A power supply terminal is preliminarily laid and formed, and a predetermined voltage is applied between the power supply terminal and the ground terminal, thereby conducting an energization test on the plurality of integrated circuits through the power supply wiring. Inspection method of semiconductor integrated circuit. The method for inspecting a semiconductor integrated circuit according to claim 1, wherein the laying of the power supply wiring and the formation of the power supply terminal are performed in the same process as the formation of a wiring pattern in each integrated circuit on the semiconductor wafer. The power supply terminal is formed on an edge of the semiconductor wafer, and the power supply wiring is laid in a shape along a cutting line when the semiconductor wafer is cut into the integrated circuit unit in a dicing process. The method for inspecting a semiconductor integrated circuit according to claim 2. Each of the integrated circuits has a constant voltage unit having a constant voltage mode for making the voltage applied to the power supply section into two kinds of voltages, that is, an operating voltage of the integrated circuit and a test voltage higher than the operating voltage. And a control circuit for switching and controlling the constant voltage mode by the constant voltage means by determining whether the voltage applied to the power supply unit is the voltage to be the operating voltage or the test voltage 4. The energization test for each integrated circuit is executed through constant voltage mode switching control by the control circuit when a voltage to be the test voltage is applied to the power supply terminal. The method for inspecting a semiconductor integrated circuit according to any one of the above. The voltage to be used as the test voltage is modulated in a predetermined manner and applied to the power supply unit of each integrated circuit, and the control circuit demodulates the modulated voltage and applies the voltage applied to the constant voltage means. The method for inspecting a semiconductor integrated circuit according to claim 4, wherein the constant voltage mode is switched and controlled so that the voltage is constant as the test voltage. In the inspection method of the semiconductor integrated circuit according to any one of claims 1 to 5,
Each of the integrated circuits is further provided with a determination circuit that self-determines whether the integrated circuit is good or bad according to the result of the energization test. The semiconductor integrated circuit inspection method according to claim 6, wherein a result of self-determination by the determination circuit is stored in a storage unit included in each integrated circuit. In the inspection method of the semiconductor integrated circuit according to claim 6 or 7,
Each of the integrated circuits is further provided with a switching element that cuts off the supply of electric power from the power feeding unit when the determination circuit determines that the defect is present. The semiconductor integrated circuit according to claim 1, wherein each of the integrated circuits includes a sensor processing circuit formed through a CMOS process, and the conduction test is performed on the sensor processing circuit. Inspection method. Constant voltage means having a constant voltage mode for constant voltage applied to the power supply terminal to two kinds of voltages, that is, an operating voltage of the integrated circuit and a test voltage higher than the operating voltage, and applied to the power supply terminal A semiconductor integrated circuit comprising: a control circuit that determines whether a voltage to be set as the operating voltage or a voltage to be set as the test voltage and switches and controls a constant voltage mode by the constant voltage means. The semiconductor integrated circuit according to claim 10,
A semiconductor integrated circuit, further comprising: a determination circuit that determines an operation result of the circuit based on the test voltage. The semiconductor integrated circuit according to claim 11, wherein
A semiconductor integrated circuit, further comprising: a switching element that switches on / off of energization on a power supply line from the power supply terminal to the constant voltage means.

Images