JP2006019885A - Multi-stage power amplifier circuit, and transmitter, receiver, and transmitter-receiver using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-stage power amplifier circuit suitable for circuit integration, and less reduced in a power supply efficiency and the gain, even when the level of a received RF signal is small. <P>SOLUTION: The multi-stage power amplifier circuit comprises a plurality of stages, and each the stage includes bias circuits (40, 50) for amplification transistors (5, 6). The multi-stage power amplification circuit is provided with a current mirror circuit 120 for totally supplying a bias current to dive the bias circuits 40, 50, and the current adjustment terminal of the bias circuits 40, 50 of the stages is connected to the output terminal of the current mirror circuit 120 via current adjustment resistors 109, 110. Then the current mirror circuit 120 supplies the bias current of the bias circuits 40, 50 of the stages, the current of the amplifier circuit at the final stage is reduced at a small signal level to increase the current of the first stage amplifier circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technology effective when applied to a transceiver such as a wireless LAN or a cellular phone, a receiver such as a TV, CATV, satellite broadcast, satellite communication, etc., and a low noise amplifier circuit and a power amplifier circuit used therefor. .

  As a technique studied by the present inventor, for example, with respect to the conventional technique of a multistage power amplifier circuit, for example, a structure as shown in FIG. 9 can be considered.

  The multistage power amplifier circuit shown in FIG. 9 is a transmission unit for transmitting a modulated radio frequency signal (RF signal) to an access point or another personal computer equipped with the wireless LAN system in a wireless LAN system. An example of the power amplifier circuit used in the final stage is shown. The RF signal frequency input to the multistage power amplifier circuit of FIG. 9 is an RF signal in the 2.4 GHz band, and the power supply voltage is 3.3V.

  9 includes an RF signal input terminal 1, an RF signal output terminal 2, a power supply terminal 3 of the amplifier circuit, a bias power supply terminal 4, amplification transistors 5 and 6, bias resistors 7, 10, a load inductor 8, a coupling capacitor 9, grounding capacitors 11, 12 and 13, an input matching circuit 20, an output matching circuit 30, and bias circuits 40 and 50, and an amplifying transistor 5. And a two-stage amplification power amplifying circuit by the amplifying transistor 6.

  In FIG. 9, the amplifying transistor 5 which is the first amplifying stage has its emitter grounded, the base connected to the RF signal input terminal 1 via the input matching circuit 20, and the bias circuit 40 via the biasing resistor 7. The collector is connected to the power supply terminal 3 via the load inductor 8.

  Further, the amplification transistor 6 which is the final amplification stage has its emitter grounded, the base is connected to the collector of the previous amplification transistor 5 via the coupling capacitor 9, and the bias circuit 50 is connected via the bias resistor 10. The collector is connected to the RF signal output terminal 2 and the power supply terminal 3 via the output matching circuit 30.

  The bias circuit 40 includes bias transistors 43, 44, 45 and current adjustment resistors 41, 42. The base of the bias transistor 43 whose emitter is grounded is connected to the emitter of the bias transistor 44, The collector is connected to the base of the bias transistor 44, connected to the bias power supply terminal 4 via the current adjustment resistors 42 and 41, and the base of the bias transistor 45 is connected to the connection point of the current adjustment resistors 41 and 42. To do.

  The collector of the bias transistor 44 and the collector of the bias transistor 45 are connected to the bias power supply terminal 4, and the emitter of the bias transistor 45 supplies a bias current to the base of the amplifying transistor 5 via the bias resistor 7. To do.

  The bias circuit 50 including the bias transistors 53, 54, and 55 and the current adjustment resistors 51 and 52 has the same configuration as the bias circuit 40, and the amplifier transistor 6 is connected via the bias resistor 10. Supply bias current to the base.

  Further, the input matching circuit 20 includes capacitors 21 and 22 and an inductor 23, and performs impedance matching between the base of the amplifying transistor 5 and the RF signal source impedance. The output matching circuit 30 includes inductors 31 and 33, The capacitor 32 has a function of matching the impedance between the collector of the amplifying transistor 6 and the load impedance, and also serves to supply the voltage of the power supply terminal 3 to the collector of the amplifying transistor 5.

  The above multistage power amplifier circuit amplifies the 2.4 GHz band RF signal input to the RF signal input terminal 1 by the amplifying transistor 5, and the amplified RF signal by the amplifying transistor 6 through the coupling capacitor 9. Further amplified and output to the RF signal output terminal 2.

  At this time, in the bias circuit 40 that supplies a bias current to the amplifying transistor 5, the current flowing through the amplifying transistor 5 can be adjusted by appropriately selecting the resistance values of the current adjusting resistors 41 and 42, and the temperature Changes in the bias current due to changes in the base of the amplifying transistor 5 and the collector-to-collector voltage VBE due to the change are the current mirror circuit composed of the bias transistors 43 and 44 of the bias circuit 40 and the base of the emitter follower circuit of the bias transistor 45. The temperature dependence of the collector current of the amplifying transistor 5 is suppressed by canceling out the fluctuation due to the temperature change of the collector-to-collector voltage (for example, see Non-Patent Document 1). Further, the current mirror circuit and the amplifying transistor are connected via a buffer by an emitter follower circuit, so that the drive capability at the time of high output in the power amplifying circuit is not short.

  The collector current flowing through the amplifying transistor 5 is adjusted by the values of the current adjusting resistors 41 and 42, and the connection between the base of the amplifying transistor 5 and the bias circuit 40 is biased via the bias resistor 7. A reduction in gain due to the influence of the impedance of the circuit 40 is suppressed, and the RF signal input to the base of the amplifying transistor 5 leaks into the bias circuit 40 through the bias resistor 7, thereby causing distortion in the bias transistor 45. It is suppressed that the distortion characteristics of the amplifying transistor 5 are deteriorated.

The above is the description of the operation of the bias circuit 40 of the first amplification stage, but the final stage constituted by the bias circuit 50, the bias resistor 10, and the amplification transistor 6 has the same configuration, and its operation is also the same. This is the same and will not be described.
The Institute of Electronics, Information and Communication Engineers IEICE Technical Report "Efficiency improvement method using distortion cancellation in 2-stage power amplifier HBT MMIC for W-CDMA", ED2001-207, FIG.

  By the way, in the multistage power amplifier circuit shown in the above prior art, since the final stage further amplifies the amplified RF signal of the first stage, it is necessary to use a transistor having a higher output than the first stage. Compared to a transistor, it is necessary to increase the transistor size and the collector current. Further, in order to secure a desired power gain and maximum output power, it is necessary to pass a certain amount of current flowing through each amplification stage even if the input RF signal is a small signal level.

  For this reason, when the input RF signal is a small signal level, the output RF signal level is also small, so that the power efficiency expressed by the ratio of the power consumption to the output signal power is deteriorated. When the power amplifier circuit is used in a power amplifier circuit of a transmitter of a mobile phone or a power amplifier circuit of a transmitter of a wireless LAN system mounted on a notebook personal computer, the power efficiency of the power amplifier circuit deteriorates. Since consumption increases, it has the subject that use time will become short.

  Also, if a part of the output power of the multistage power amplifier circuit is detected by the detector circuit, the output level from the power amplifier circuit can be known. If the output level is low, the power supply efficiency can be reduced by reducing the bias current of the amplifying transistor. A means for improving the above is also conceivable. However, if the current flowing through the amplifying transistor is reduced when the input RF signal is at a small signal level, there is a problem that the power gain is lowered.

  In the power amplifier circuit shown in the above prior art, for example, in the case of the first stage, in order to reduce distortion deterioration due to distortion occurring in the bias transistor 45 due to leakage of the input RF signal into the bias circuit 40. The resistance value of the bias resistor 7 may be increased. However, when a strong RF signal is input such that the base and emitter of the amplifying transistor are turned on as a diode, the average value of the voltage VBE between the base and emitter of the amplifying transistor decreases, and the base current is reduced. For example, in the conventional technology of the power amplifier circuit shown in FIG. 9, the voltage drop due to the bias resistor 7 becomes larger and the supply of the bias current to the amplifying transistor becomes insufficient, so that the input / output characteristics deteriorate. However, sufficient output power cannot be obtained.

  For this reason, if an inductor having a large impedance with respect to the RF signal is used instead of the bias resistor 7, the voltage drop due to the inductor is eliminated, and the input / output characteristics are improved. However, considering the integration of the power amplifier circuit, the chip area of the inductor portion becomes very large, and thus there is a problem that it is difficult to integrate the power amplifier circuit using the inductor.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a multistage power amplifier circuit that is less likely to reduce power supply efficiency and gain even when an input RF signal has a small signal level and is suitable for integration.

  In order to achieve the above-mentioned object, the present invention provides means for solving the above-mentioned problems of power supply efficiency deterioration and gain reduction at the time of small signal level input, and the above-mentioned problem of multi-stage power amplifier circuit suitable for integration. As means for obtaining, it has the following characteristics. Here, in order to make the characteristics of the present invention easier to understand, the description will be made in comparison with the multistage power amplifier circuit shown in the prior art of FIG.

  In the present invention, the first means for solving the power supply efficiency deterioration and gain reduction at the time of inputting a small signal level, which is the above-mentioned problem, is a PNP for the multistage power amplifier circuit shown in the prior art of FIG. A current mirror circuit composed of a transistor of a type is newly provided, and the bias current output of this PNP type current mirror circuit is passed through the current adjusting resistors (41, 51) of the bias circuit (40, 50) of each amplification stage. Thus, a bias current is supplied to the bias circuit of each amplification stage.

  With the above configuration, the current flows through the amplifying transistors (5, 6) corresponding to the currents flowing through the current adjusting resistors (41, 51) of the bias circuits (40, 50) of the respective amplifying stages. Since the current can be adjusted, the distribution of the current flowing through the first and last stage amplifying transistors can be adjusted by the resistance value of the current adjusting resistor, and the bias current output from the PNP current mirror circuit By adjusting the current, the current flowing through the entire amplification transistor at each stage can be adjusted. Furthermore, when the distribution of the current flowing through the first and last stage amplifying transistors is small, the current flowing through the first stage amplifying transistor is larger and the current flowing through the last stage amplifying transistor is smaller than when the signal is large. The value of the current adjusting resistor was adjusted.

  Next, the operation of the above configuration will be described. When a two-stage amplifier circuit is considered as an example of a general multi-stage power amplifier circuit, if the signal output from the amplifier circuit is to be as large as possible, the final stage amplification transistor is the first stage amplified RF signal. Therefore, it is necessary to increase the size of the final stage amplifying transistor as compared with the first stage amplifying transistor and to increase the collector current. For this reason, the power consumption efficiency is generally worse in the final stage, which consumes more current than in the first stage, and this contributes to the deterioration of the power efficiency when a small signal level is input. Therefore, when the input RF signal is at a small signal level, it is possible to prevent the power supply efficiency from being lowered by narrowing the current of the amplifier circuit at the final stage to such an extent that the distortion characteristic does not deteriorate. The power gain is reduced by reducing the current of the amplifying transistor in the stage. For this reason, when the signal is small, the current flowing through the amplification transistor at the final stage is reduced and the current flowing through the amplification transistor at the first stage is increased, thereby reducing the gain of the amplification transistor at the final stage. The increase in gain due to the increase in current can suppress the decrease in gain at the small signal level. Furthermore, at the time of a small signal level, the current is increased by increasing the current of the first stage amplifier circuit with good power supply efficiency, and the gain is reduced by reducing the current of the last stage amplifier circuit with poor power supply efficiency. Compared with the amplifier circuit shown in (5), the power supply efficiency of the entire multistage power amplifier circuit can be improved.

  Further, when the input RF signal is at a large signal level, the current flowing through the final stage amplification transistor increases as the RF signal power output from the multistage power amplification circuit increases. 51), the current from the PNP-type current mirror circuit flowing to the final stage bias circuit (50) via 51) increases, and accordingly, the current from the PNP-type current mirror circuit is a constant current. The current flowing from the current mirror circuit to the first stage bias circuit (40) via the current adjustment resistor (41) decreases, and the current flowing to the first stage amplification transistor decreases. Therefore, when the input RF signal is at a large signal level, the current flowing through the final stage amplification transistor is large, and the current flowing through the first stage amplification transistor is small. Thus, the multistage power shown in the prior art of FIG. The operation is the same as that of the amplifier circuit.

  The first means for obtaining the multi-stage power amplifier circuit suitable for integration, which is the above-mentioned problem, is the first means for solving the power supply efficiency deterioration and gain reduction at the time of inputting the small signal level described above. , A current mirror circuit composed of PNP transistors is a multi-output type current mirror circuit, and each bias current output from the current mirror circuit is compared with the multistage power amplifier circuit shown in the prior art of FIG. A bias current is separately supplied to the bias circuit of each amplification stage via the current adjustment resistors (41, 51).

  With the above configuration, since the PNP current mirror circuit is a multi-output type, current can be separately supplied to the bias circuit of each amplification stage. It is possible to change the distribution of current flowing through the amplifier circuit. As a result, when a multi-stage power amplifier circuit including a PNP-type current mirror circuit is to be integrated, if the PNP-type current mirror circuit is not a multi-output type, in order to adjust the current flowing through the amplification transistor at each stage The current adjusting resistors (41, 51) need to be externally attached to the multistage power amplifier circuit shown in the prior art of FIG. 9, but if the above-described means is used, the current adjusting resistors are included. Can be integrated.

  Next, a second means for obtaining a multistage power amplifier circuit suitable for integration, which is the above problem, is the first stage bias circuit (40) with respect to the multistage power amplifier circuit shown in the prior art of FIG. The bias current from the emitter of the biasing transistor (45) is supplied to the base of the amplifying transistor (5) via a biasing inductor of a size that can be integrated with the biasing resistor, and the biasing transistor emitter Was grounded by a series connection body consisting of a capacitor and a resistor. The final stage bias circuit (50) has the same configuration.

  With the above configuration, for example, in the first stage, the emitter of the biasing transistor (45) is grounded by a series connection of a capacitor and a resistor, so that the RF signal input to the base of the amplifying transistor (5) can be obtained. Since leakage to the bias circuit is suppressed, deterioration of the distortion characteristics of the amplifying transistor due to distortion in the bias circuit can be suppressed. For this reason, even if the value of the bias inductor is reduced, the effect of deterioration of the distortion characteristics is small. Therefore, when the power amplifier circuit is integrated, the chip area can be further reduced.

  Further, in the first means for solving the power supply efficiency deterioration and the gain reduction at the time of the small signal level input, the PNP type current mirror circuit is configured to use a P channel type field effect transistor.

  With the above configuration, when an attempt is made to integrate a power amplifier circuit including a PNP-type current mirror circuit, the chip area can be reduced as compared with the case where a PNP transistor is used.

  According to the present invention, a reduction in power supply efficiency when an input RF signal is at a small signal level is small, and a multistage power amplifier circuit excellent in integration can be obtained, and this can be used for a transmitter, a receiver, and a transceiver. By using it, the power consumption and size of these devices can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram showing a first embodiment of a multistage power amplifier circuit according to the present invention. An example of the configuration and operation of the multistage power amplifier circuit according to the first embodiment will be described with reference to FIG.

  As shown in FIG. 1, the multistage power amplifier circuit according to the first embodiment includes an RF signal input terminal 1, an RF signal output terminal 2, an amplifier circuit power supply terminal 3, a bias power supply terminal 4, and amplification transistors 5 and 6. , Load inductor 8, coupling capacitor 9, grounding capacitors 11, 12, 13, input matching circuit 20, output matching circuit 30, bias circuits 40, 50, grounding capacitors 101, 105, grounding resistors 102, 106 , Bias inductors 103 and 107, bias resistors 104 and 108, current adjustment resistors 109 and 110, a current mirror circuit 120 using a PNP transistor, and the like.

  The current mirror circuit 120 includes PNP transistors 121 and 122 and current adjustment resistors 123, 124 and 125. The emitters of the PNP transistors 121 and 122 are connected to the bias power supply terminal 4 through current adjusting resistors 123 and 124, respectively, and the bases of the PNP transistors 121 and 122 are connected to the collector of the PNP transistor 122 in common. The current adjusting resistor 125 is grounded. The collector of the PNP transistor 121 is connected to the base of the bias transistor 45 and the current adjustment resistor 42, the base of the bias transistor 55, and the current adjustment resistor 52 via the current adjustment resistors 109 and 110, respectively. Connected to the connection point.

  In this current mirror circuit 120, the collector of the PNP transistor 121 serves as an output terminal for supplying a bias current to the bias circuits 40 and 50. In the bias circuits 40 and 50, the bases of the bias transistors 45 and 55 serve as current adjustment terminals for adjusting the current flowing through the amplification transistors 5 and 6, and the emitters of the bias transistors 45 and 55 are used for amplification. This is a terminal for supplying a bias current to the transistors 5 and 6.

  Other parts corresponding to those in FIG. 9 are given the same reference numerals and description thereof is omitted.

  In FIG. 1, in the multistage power amplifier circuit of the first embodiment, the RF signal input to the RF signal input terminal 1 is amplified by the amplification transistor 5 and the amplification transistor 6 via the input matching circuit 20, The signal is output from the RF signal output terminal 2 via the output matching circuit 30.

  The current flowing in each amplification stage can be adjusted in accordance with the current flowing in the current adjustment resistors 109 and 110, so that the current flowing in the amplification transistors 5 and 6 in each amplification stage can be adjusted. The distribution of the current flowing through the first-stage and final-stage amplification transistors 5 and 6 is adjusted by the resistance values of the resistors 109 and 110, and the resistance values of the current adjustment resistors 123, 124, and 125 of the PNP-type current mirror circuit 120 are adjusted. Thus, the current of the entire multistage power amplifier circuit is adjusted.

  Further, when the RF signal inputted to the distribution of the current flowing through the first-stage and final-stage amplification transistors 5 and 6 is at a small signal level compared to when the signal is large, the current flowing through the first-stage amplification transistor 5 is increased. The values of the current adjusting resistors 109 and 110 are adjusted so that the current flowing through the amplifying transistor 6 is reduced.

  By adopting such a configuration, in order to improve the deterioration of the power supply efficiency at the time of inputting a small signal level, the gain reduction due to the reduction of the current flowing in the final stage amplification transistor 6 is reduced in the first stage amplification transistor 5. A gain increase due to an increase in current can suppress a decrease in gain when a small signal level is input. Furthermore, when the small signal level is input, the current of the first stage amplifier circuit with good power supply efficiency is increased and the current of the final stage amplifier circuit with low power supply efficiency is reduced, so the gain at the time of small signal level input is not reduced. In addition, the power supply efficiency of the entire amplifier circuit can be improved.

  Although the above-described first embodiment shows the case of a power amplifier circuit having a two-stage configuration, the input RF signal is similarly at a small signal level even in a multi-stage power amplifier circuit having three or more stages. In this case, a decrease in power supply efficiency at the time of inputting a small signal level can be reduced by increasing the current of the first stage amplification transistor and decreasing the current of the last stage amplification transistor.

  The bias current from the emitter of the bias transistor 45 is supplied to the base of the amplifying transistor 5 via the bias inductor 103 and the bias resistor 104 as bias applying elements, and the emitter of the bias transistor 45 is The grounding resistor 102 as a grounding element and the grounding capacitor 101 are connected in series at a high frequency. Similarly, the bias current from the emitter of the biasing transistor 55 is supplied to the base of the amplifying transistor 6 via the biasing inductor 107 and the biasing resistor 108, and the emitter of the biasing transistor 55 is connected to the grounding resistor. It is grounded at a high frequency by a series connection body of 106 and a grounding capacitor 105.

  With this configuration, the emitters of the bias transistors 45 and 55 of the emitter follower circuit are grounded by a series connection body of a capacitor and a resistor, so that the RF signal input to the bases of the amplifying transistors 5 and 6 is biased. Since leakage into the circuits 40 and 50 is suppressed, deterioration of distortion characteristics can be suppressed even if the values of the bias resistors 104 and 108 and the bias inductors 103 and 107 are reduced, and a power amplifier circuit suitable for integration can be obtained. Obtainable.

  FIG. 2 is a circuit diagram showing a second embodiment of the multistage power amplifier circuit according to the present invention. An example of the configuration and operation of the multistage power amplifier circuit according to the second embodiment will be described with reference to FIG.

  In FIG. 2, reference numerals 200 and 210 denote bias circuits. The bias circuit 200 includes bias transistors 201 and 202. Similarly, the bias circuit 210 includes bias transistors 211 and 212. The portions corresponding to 1 are assigned the same reference numerals and the description thereof is omitted.

  In FIG. 2, the bias circuit 200 connects the base of the biasing transistor 201 whose emitter is grounded to the emitter of the biasing transistor 202, connects the collector of the biasing transistor 201 to the base of the biasing transistor 202, and It is connected to the collector of the PNP transistor 121 via the adjusting resistor 109. Similarly, the bias circuit 210 connects the base of the bias transistor 211 whose emitter is grounded to the emitter of the bias transistor 212, connects the collector of the bias transistor 211 to the base of the bias transistor 212, and adjusts the current. The resistor is connected to the collector of the PNP transistor 121 through the resistor 110.

  Further, the connection point between the base of the bias transistor 201 and the emitter of the bias transistor 202 is connected to the base of the amplifying transistor 5 via the bias inductor 103 and the bias resistor 104, and the grounding resistor 102 and the grounding capacitor are connected. It is grounded by the 101 series connection body. Similarly, the connection point between the base of the biasing transistor 211 and the emitter of the biasing transistor 212 is connected to the base of the amplifying transistor 6 via the biasing inductor 107 and the biasing resistor 108, and the grounding resistor 106 and grounding are connected. It is grounded by the series connection body of the capacitor 105.

  The above configuration is a configuration in which a bias current is supplied to the amplifying transistor 5 and the amplifying transistor 6 without passing through an emitter follower circuit as compared with the first embodiment. In addition to the embodiment, the bias circuit 200, 210 does not use an emitter follower circuit, so that the circuit can be simplified.

  FIG. 3 is a circuit diagram showing a third embodiment of the multistage power amplifier circuit according to the present invention. An example of the configuration and operation of the multistage power amplifier circuit according to the third embodiment will be described with reference to FIG.

  In FIG. 3, reference numeral 300 denotes a multi-output type current mirror circuit composed of PNP type transistors. The current mirror circuit 300 includes PNP type transistors 301, 302, and 303 and current adjustment resistors 304, 305, 306, and 307. The emitters of the PNP transistors 301, 302, and 303 are connected to the bias power supply terminal 4 via current adjusting resistors 304, 305, and 306, respectively, and the bases of the PNP transistors 301, 302, and 303 are connected in common. Commonly connected to the collector and grounded by a current adjustment resistor 307. The collector of the PNP transistor 301 is connected to the connection point between the base of the bias transistor 45 and the current adjustment resistor 42 via the current adjustment resistor 109, and the collector of the PNP transistor 302 is the current adjustment resistor 110. To the connection point between the base of the biasing transistor 55 and the current adjusting resistor 52. In addition, parts corresponding to those in FIG.

  With the above configuration, the same effects as those of the first embodiment can be obtained, and the current flowing through each amplification stage can be adjusted by the current adjustment resistors 304 and 305. When the power amplifier circuit including the bias circuits 40 and 50 and the current mirror circuit 300 is to be integrated, the current adjusting resistors 109 and 110 do not need to be externally provided, so that a configuration that is easier to integrate can be obtained.

  FIG. 4 is a circuit diagram showing a fourth embodiment of the multistage power amplifier circuit according to the present invention. An example of the configuration and operation of the multistage power amplifier circuit according to the fourth embodiment will be described with reference to FIG.

  In FIG. 4, reference numeral 400 denotes a multi-output type current mirror circuit composed of p-channel field effect transistors. The current mirror circuit 400 includes p-channel field effect transistors 401, 402, and 403, and a current adjusting resistor 404. , 405, 406, and 407, and the sources of the p-channel field effect transistors 401, 402, and 403 are connected to the bias power supply terminal 4 through the current adjusting resistors 404, 405, and 406, respectively, and the gates are commonly used. In addition to the connection, it is commonly connected to the drain of the p-channel field effect transistor 403 and grounded by the current adjustment resistor 407.

  The drain of the p-channel field effect transistor 401 is connected to the connection point between the base of the bias transistor 45 and the current adjustment resistor 42 via the current adjustment resistor 109, and the drain of the p-channel field effect transistor 402 is connected. Is connected to the connection point between the base of the biasing transistor 55 and the current adjusting resistor 52 via the current adjusting resistor 110. Other parts corresponding to those in FIG. 3 are given the same reference numerals and description thereof is omitted.

  Compared with the third embodiment shown in FIG. 3, the power amplifier circuit in FIG. 4 uses p-channel field effect transistors 401, 402, and 403 as current mirror circuits of bias circuits composed of PNP transistors. In addition to the same operation and effect as in the third embodiment, the p-channel field effect transistors 401, 402, and 403 are used to integrate the power circuit. In this case, the chip area can be further reduced.

  FIG. 5 is a circuit diagram showing a fifth embodiment of the multistage power amplifier circuit according to the present invention. An example of the configuration and operation of the multistage power amplifier circuit according to the fifth embodiment will be described with reference to FIG.

  In FIG. 5, reference numeral 500 denotes an IC package, and other parts corresponding to those in FIG.

  The multistage power amplifier circuit of FIG. 5 schematically shows a configuration when the multistage power amplifier circuit of the third embodiment shown in FIG. 3 is integrated, and in FIG. 5, 6, a load inductor 8, a coupling capacitor 9, and bias circuits 40 and 50 are integrated on the same semiconductor substrate and enclosed in an IC package 500. Further, the input matching circuit 20, the output matching circuit 30, and the current adjusting resistors 304 and 305 are externally attached.

  With the above configuration, the same effects as those of the first embodiment can be obtained, and the current flowing through each amplification stage can be adjusted by the current adjustment resistors 304 and 305. When an amplifier circuit is to be integrated including the bias circuits 40 and 50 and the current mirror circuit 300, a configuration that is easier to integrate is obtained.

  Next, effects in the embodiment of the present invention will be described with reference to FIGS.

  FIG. 6 shows a comparison of simulation results of input / output characteristics in the first embodiment of the multistage power amplifier circuit of FIG. 1 and the prior art multistage power amplifier circuit of FIG.

  In FIG. 6, the simulation was performed for the power amplification circuit at the final stage of the 2.4 GHz band wireless LAN transmitter, and the input / output characteristics when an RF signal input level of −15 dBm and a power supply voltage of 3.3 V were applied were simulated. The horizontal axis represents the input RF signal level, and the vertical axis represents the output signal level.

  FIG. 7 is a simulation of current consumption with respect to the input RF signal level in the first embodiment of the multistage power amplifier circuit of FIG. 1 and the conventional multistage power amplifier circuit of FIG. is there.

  From the input / output characteristics of FIG. 6, it can be seen that the first embodiment of the multistage power amplifier circuit of FIG. 1 and the conventional multistage power amplifier circuit of FIG. Further, regarding the current consumption with respect to the input signal level in FIG. 7, the input signal level is consumed in the first embodiment of the multistage power amplifier circuit in FIG. 1 when the input signal level can be regarded as a small signal level of, for example, −10 dBm or less. It can be seen that the current is smaller than 20 mA and the power supply efficiency is good.

  Next, a transceiver including a transmitter and a receiver using the multistage power amplifier circuit in the above-described embodiment will be described with reference to FIG.

  FIG. 8 is a block diagram of a transceiver of a 2.4 GHz band wireless LAN system. An example of the configuration and operation of a transceiver using the multistage power amplifier circuit in this embodiment will be described with reference to FIG.

  As shown in FIG. 8, the transceiver according to this embodiment includes a transmission / reception antenna 801, a switching circuit 802, a low noise amplification circuit 803, bandpass filters (BPF) 804, 806, 814, 816, and mixer circuits 805, 813. , A quadrature signal demodulation unit 807, a baseband signal processing unit 808, a control unit 809, a local oscillation circuit 810, a PLL circuit (PLL) 811, a quadrature signal modulation unit 812, a power amplification circuit 815, and the like.

  8 transmits and receives data by alternately switching between transmission and reception using the same frequency band, and the low noise amplifier circuit 803 and the power amplifier circuit 815 in FIG. Any of the multistage power amplifier circuits shown in FIG. 5 is used.

  The case of receiving a 2.4 GHz band RF signal transmitted from a wireless LAN access point or a personal computer equipped with another wireless LAN will be described first with respect to the transceiver in the wireless LAN system of FIG.

  In FIG. 8, the control unit 809 of the baseband signal processing unit 808 switches the switching circuit 802 to the reception side, turns the transmission unit off, and turns the reception unit on.

  The RF signal transmitted from the access point or another personal computer is received from the transmission / reception antenna 801 and input to the low noise amplification circuit 803 via the switching circuit 802. The input RF signal is amplified and input to the mixer circuit 805 via the band pass filter 804. The mixer circuit 805 converts the input RF signal into an intermediate frequency signal having a frequency lower than the RF signal frequency by the local oscillation signal from the transmission / reception local oscillation circuit 810 whose oscillation frequency is controlled by the PLL circuit 811, The signal is input to the orthogonal signal demodulator 807 via the band pass filter 806. In the orthogonal signal demodulator 807, the input intermediate frequency signal is demodulated into an I / Q orthogonal signal, and then demodulated into a baseband data signal by a baseband signal processor 808. The demodulated data signal is stored in a memory of a personal computer or the like on which the transceiver is mounted via an interface.

  Next, a case where a data signal is transmitted from a wireless LAN transceiver to an access point or another personal computer equipped with the wireless LAN will be described.

  In FIG. 8, the control unit 809 of the baseband signal processing unit 808 switches the switching circuit 802 to the transmission side, turns the reception unit off, and turns the transmission unit on.

  The baseband signal processing unit 808 modulates the data signal into an I / Q quadrature signal and inputs it to the quadrature signal modulation unit 812. The input I / Q quadrature signal is modulated and output as an intermediate frequency signal in the quadrature signal modulator 812 and input to the mixer circuit 813. The input intermediate frequency signal is frequency-converted and output to a 2.4 GHz band RF signal by the local oscillation signal from the local oscillation circuit 810 for both transmission and reception whose oscillation frequency is controlled by the PLL circuit 811 in the mixer circuit 813. The signal is input to the power amplifier circuit 815 via the pass filter 814. The power amplifying circuit 815 amplifies the power of the input RF signal and transmits the amplified RF signal through the band-pass filter 816 and the switching circuit 802 using the transmission / reception antenna 801.

  In the transceiver in the wireless LAN system of FIG. 8 described above, an RF signal input by using any of the multistage power amplifier circuits shown in FIGS. 1 to 5 as the low noise amplifier circuit 803 and the power amplifier circuit 815. It is possible to obtain a transceiver having excellent power supply efficiency when the signal level is small. Further, when the low noise amplifier circuit 803 and the power amplifier circuit 815 are integrated, the chip size can be further reduced, so that the IC package can be downsized and a smaller transceiver can be obtained.

  In addition to the transceiver, the multistage power amplifier circuit in this embodiment includes a receiver including a low noise amplifier circuit, a local oscillator circuit, a mixer circuit, an orthogonal signal demodulator, an orthogonal signal modulator, and a local oscillator circuit. The present invention can also be applied to a transmitter including a mixer circuit, a power amplifier circuit, and the like, and in this case, the same effect as that of the transceiver can be obtained.

  The multi-stage power amplifier circuit of the present invention is suitable for transceivers such as wireless LAN and cellular telephone, receivers for TV, CATV, satellite broadcast, satellite communication, etc., and low noise amplifier circuits and power amplifier circuits used for them. Applicable.

1 is a circuit diagram showing a first embodiment of a multistage power amplifier circuit according to the present invention; FIG. It is a circuit diagram which shows 2nd Embodiment of the multistage power amplifier circuit by this invention. It is a circuit diagram which shows 3rd Embodiment of the multistage power amplifier circuit by this invention. It is a circuit diagram which shows 4th Embodiment of the multistage power amplifier circuit by this invention. FIG. 6 is a circuit diagram showing a fifth embodiment of a multistage power amplifier circuit according to the present invention. It is a characteristic view which shows the 1st Embodiment of the multistage power amplifier circuit by this invention, and the simulation result of the input-output characteristic of the multistage power amplifier circuit of a prior art. It is a characteristic view which shows the 1st Embodiment of the multistage power amplifier circuit by this invention, and the simulation result of the consumption current with respect to the input level of the multistage power amplifier circuit of a prior art. It is a block diagram which shows the transmitter / receiver comprised using the multistage power amplifier circuit by this invention. It is a circuit diagram which shows an example of the prior art of a multistage power amplifier circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... RF signal input terminal, 2 ... RF signal output terminal, 3 ... Power supply terminal, 4 ... Bias power supply terminal, 5, 6 ... Amplifying transistor, 7, 10, 104, 108 ... Bias resistance, 8 ... Load inductor, DESCRIPTION OF SYMBOLS 9 ... Coupling capacity, 11, 12, 13, 101, 105 ... Grounding capacity, 20 ... Input matching circuit, 21, 22, 32 ... Capacity, 23, 31, 33 ... Inductor, 30 ... Output matching circuit, 40, 50 , 200, 210... Bias circuit, 41, 42, 51, 52, 109, 110, 123, 124, 125, 304, 305, 306, 307, 404, 405, 406, 407 ... Current adjustment resistors, 43, 44 , 45, 53, 54, 55, 201, 202, 211, 212... Biasing transistor, 102, 106... Grounding resistor, 103, 107. 120, 300, 400 ... current mirror circuit, 121, 122, 301, 302, 303 ... PNP transistor, 401, 402, 403 ... p-channel field effect transistor, 500 ... IC package, 801 ... antenna for transmitting and receiving, 802 ... Switching circuit 803... Low noise amplifier circuit 804 806 814 816 Band pass filter 805 813 Mixer circuit 807 Orthogonal signal demodulator 808 Baseband signal processor 809 Control unit 810 ... Local oscillator circuit, 811 ... PLL circuit, 812 ... Orthogonal signal modulator, 815 ... Power amplifier circuit.

Claims (10)

Each stage includes a bias circuit for amplifying transistors of a plurality of stages of power amplifying circuits, the bias circuit includes a current mirror circuit, and the amplifying transistor from the bias circuit via a bias applying element including a resistor A multistage power amplifier circuit configured to supply a bias current to
A first current mirror circuit that collectively supplies a bias current for driving the bias circuit, the first current mirror circuit having an output terminal that supplies a bias current to the bias circuit; The bias circuit has a current adjustment terminal for adjusting a current flowing through the amplification transistor, and the current adjustment terminal of each stage of the bias circuit is an output terminal of the first current mirror circuit via a current adjustment resistor. A multistage power amplifier circuit, characterized in that the multistage power amplifier circuit is connected. The multistage power amplifier circuit according to claim 1,
The bias circuit at each stage includes the current mirror circuit and an emitter follower circuit, and a bias current output from the current mirror circuit is supplied to the amplification transistor via the emitter follower circuit. Multi-stage power amplifier circuit. The multistage power amplifier circuit according to claim 1 or 2,
A multi-stage power amplifier circuit characterized in that a connection point between a terminal for supplying a bias current from the bias circuit to the amplifying transistor and a bias applying element including the resistor is grounded in a high frequency by a ground element including a capacitor. . The multistage power amplifier circuit according to any one of claims 1 to 3,
The first current mirror circuit is a multi-output type current mirror circuit having a plurality of output terminals for outputting a bias current, and the current adjustment terminals of the bias circuits in the respective stages are respectively connected to the first current mirror circuit through current adjustment resistors. A multistage power amplifier circuit, wherein the multistage power amplifier circuit is connected to different output terminals of one current mirror circuit. The multistage power amplifier circuit according to any one of claims 1 to 4,
The multistage power amplifier circuit, wherein the first current mirror circuit includes a PNP transistor or a p-channel field effect transistor. The multistage power amplifier circuit according to any one of claims 1 to 5,
When the input RF signal is a small signal level, the current mirror is configured so that the current flowing through the first stage amplification transistor is larger and the current flowing through the last stage amplification transistor is smaller than when the input RF signal is a large signal level. A multistage power amplifier circuit characterized in that a bias current supplied from the circuit to the bias circuit of each stage is adjusted. The multistage power amplifier circuit according to any one of claims 1 to 6,
The multistage power amplifier circuit, wherein the amplifying transistor, the bias circuit, and the first current mirror circuit are integrated on the same semiconductor substrate. A low noise amplifier circuit that amplifies and outputs the received RF frequency signal; a reception mixer circuit that converts the RF frequency signal output from the low noise amplifier circuit into an intermediate frequency signal by a local oscillation signal; and the reception A receiver having a demodulation circuit for demodulating the intermediate frequency signal output from the mixer circuit,
The receiver using the multistage power amplifier circuit according to claim 1, wherein the low noise amplifier circuit is used. A transmission mixer circuit that converts an intermediate frequency signal modulated and output in the modulation circuit into an RF frequency signal by a local oscillation signal, and a power amplification circuit that amplifies the RF frequency signal output from the transmission mixer circuit; A transmitter,
The transmitter using the multistage power amplifier circuit according to any one of claims 1 to 7. A low noise amplifier circuit that amplifies and outputs the received RF frequency signal; a reception mixer circuit that converts the RF frequency signal output from the low noise amplifier circuit into an intermediate frequency signal by a local oscillation signal; and the reception A receiver comprising a demodulator that demodulates the intermediate frequency signal output from the mixer circuit;
Transmission consisting of a transmission mixer circuit that converts and outputs an intermediate frequency signal modulated and output in the modulation circuit to an RF frequency signal by a local oscillation signal, and a power amplification circuit that amplifies the RF frequency signal output from the transmission mixer circuit A transmitter / receiver comprising:
8. The transceiver according to claim 1, wherein the low noise amplifier circuit and the power amplifier circuit use the multistage power amplifier circuit according to claim 1.

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