JP4095398B2 - Amplifier and radio communication apparatus using the same - Google Patents

Description

【００３５】
ここで、Ｉ_S はプロセス条件によって決まる定数である。熱電圧Ｖ_{T 、}は素電荷ｑ、ボルツマン定数ｋ及び絶対温度Ｔから、ｋＴ／ｑで決まる値であり、半導体デバイスの特性を決める重要な変数の一つである。常温（摂氏２７℃）の場合、熱電圧Ｖ_T の値は約２６ｍＶである。
【００３６】
ここで、図４に示した構成のバイアス制御回路１２では、利得切替回路１４から端子４１，４２にそれぞれ与えられるバイアス制御信号により、ＭＯＳトランジスタＭ５１，Ｍ５２がオン／オフを行い、これによってトランジスタＱ５１とＱ５２の動作が決まる。この結果、図１においてバイアス制御回路１２から入力段トランジスタＱ１１にベース電圧として与えられるバイアス制御信号の電圧が決定される。
【００３７】
本実施形態では、このバイアス制御回路１４による入力段トランジスタＱ１１のバイアス電流の制御範囲を以下のように設定する。例えば、ＬＮＡにおいて一般的に要求されている３０ｄＢ以上という利得制御幅を実現する場合について考える。この場合、出力信号電流には約３２倍の電流変化幅が必要となる。この電流変化幅を（ａ）の電流振り分けのみで実現する場合、カスコードトランジスタＱ１２とＱ１３，Ｑ１４に、この電流変化幅に見合ったエミッタ面積比のトランジスタを用いることになる。（ａ）の方法のみで利得切り替えを行う従来の技術では、入力インピーダンスの変動を抑制するために入力段トランジスタＱ１１のバイアス電流を一定にする必要から消費電流は一定であり、これによって消費電力が大きくなるという問題点があることは前述の通りである。
【００３８】
一方、低消費電力化のために上記の出力信号電流の電流変化幅をバイアス電流の制御で実現しようとした場合、次のような問題がある。前述の式（２）から、３０ｄＢ以上という利得制御幅を実現するために、入力段トランジスタＱ１１のベース電圧の変化でコレクタ電流に３０倍以上の変化を与えるためには、常温で約９０ｍＶの電圧変動幅が必要となる。ここで簡単のためにエミッタ端の電位は一定と仮定している。
【００３９】
携帯電話機のような民生機器は、ほぼ−４０℃〜８５℃の温度範囲での動作を保証している。この動作保証温度範囲は、常温に対して絶対温度で約３０％の変動幅ということになり、熱電圧Ｖ_T の変動としてみると、約１１ｍＶである。これに比べてベース電圧の変動が約９０ｍＶというのは、非常に大きな値であることが分かる。これだけの電圧変動があると、入力段トランジスタＱ１１が同じ条件で動作しているとみなせなくなり、入力インピーダンスの変動が無視できなくなる。
【００４０】
携帯通信端末のような２ＧＨｚ帯以上の信号を扱う高周波回路では、入力インピーダンスの整合条件が利得などの回路特性に大いに影響する。入力インピーダンスが変化して整合条件が悪化すると、反射により定在波が立つおそれがあり、回路の発振を引き起こすこともある。従って、バイアス制御回路１２によるバイアス電流の制御幅は、入力インピーダンスの変動が許容範囲に収まるように厳しく制限される必要がある。入力段トランジスタＱ１１のベース電圧の変動幅を前述の動作保証温度範囲（絶対温度で約３０％）相当の１０ｍＶと制限すると、コレクタ電流の変動幅は最大で５０％になる。これは入力段トランジスタＱ１１のバイアス電流の変動幅が５０％以内であれば、入力インピーダンスの変動が許容範囲に収まることを意味する。
【００４１】
そこで、本実施形態では図４に示したバイアス制御回路１２の抵抗Ｒ５１，Ｒ５２の抵抗値及びトランジスタＱ５１，Ｑ５２のエミッタ面積を入力段トランジスタＱ１１のコレクタ電流の変動幅が５０％以内に収まるように制限する。すなわち、バイアス制御回路１２による入力段トランジスタＱ１１のバイアス電流の制御範囲を５０％以内に抑える。
【００４２】
このように本実施形態では、入力段トランジスタＱ１１のバイアス電流の制御による利得制御を行い、カスコードトランジスタによる電流の振り分けによる利得切り替えと合わせて、例えば３０ｄＢというような所望の利得制御幅を実現する。従って、バイアス電流の制御幅に対して例えば５０％以内という制限を与えることにより、入力インピーダンスの変動を許容できる範囲に収めつつ、消費電流の低減を可能とした利得切り替えを実現できる。
【００４３】
このとき電流振り分けとバイアス電流の制御を必ずしも同時に、つまり両者を関連付けて行う必要はなく、必要に応じて互いに独立に行うことも有効である。すなわち、前記の説明では利得切替回路１４が利得制御信号に従ってカスコードトランジスタＱ１２，Ｑ１３，Ｑ１４に対して電流振り分けの制御を行って利得切り替えを行う際、高利得時には入力段トランジスタＱ１１のバイアス電流を大きくし、低利得時にはバイアス電流を小さくするようなバイアス制御信号をバイアス制御回路１２に供給している。
【００４４】
これに対して、バイアス制御回路１２へのバイアス制御信号の供給を利得切替回路１４への利得制御信号とは関係なく行ってもよい。その場合、低利得時及び高利得時の各々の場合に入力段トランジスタＱ１１のバイアス電流を個別に制御することにより、利得をさらに細かく制御することもできる。
【００４５】
（第２の実施形態）
図５に、本発明の第２の実施形態に係る増幅器を示す。第１の実施形態では、利得を高利得と低利得の２段階に切り替え可能な増幅器について説明したが、本実施形態では５個のカスコードトランジスタＱ１２，Ｑ１３，Ｑ１４，Ｑ１５，Ｑ１６を用いることにより、利得を３段階に切り替え可能としている。同様に、本発明はカスコードトランジスタの数をさらに増やして、さらに多段階の利得切り替えを可能としてもよい。
【００４６】
このように多段階にわたる利得切り替えを行う構成においても、入力段トランジスタＱ１１のバイアス電流を第１の実施形態と同様に制御することができる。例えば、最高利得時にバイアス電流を最も大きくし、最低利得時にバイアス電流を最も小さくするか、あるいは、多段階の各利得においてバイアス電流を制御する。この場合においても、バイアス電流の制御幅は５０％以内に抑えることが望ましい。
【００４７】
（第３の実施形態）
図６は、本発明の第３の実施形態に係る増幅器であり、図１に示した第１の実施形態に係る増幅器を差動化した例である。本実施形態に係る増幅器は、差動信号を扱う以外は基本的に第１の実施形態と同様であり、第１の実施形態と同様にして利得切り替えが行われる。
【００４８】
図６においては、二つの信号入力端子１１Ａ，１１Ｂに差動入力信号がそれぞれ与えられる。差動入力信号に対応して、入力整合回路もインダクタＬ１１ＡとキャパシタＣ１１Ａの直列回路及びインダクタＬ１１ＢとキャパシタＣ１１Ｂの直列回路が備えられる。
【００４９】
入力段トランジスタＱ１１Ａ，Ｑ１１Ｂは差動対を構成しており、各々のエミッタはディジェネレーションインダクタＬ１３Ａ，Ｌ１３Ｂの一端にそれぞれ接続され、インダクタＬ１３Ａ，Ｌ１３Ｂの他端は共通の抵抗Ｒを介してグラウンドＧＮＤに接続される。バイアス制御回路１２は、二つの入力段トランジスタＱ１１Ａ，Ｑ１１Ｂのベースに接続される。
【００５０】
差動対の入力段トランジスタＱ１１Ａ，Ｑ１１Ｂに対応して、図１中のＱ１２，Ｑ１３，Ｑ１４に相当するカスコードトランジスタもＱ１２ＡとＱ１２Ｂ，Ｑ１３ＡとＱ１３Ｂ，Ｑ１４ＡとＱ１４Ｂのように対で設けられており、これらのカスコードトランジスタ対はそれぞれ利得制御回路１４からの差動信号によって相補的にオン／オフするように制御される。出力整合回路は、二つのインダクタＬ１２Ａ，Ｌ１２Ｂと二つのキャパシタＣ１２Ａ，Ｃ１２Ｂからなっており、この出力整合回路を介して信号出力端子１５Ａ，１５Ｂから差動出力信号が取り出される。
【００５１】
このように差動化した構成においても、カスコードトランジスタ対の数を増やすことにより、３段階さらにはそれ以上の多段階に利得切り替えを行うことが可能な増幅器を実現できることは明らかである。
【００５２】
次に、図７を用いて本実施形態の効果について具体的に述べる。図７は、図６に示した増幅器におけるバイアス制御回路１２を図４のように構成し、バイアス制御回路１２により入力段トランジスタＱ１１Ａ，Ｑ１１Ｂのバイアス電流を切り替えたときの入力反射特性を示している。
【００５３】
図４に示した構成のバイアス制御回路１２において、トランジスタＱ５１とＱ５２のエミッタ面積比及び抵抗Ｒ５１とＲ５２の値の比を種々変化させ、スイッチとして機能するトランジスタＭ５１，Ｍ５２をオン／オフさせることにより、バイアス電流を制御する。この場合、トランジスタＭ５１は常にオン状態となっており、トランジスタＱ５１にはＶ_Tリファレンス回路により発生される基準電圧で定まる一定の電流が常に流れている。トランジスタＭ５２をオン／オフさせることによって、トランジスタＱ５２に電流が流れるか否かを制御している。トランジスタＱ５１，Ｑ５２に流れる電流の合計によって、バイアス電流の値が決まる。
【００５４】
図７の横軸は周波数、縦軸は入力反射特性を示すためのＶＳＷＲ（電圧定在波比）を表している。各曲線の上に付された［Ａ／Ｂ］は、トランジスタＱ５２の電流Ｉ_Q52 とトランジスタＱ５１，Ｑ５２の合計の電流Ｉ_Q51＋Ｉ_Q52 との電流比を示している。例えば、［０／１２］はトランジスタＱ５１のみに常に一定の電流が流れていることを示しており、［４／８］は合計で１２単位となる電流のうち、４単位分の電流を制御できるようにしたことを示している。入力ＶＳＷＲの値は、入力インピーダンスの整合がとれていれば１．０となり、整合がずれてくると１よりも大きな値となる。ＬＮＡでは通常、回路の安定性確保のために、所望の周波数帯（例えば２．１〜２．２ＧＨｚ）において入力ＶＳＷＲの値が２．０以下に収まるように設計がなされる。
【００５５】
図７によると、例えば上記の電流比Ｉ_Q52／Ｉ_Q51＋Ｉ_Q52 が［５／７］、すなわちバイアス電流の制御幅が７１％のときは、入力ＶＳＷＲの値は所望の周波数帯の高域側で２．０を越えている。これに対して、電流比がバイアス電流の制御幅５０％に相当する［４／８］までであれば、入力ＶＳＷＲの値は２．０以下に収まっている。従って、この結果からもバイアス電流の制御幅は５０％以下であることが好ましいことが分かる。
【００５６】
以上の実施形態で説明した増幅器においては、バイアス制御信号として２値化信号を用いたが、連続値の信号を用いてバイアス電流を連続的に制御することも可能である。これにより利得の切り替えを連続的にあるいは、滑らかに行うことができる。さらに、これまでの実施形態では入力段トランジスタ及びカスコードトランジスタにバイポーラトランジスタを用いた例について説明したが、ＭＯＳトランジスタのような電界効果トランジスタを用いた回路でも同様に実施できることはいうまでもない。カスコードトランジスタに電界効果トランジスタを用いた場合、前述したバイポーラトランジスタのエミッタ面積の関係をゲート幅（Ｗ）とゲート長（Ｌ）の比Ｗ／Ｌに置き換えて考えればよいことが明らかである。
【００５７】
（第４の実施形態）
図８は、本発明の第４の実施形態として、上述した本発明の実施形態に基づく増幅器を受信系の低雑音増幅器に用いた携帯無線端末などの無線通信装置の概略的な構成を示している。
【００５８】
図８において、アンテナ８１は例えば基地局から送信される高周波信号を受信する。アンテナ８１から出力される受信信号は、送受切替器８２を介してＬＮＡ８３に入力される。ＬＮＡ８３によって増幅された受信信号は、例えば周波数変換、復調及びフィルタ処理などを行う図示しない受信処理回路系を経て受信ベースバンド信号となり、ベースバンド処理部８４に入力される。これにより受信信号のデータ再生が行われる。
【００５９】
一方、送信すべきデータに応じてベースバンド処理部８４によって生成される送信ベースバンド信号は、周波数変換、フィルタ処理及び変調などの処理を行う図示しない送信処理回路系を経て、電力増幅器８５から送受切替器８２を介してアンテナ８１に供給され、基地局に向けて送信される。
【００６０】
ＬＮＡ８３には、上述の第１〜第３の実施形態で説明したようなカスコードトランジスタによる入力段トランジスタの電流の振り分けと入力段トランジスタのバイアス電流制御との組み合わせによる利得切り替え機能を備えた増幅器が用いられる。ＬＮＡ８３への利得制御信号は、従来の無線通信端末と同様に、ベースバンド処理部８４から出力される。利得制御信号は実際にはＬＮＡ８３に対してのみならず、可変利得増幅器その他の回路ブロックへも適宜供給されるが、簡単のため図８ではベースバンド処理部８４からＬＮＡ８３への利得制御信号経路のみを示してある。
【００６１】
ここで、本実施形態の無線通信装置では、ベースバンド処理部８４により例えば図９に示すような手順に従って、ＬＮＡ８３の利得制御を行う。まず、ＬＮＡ８３の通常動作モードを低利得モードと定める。ベースバンド処理部８４によって、受信ベースバンド信号から受信信号レベルＶｒを観測して測定し（ステップＳ１）、Ｖｒが予め設定された第１の閾値Ｖth1以上か否かを調べる（ステップＳ２）。ＶｒがＶth1以上であれば、さらにＶｒが第２の閾値Ｖth2（ただし、Ｖth2＞Ｖth1）以上かどうかを調べる（ステップＳ３）。
【００６２】
ここで、Ｖｒ≧Ｖth2であれば低利得モードを維持する（ステップＳ５）。この低利得モードは、例えば第１の実施形態において図１中のカスコードトランジスタＱ１２，Ｑ１３，Ｑ１４のうちＱ１２とＱ１４をオン、Ｑ１３をオフにした状態に相当する。また、このときは入力段トランジスタＱ１１のバイアス電流を前述した５０％のバイアス電流制御範囲の最小値に設定する。
【００６３】
一方、ステップＳ２においてＶｒが第１の閾値Ｖth1に満たない受信信号が一定期間入力された場合、言い換えればＶｒがVth1以上の受信信号が一定期間入力されなかった場合（ステップＳ４でＹＥＳ）、ＬＮＡ８３を低利得モードから高利得モードに変更する（ステップＳ６）。この高利得モードは、例えば第１の実施形態において図１中のカスコードトランジスタＱ１２，Ｑ１３，Ｑ１４のうちＱ１２とＱ１３をオン、Ｑ１４をオフにした状態に相当する。また、このときは入力段トランジスタＱ１１のバイアス電流を前述した５０％のバイアス電流制御範囲の最大値に設定する。
【００６４】
このような利得制御をＬＮＡ８３に対して行うと、無線通信装置が消費電流の少ない低利得モードで動作する期間の割合が増す。従って、無線通信装置が特に電池を電源とする携帯無線端末の場合、電池寿命が延びることになり、一回の充電で端末を使用できる時間を長くとることができる。
【００６５】
上記説明では、ＬＮＡ８３の利得切り替えを低利得と高利得の２段階に行うと説明したが、さらに多段階に利得切り替えを行ってもよいことは言うまでもない。その場合、受信信号レベルの判定のための閾値を３つ以上用意しておけばよい。
【００６６】
【発明の効果】
以上説明したように本発明によれば、入力インピーダンスの変動による回路特性の劣化を抑えつつ、消費電流の低減を可能とした広範囲の利得切り替え機能を持つ増幅器を実現できる。さらに、この増幅器を低雑音増幅器に用いて消費電流の低減を可能とした無線通信装置を提供することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係る増幅器の構成を示す回路図
【図２】同実施形態における利得切替回路の具体的な構成例を示す回路図
【図３】同実施形態における利得切替回路の他の具体的な構成例を示す回路図
【図４】同実施形態におけるバイアス制御回路の具体的な構成例を示す回路図
【図５】本発明の第２の実施形態に係る増幅器の構成を示す回路図
【図６】本発明の第３の実施形態に係る増幅器の構成を示す回路図
【図７】同実施形態におけるバイアス電流の最適制御範囲を説明するための入力ＶＳＷＲの周波数特性を示す図
【図８】本発明の第４の実施形態に係る無線通信装置の概略的な構成を示すブロック図
【図９】同実施形態における低雑音増幅器に対する利得制御の手順を示すフローチャート
【符号の説明】
１１，１１Ａ，１１Ｂ…信号入力端子
１２…バイアス制御回路
１３…制御入力端子
１４…利得切替回路
１５，１５Ａ，１５Ｂ…信号出力端子
８１…アンテナ
８２…送受切替器
８３…低雑音増幅器
８４…ベースバンド処理部
８５…電力増幅器[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an amplifier having a gain switching function and a radio communication apparatus using the same.
[0002]
[Prior art]
In recent years, mobile phones have been remarkably enhanced in functionality and have played a role as portable information terminals that transmit and receive various digital data including image information as well as transmission and reception of voice call signals. In general, higher functionality of a system raises the demand for electronic circuits constituting the system.
[0003]
For example, in a wireless communication device such as a cellular phone, a low noise amplifier (LNA) that is usually provided on the receiving side is taken as an example, and it is constant regardless of changes in received signal strength due to changes in the surrounding environment. It is required that the received signal can be amplified while maintaining a standard signal quality. In order to meet this requirement, the LNA is provided with a gain switching function. In the current system environment of the wireless communication apparatus, the fluctuation of the received signal strength is large, and the gain control width required for the LNA having the gain switching function is as large as about 30 dB.
[0004]
In a conventional LNA having a gain switching function, a gain switching method is used by switching the value of a current flowing through an input stage transistor using a plurality of transistors (cascode transistors) cascode-connected to the input stage transistor. (For example, refer nonpatent literature 1).
[0005]
More specifically, gain switching is performed by controlling on / off of a plurality of cascode transistors connected to the collector of the input stage transistor and changing the number of cascode transistors that distribute the collector current of the input stage transistor. At that time, the collector current of the input stage transistor is held at a constant value by the base voltage supplied from the bias circuit. By keeping the bias condition of the input stage transistor constant in this way, fluctuations in input impedance due to LNA gain switching can be suppressed.
[0006]
[Non-Patent Document 1]
Danilo Manstretta, Rinaldo Castello, Francesco Gatta, Paolo Rossi and Francesco Svelto, “A 0.18μm CMOS Direct-Conversion Receiver Front-End for UMTS,” 2002 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.240-241, 2002
[0007]
[Problems to be solved by the invention]
In the method described in Non-Patent Document 1, in order to avoid fluctuation of input impedance with respect to gain change, it is necessary to keep a bias condition of the input stage transistor constant by flowing a constant collector current through the input stage transistor even at low gain. There is. Accordingly, the average current consumption increases.
[0008]
Wireless communication devices such as mobile terminal devices such as mobile phones are strongly required to reduce power consumption in order to ensure continuous use time. Therefore, a technology for reducing current consumption while maintaining good circuit characteristics is required for the electronic circuit in such a wireless communication apparatus. In the prior art, particularly with respect to the LNA, as described above, the request is not sufficiently satisfied.
[0009]
An object of the present invention is to provide an amplifier particularly suitable as a low noise amplifier capable of effectively reducing current consumption while avoiding fluctuations in input impedance due to gain change.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, an amplifier according to the present invention includes an input stage transistor that receives an input signal from a signal input terminal, a plurality of cascode transistors that are cascode-connected to the input stage transistor, and a first control signal. A first control circuit for controlling on / off of at least one of the plurality of cascode transistors so that the distribution ratio of the current flowing through the input stage transistor to the signal output terminal side is switched to at least two stages, and the operation of the input stage transistor And a second control circuit that determines a point and controls a bias current of the input stage transistor according to a second control signal.
[0011]
According to the present invention, a combination of gain switching by the collector current distribution of the input stage transistor by the first control circuit and bias current control of the input stage transistor and a sufficient gain control width are ensured, and the gain change is accompanied. It becomes possible to avoid fluctuations in input impedance and to effectively reduce current consumption.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 shows a configuration of an amplifier suitable as a low noise amplifier (LNA) according to the first embodiment of the present invention.
An input signal from the signal input terminal 11 is input to the base of the input stage transistor Q11 via an input matching circuit composed of a series circuit of an inductor L11 and a capacitor C11. The input matching circuit is a circuit for matching the input impedance of the amplifier with the impedance of the previous stage of the amplifier. The emitter of the input stage transistor Q11 is connected to one end of a degeneration inductor L13 for improving distortion characteristics, and the other end of the inductor L13 is connected to the ground GND.
[0013]
A bias control circuit 12 (second control circuit) is connected to the base of the input stage transistor Q11. The bias control circuit 12 determines the operating point of the input stage transistor Q11 to an appropriate value and controls the bias current.
[0014]
The collector of the input stage transistor Q11 is connected in common to the emitters of a plurality (three in this example) of cascode transistors Q12, Q13, Q14. Of the cascode transistors Q12, Q13, and Q14, the collectors of Q12 and Q13 are connected to one end of each of a capacitor C12 and an inductor L12 that form an output matching circuit. The output matching circuit is a circuit for matching the output impedance of the amplifier with the input impedance of the subsequent stage. The other end of the capacitor C12 is connected to the signal output terminal 15. The other end of the inductor L12 is connected to the power supply Vcc. The collector of another cascode transistor Q14 is directly connected to the power supply Vcc.
[0015]
A gain switching circuit 14 (first control circuit) is connected to the bases of the cascode transistors Q12, Q13, and Q14. The gain switching circuit 14 controls on / off of the cascode transistors Q13 and Q14 according to a gain control signal (first control signal) input from the outside to the control input terminal 13. As a result, the distribution ratio of the collector current of the input stage transistor Q11 to the signal output terminal 15 side is switched, and as a result, the gain of the amplifier is switched in two stages.
[0016]
A bias control signal (second control signal) is sent from the gain switching circuit 14 to the bias control circuit 12. In accordance with this bias control signal, the bias control circuit 12 controls the base voltage of the input stage transistor Q11 in connection with the on / off control of the cascode transistors Q13 and Q14 by the gain switching circuit 14 in this embodiment, whereby the transistor Q11 The bias current is controlled.
[0017]
As described above, in this embodiment, the gain switching of the amplifier is performed by a combination of the on / off control of the cascode transistors Q13 and Q14 by the gain switching circuit 14 and the control of the bias current of the input stage transistor Q11 by the bias control circuit 12 associated therewith. Is done.
[0018]
Next, the operation of the amplifier according to the present embodiment will be described.
As described above, the gain switching in this embodiment is performed by (a) distributing the collector current of the input stage transistor Q11 by on / off control of the cascode transistors Q13 and Q14, and (b) input stage transistor Q11 by the bias control circuit 12. This is a combination of controlling the bias current.
[0019]
First, (a) a gain switching operation by distributing the collector current of the input stage transistor Q11 will be described.
In this embodiment, the gain of the amplifier is basically switched to two stages by distributing the collector current by the three cascode transistors Q12, Q13, and Q14. For this purpose, among the three cascode transistors Q12, Q13, and Q14, Q13 and Q14 are controlled by the gain switching circuit 14 so that one is turned on and the other is turned off by the control signal from the gain control circuit 14. . Transistor Q12 is kept on. The emitter areas of the transistors Q13 and Q14 are preferably set equal to each other, and are selected to be sufficiently larger than the emitter area of the transistor Q12, for example, 30 times according to a desired gain control width.
[0020]
An input signal from the signal input terminal 11 is amplified by the input stage transistor Q11 and appears as a collector current of the transistor Q11. The collector current of the transistor Q11 flows into the collector of Q11 through the cascode transistors Q12, Q13, and Q14. At this time, if Q12 and Q13 are in the on state and Q14 is in the off state among the cascode transistors Q12, Q13, and Q14, the collector current of the input stage transistor Q11 passes through the signal output terminal 15 side of the amplifier. Gain is obtained.
[0021]
On the other hand, out of the cascode transistors Q12, Q13, and Q14, assuming that Q12 and Q14 are in an on state and Q13 is in an off state, the collector current of the input stage transistor Q11 is a component and a transistor that flow through the signal output terminal 15 side. It is divided into components that flow on the Q14 side, and the latter is a component that flows directly from the power source Vcc, and does not contribute to the output signal, so the gain is low.
[0022]
At this time, by selecting the emitter areas of the transistors Q13 and Q14 to be sufficiently larger than the emitter area of the transistor Q12 as described above, the gain difference between the high gain and the low gain, that is, the gain control width can be increased. . Further, by making the emitter areas of the transistors Q13 and Q14 equal, fluctuations in circuit characteristics due to manufacturing variations can be suppressed.
[0023]
Next, (b) gain control by controlling the bias current of the input stage transistor Q11 will be described.
In general, it is also possible in principle to switch the gain in the LNA simply by changing the bias current (collector current) of the input stage transistor. However, in order to produce a desired large gain control width of, for example, 30 dB only by controlling the bias current, the base voltage of the input stage transistor must be changed over a wide range. If the base voltage of the input stage transistor changes greatly, the input impedance of the amplifier will fluctuate significantly, so that the reflection characteristics of the input deteriorate, and in the worst case, the circuit oscillates. Therefore, in a circuit that handles a high frequency signal in the GHz band such as LNA in a mobile phone, it is difficult to switch the gain over a wide range only by the method of controlling the bias current of the input stage transistor.
[0024]
In the present embodiment, such a problem is solved by combining (a) gain switching by distributing the collector current of the input stage transistor Q11 and (b) controlling the bias current of the input stage transistor Q11. Specifically, for example, among the cascode transistors Q12, Q13, and Q14, the bias current is increased at the time of high gain when Q12 and Q13 are on and Q14 is off, Q12 and Q14 are on, and Q13 is off. When the gain is low, a wide gain control width is secured by reducing the bias current. At that time, the control range of the bias current is preferably within 50% as will be described later. For example, if the bias current at low gain is “1”, the bias current at high gain is set to “1.5” or less.
[0025]
Next, the configuration of each unit in FIG. 1 will be described in detail.
FIG. 2 shows a specific configuration example of the gain switching circuit 14. This circuit includes transistors M21 and M22 connected between the power supply Vss and the ground GND, and two-stage CMOS inverters 20 and 21 including transistors M23 and M24. The gain control signal from the control input terminal 13 is input to the first-stage CMOS inverter 20. The output of the first-stage CMOS inverter 20 is supplied to the base of the cascode transistor Q14 in FIG. The output of the second-stage CMOS inverter 21 is supplied to the base of the cascode transistor Q13 in FIG.
[0026]
The cascode transistors Q13 and Q14 are turned on when the base potential is high. According to the configuration of FIG. 2, the outputs of the CMOS inverters 20 and 21 are in a state where one is at a high level and the other is at a low level, and are always inverted. Therefore, when one of the cascode transistors Q13 and Q14 is turned on, the other is turned off. On the other hand, since the potential of the power supply Vss is applied to the base of the cascode transistor Q12 via the terminal 22, the transistor Q12 always maintains an on state.
[0027]
FIG. 3 shows another specific configuration example of the gain switching circuit 14. The generation of the inversion signal using the CMOS inverter is the same as that of the circuit of FIG. 2 except that the amplitude of the output voltage is limited. In FIG. 3, transistors M31 and M32 and transistors M35 and M36 constitute the first and second stage CMOS inverters, respectively.
[0028]
An amplitude limiting circuit including transistors M33 and M34 and a resistor R31 is arranged on the output side of the first-stage CMOS inverter. Similarly, transistors M37 and M38 and a resistor R32 are also provided on the output side of the second-stage CMOS inverter. An amplitude limiting circuit is arranged. The transistors M34 and M38 function as a current source, and form a current mirror together with the diode-connected transistor M39. Terminals 22, 23, and 24 are connected to the bases of cascode transistors Q12, Q13, and Q14 in FIG.
[0029]
In the circuit of FIG. 3, the value of the current flowing through the current source transistors M34, M38, and M39 can be adjusted by the value of the resistor R33 connected in series with the transistor M39. By appropriately selecting the current value and the values of the resistors R31 and R32, the voltage output from the terminals 23 and 24, that is, the potential applied to the bases of the cascode transistors Q13 and Q14 in FIG. To. As a result, it is possible to avoid the problem of degrading the stable operation of the bipolar transistor if the base potential is too low compared to the emitter potential, and to stabilize the operation of the cascode transistors Q13 and Q14.
[0030]
In FIG. 2 and FIG. 3, a portion that generates a bias control signal to be supplied from the gain switching circuit 14 to the bias control circuit 12 is omitted, but the gain switching circuit 14 has a gain from the control input terminal 13 in this embodiment. In accordance with the control signal, for example, a bias control signal that increases the bias current of the input stage transistor Q11 at high gain and decreases the bias current at low gain is configured to be supplied to the bias control circuit 12.
[0031]
FIG. 4 shows a specific configuration example of the bias control circuit 12. In the present embodiment, the bias control circuit 12 has a function of receiving a bias control signal from the gain control circuit 14 and creating a plurality of bias conditions. In the amplifier of FIG. 1, the bias condition here is the setting of the base voltage of the input stage transistor Q11. The bias control circuit 12 of FIG. 4 is described in, for example, Paul R. Gray and Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits, Third Edition”, John Wiley & Sons, P.329, 1993. V_T It is based on a circuit generally known as a reference circuit.
[0032]
In FIG. 4, a thermal voltage V is generated by a circuit composed of bipolar transistors Q41 to Q47, resistors R41 to R47, and a MOS transistor M40._TA voltage with reference to is generated. This reference voltage is applied to the bases of the transistors Q51 and Q52. MOS transistors M51 and 52 functioning as switches are connected between the emitters of the transistors Q51 and Q52 and the power supply Vss, and a bias control signal from the gain switching circuit 14 is input to the gates of M51 and M52.
[0033]
Next, a method for controlling the bias current by the bias control circuit 12 will be described in detail. In general, the base-emitter voltage V of a bipolar transistor_BEAnd collector current I_CThe relationship is expressed by the following equation.
[0034]
[Expression 1]

[0035]
Where I_SIs a constant determined by process conditions. Thermal voltage V_{T ,}Is a value determined by kT / q from the elementary charge q, the Boltzmann constant k, and the absolute temperature T, and is one of the important variables that determine the characteristics of the semiconductor device. Thermal voltage V at room temperature (27 degrees Celsius)_TThe value of is about 26 mV.
[0036]
Here, in the bias control circuit 12 having the configuration shown in FIG. 4, the MOS transistors M51 and M52 are turned on / off by the bias control signals supplied from the gain switching circuit 14 to the terminals 41 and 42, respectively, thereby the transistor Q51. And the operation of Q52 is determined. As a result, the voltage of the bias control signal given as the base voltage from the bias control circuit 12 to the input stage transistor Q11 in FIG. 1 is determined.
[0037]
In the present embodiment, the control range of the bias current of the input stage transistor Q11 by the bias control circuit 14 is set as follows. For example, consider a case where a gain control width of 30 dB or more, which is generally required in an LNA, is realized. In this case, the output signal current requires a current change width of about 32 times. When this current change width is realized only by the current distribution of (a), transistors having an emitter area ratio corresponding to the current change width are used for the cascode transistors Q12, Q13, and Q14. In the conventional technique in which the gain is switched only by the method (a), the current consumption is constant because it is necessary to make the bias current of the input stage transistor Q11 constant in order to suppress the fluctuation of the input impedance. As described above, there is a problem that it becomes larger.
[0038]
  On the other hand, when the current change width of the output signal current is to be realized by controlling the bias current in order to reduce power consumption, there are the following problems. The above formula (2Therefore, in order to realize a gain control width of 30 dB or more, a change in base voltage of the input stage transistor Q11 requires a voltage fluctuation width of about 90 mV at room temperature in order to give a change of 30 times or more to the collector current. Become. Here, for the sake of simplicity, it is assumed that the potential at the emitter end is constant.
[0039]
Consumer devices such as mobile phones guarantee operation in the temperature range of approximately −40 ° C. to 85 ° C. This guaranteed operating temperature range is a fluctuation range of about 30% in absolute temperature with respect to normal temperature._T The fluctuation is about 11 mV. Compared to this, it is understood that the fluctuation of the base voltage of about 90 mV is a very large value. If there is such a voltage fluctuation, it cannot be considered that the input stage transistor Q11 is operating under the same conditions, and the fluctuation of the input impedance cannot be ignored.
[0040]
In a high-frequency circuit that handles signals of 2 GHz band or higher, such as a portable communication terminal, input impedance matching conditions greatly affect circuit characteristics such as gain. If the input impedance changes and the matching condition deteriorates, a standing wave may be generated due to reflection, which may cause circuit oscillation. Therefore, the control range of the bias current by the bias control circuit 12 needs to be strictly limited so that the fluctuation of the input impedance falls within the allowable range. When the fluctuation range of the base voltage of the input stage transistor Q11 is limited to 10 mV, which corresponds to the above-described guaranteed operating temperature range (about 30% in absolute temperature), the fluctuation range of the collector current is 50% at the maximum. This means that if the fluctuation range of the bias current of the input stage transistor Q11 is within 50%, the fluctuation of the input impedance falls within the allowable range.
[0041]
Therefore, in the present embodiment, the resistance values of the resistors R51 and R52 of the bias control circuit 12 and the emitter areas of the transistors Q51 and Q52 shown in FIG. 4 are set so that the fluctuation range of the collector current of the input stage transistor Q11 is within 50%. Restrict. That is, the control range of the bias current of the input stage transistor Q11 by the bias control circuit 12 is suppressed to 50% or less.
[0042]
Thus, in the present embodiment, gain control is performed by controlling the bias current of the input stage transistor Q11, and a desired gain control width of, for example, 30 dB is realized together with gain switching by current distribution by the cascode transistor. Therefore, by providing a limit of, for example, 50% or less to the control range of the bias current, it is possible to realize gain switching that can reduce the consumption current while keeping the fluctuation of the input impedance within an allowable range.
[0043]
At this time, current distribution and bias current control are not necessarily performed simultaneously, that is, in association with each other, and it is also effective to perform them independently of each other as necessary. That is, in the above description, when the gain switching circuit 14 controls the current distribution to the cascode transistors Q12, Q13, and Q14 according to the gain control signal and performs gain switching, the bias current of the input stage transistor Q11 is increased at high gain. At the time of low gain, a bias control signal for reducing the bias current is supplied to the bias control circuit 12.
[0044]
On the other hand, the supply of the bias control signal to the bias control circuit 12 may be performed regardless of the gain control signal to the gain switching circuit 14. In that case, the gain can be further finely controlled by individually controlling the bias current of the input stage transistor Q11 in each of the low gain and high gain cases.
[0045]
(Second Embodiment)
FIG. 5 shows an amplifier according to the second embodiment of the present invention. In the first embodiment, the amplifier capable of switching the gain between two stages of high gain and low gain has been described. In the present embodiment, by using five cascode transistors Q12, Q13, Q14, Q15, and Q16, The gain can be switched in three stages. Similarly, the present invention may further increase the number of cascode transistors to enable multistage gain switching.
[0046]
Even in such a configuration in which gain switching is performed in multiple stages, the bias current of the input stage transistor Q11 can be controlled in the same manner as in the first embodiment. For example, the bias current is maximized at the highest gain and the bias current is minimized at the lowest gain, or the bias current is controlled at each of the multistage gains. Even in this case, it is desirable to keep the control range of the bias current within 50%.
[0047]
(Third embodiment)
FIG. 6 shows an amplifier according to the third embodiment of the present invention, which is an example in which the amplifier according to the first embodiment shown in FIG. 1 is differentiated. The amplifier according to the present embodiment is basically the same as that of the first embodiment except that differential signals are handled, and gain switching is performed in the same manner as in the first embodiment.
[0048]
In FIG. 6, differential input signals are applied to the two signal input terminals 11A and 11B, respectively. Corresponding to the differential input signal, the input matching circuit is also provided with a series circuit of an inductor L11A and a capacitor C11A and a series circuit of an inductor L11B and a capacitor C11B.
[0049]
The input stage transistors Q11A and Q11B form a differential pair, each emitter is connected to one end of the degeneration inductors L13A and L13B, and the other ends of the inductors L13A and L13B are connected to the ground GND through a common resistor R. Connected to. The bias control circuit 12 is connected to the bases of the two input stage transistors Q11A and Q11B.
[0050]
  Corresponding to the input stage transistors Q11A and Q11B of the differential pair, the cascode transistors corresponding to Q12, Q13 and Q14 in FIG. 1 are also Q12A and Q12B,Q13AQ13B, Q14A, and Q14B are provided in pairs, and these cascode transistor pairs are controlled to be turned on / off in a complementary manner by differential signals from the gain control circuit 14, respectively. The output matching circuit includes two inductors L12A and L12B and two capacitors C12A and C12B, and differential output signals are taken out from the signal output terminals 15A and 15B via the output matching circuit.
[0051]
Even in such a differential configuration, it is apparent that an amplifier capable of performing gain switching in three or more stages can be realized by increasing the number of cascode transistor pairs.
[0052]
Next, the effect of the present embodiment will be specifically described with reference to FIG. FIG. 7 shows the input reflection characteristics when the bias control circuit 12 in the amplifier shown in FIG. 6 is configured as shown in FIG. 4 and the bias current of the input stage transistors Q11A and Q11B is switched by the bias control circuit 12. .
[0053]
In the bias control circuit 12 having the configuration shown in FIG. 4, the emitter area ratio of the transistors Q51 and Q52 and the ratio of the values of the resistors R51 and R52 are variously changed to turn on and off the transistors M51 and M52 functioning as switches. Control the bias current. In this case, the transistor M51 is always on, and the transistor Q51 has V_TA constant current determined by the reference voltage generated by the reference circuit always flows. By turning on / off the transistor M52, it is controlled whether or not a current flows through the transistor Q52. The value of the bias current is determined by the sum of the currents flowing through the transistors Q51 and Q52.
[0054]
In FIG. 7, the horizontal axis represents frequency, and the vertical axis represents VSWR (voltage standing wave ratio) for indicating input reflection characteristics. [A / B] given above each curve is the current I of the transistor Q52._Q52 And the total current I of the transistors Q51 and Q52_Q51+ I_Q52 And the current ratio. For example, [0/12] indicates that a constant current always flows only through the transistor Q51, and [4/8] can control a current corresponding to 4 units out of a total of 12 units. It shows that it did. The value of the input VSWR becomes 1.0 when the input impedance is matched, and becomes a value larger than 1 when the matching is shifted. The LNA is usually designed so that the value of the input VSWR falls within 2.0 in a desired frequency band (for example, 2.1 to 2.2 GHz) in order to ensure the stability of the circuit.
[0055]
According to FIG. 7, for example, the above current ratio I_Q52/ I_Q51+ I_Q52 [5/7], that is, when the control width of the bias current is 71%, the value of the input VSWR exceeds 2.0 on the high frequency side of the desired frequency band. On the other hand, if the current ratio is up to [4/8] corresponding to a control width of 50% of the bias current, the value of the input VSWR is 2.0 or less. Therefore, it can be seen from this result that the control range of the bias current is preferably 50% or less.
[0056]
  In the amplifiers described in the above embodiments, the binarized signal is used as the bias control signal. However, it is also possible to continuously control the bias current using a continuous value signal. Thereby, the gain can be switched continuously or smoothly. Further, in the embodiments described so far, the example in which the bipolar transistor is used for the input stage transistor and the cascode transistor has been described, but the same applies to a circuit using a field effect transistor such as a MOS transistor.ImplementationNeedless to say, it can be done. When a field effect transistor is used as the cascode transistor, the relationship between the emitter area of the bipolar transistor described above may be replaced with the ratio W / L of the gate width (W) and the gate length (L).Butit is obvious.
[0057]
(Fourth embodiment)
FIG. 8 shows, as a fourth embodiment of the present invention, a schematic configuration of a radio communication apparatus such as a portable radio terminal using the amplifier according to the above-described embodiment of the present invention as a low noise amplifier for a reception system. Yes.
[0058]
In FIG. 8, an antenna 81 receives a high frequency signal transmitted from, for example, a base station. The reception signal output from the antenna 81 is input to the LNA 83 via the transmission / reception switch 82. The reception signal amplified by the LNA 83 becomes a reception baseband signal through a reception processing circuit system (not shown) that performs, for example, frequency conversion, demodulation, and filter processing, and is input to the baseband processing unit 84. As a result, data reproduction of the received signal is performed.
[0059]
On the other hand, a transmission baseband signal generated by the baseband processing unit 84 according to data to be transmitted is transmitted and received from the power amplifier 85 via a transmission processing circuit system (not shown) that performs processing such as frequency conversion, filter processing, and modulation. The signal is supplied to the antenna 81 via the switch 82 and transmitted to the base station.
[0060]
As the LNA 83, an amplifier having a gain switching function by combining the current distribution of the input stage transistor by the cascode transistor and the bias current control of the input stage transistor as described in the first to third embodiments is used. It is done. The gain control signal to the LNA 83 is output from the baseband processing unit 84 as in the conventional wireless communication terminal. Although the gain control signal is actually supplied not only to the LNA 83 but also to the variable gain amplifier and other circuit blocks as appropriate, only the gain control signal path from the baseband processing unit 84 to the LNA 83 is shown in FIG. Is shown.
[0061]
Here, in the wireless communication apparatus of the present embodiment, the baseband processing unit 84 performs gain control of the LNA 83 in accordance with a procedure as shown in FIG. First, the normal operation mode of the LNA 83 is defined as the low gain mode. The baseband processing unit 84 observes and measures the received signal level Vr from the received baseband signal (step S1), and checks whether Vr is equal to or higher than a preset first threshold value Vth1 (step S2). If Vr is equal to or greater than Vth1, it is further checked whether Vr is equal to or greater than a second threshold value Vth2 (where Vth2> Vth1) (step S3).
[0062]
Here, if Vr ≧ Vth2, the low gain mode is maintained (step S5). This low gain mode corresponds to, for example, a state in which Q12 and Q14 are turned on and Q13 is turned off among the cascode transistors Q12, Q13, and Q14 in FIG. 1 in the first embodiment. At this time, the bias current of the input stage transistor Q11 is set to the minimum value of the above-described 50% bias current control range.
[0063]
On the other hand, when a received signal whose Vr is less than the first threshold value Vth1 is input for a certain period in step S2, in other words, when a received signal whose Vr is Vth1 or more is not input for a certain period (YES in step S4), the LNA 83 Is changed from the low gain mode to the high gain mode (step S6). This high gain mode corresponds to, for example, a state in which Q12 and Q13 are turned on and Q14 is turned off among the cascode transistors Q12, Q13, and Q14 in FIG. 1 in the first embodiment. At this time, the bias current of the input stage transistor Q11 is set to the maximum value of the 50% bias current control range described above.
[0064]
When such gain control is performed on the LNA 83, the ratio of the period during which the wireless communication apparatus operates in the low gain mode with low current consumption increases. Therefore, in the case where the wireless communication device is a portable wireless terminal that uses a battery as a power source, the battery life is extended, and the time that the terminal can be used with a single charge can be increased.
[0065]
  In the above description, the gain switching of the LNA83 is performed in two stages, low gain and high gain.DoHowever, it goes without saying that gain switching may be performed in more stages. In that case, three or more thresholds for determining the received signal level may be prepared.
[0066]
【The invention's effect】
As described above, according to the present invention, it is possible to realize an amplifier having a wide range of gain switching functions capable of reducing current consumption while suppressing deterioration in circuit characteristics due to fluctuations in input impedance. Furthermore, it is possible to provide a wireless communication apparatus that can reduce current consumption by using this amplifier as a low noise amplifier.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of an amplifier according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a specific configuration example of a gain switching circuit in the same embodiment;
FIG. 3 is a circuit diagram showing another specific configuration example of the gain switching circuit according to the embodiment;
FIG. 4 is a circuit diagram showing a specific configuration example of a bias control circuit in the embodiment;
FIG. 5 is a circuit diagram showing a configuration of an amplifier according to a second embodiment of the present invention.
FIG. 6 is a circuit diagram showing a configuration of an amplifier according to a third embodiment of the present invention.
FIG. 7 is a view showing frequency characteristics of an input VSWR for explaining an optimum control range of bias current in the embodiment;
FIG. 8 is a block diagram showing a schematic configuration of a wireless communication apparatus according to a fourth embodiment of the present invention.
FIG. 9 is a flowchart showing a gain control procedure for the low noise amplifier according to the embodiment;
[Explanation of symbols]
11, 11A, 11B ... signal input terminals
12 ... Bias control circuit
13 ... Control input terminal
14 ... Gain switching circuit
15, 15A, 15B ... Signal output terminals
81. Antenna
82 ... Transmission / reception switch
83. Low noise amplifier
84 ... Baseband processing section
85 ... Power amplifier

Claims (7)

An input stage transistor to which an input signal from a signal input terminal is input to the base;
A first cascode transistor having an emitter connected to the collector of the input stage transistor and a collector connected to a power supply via a connection point with a signal output terminal;
A second cascode transistor having an emitter connected to the collector of the input transistor and a collector connected between the collector of the first cascode transistor and the connection point;
A third cascode transistor having an emitter connected to the collector of the input transistor and a current supplied from the power supply to the collector;
The first cascode transistor is maintained in an on state, and the base potential of the second cascode transistor and the base potential of the third cascode transistor are controlled to control the second cascode transistor and the third cascode transistor. A first control circuit having an on / off relationship in which the cascode transistors are inverted from each other;
And a second control circuit that controls the bias current of the input stage transistor so that the bias current of the input stage transistor is larger when the third cascode transistor is on than when the third cascode transistor is on. amplifier.   The amplifier according to claim 1, wherein the second cascode transistor and the third cascode transistor have an emitter area larger than an emitter area of the first cascode transistor. An input stage transistor to which an input signal from the signal input terminal is input to the gate;
A first cascode transistor having a source connected to a drain of the input stage transistor and a drain connected to a power supply via a connection point with a signal output terminal;
A second cascode transistor having a source connected to the drain of the input transistor and a drain connected between the drain of the first cascode transistor and the connection point;
A third cascode transistor having a source connected to the drain of the input transistor and a current from the power supply supplied to the drain;
The first cascode transistor is maintained in an on state, and the gate potential of the second cascode transistor and the gate potential of the third cascode transistor are controlled to control the second cascode transistor and the third cascode transistor. A first control circuit having an on / off relationship in which the cascode transistors are inverted from each other;
And a second control circuit that controls the bias current of the input stage transistor so that the bias current of the input stage transistor is larger when the third cascode transistor is on than when the third cascode transistor is on. amplifier.   4. The amplifier according to claim 3, wherein the second cascode transistor and the third cascode transistor have a gate width / gate length ratio larger than a gate width / gate length ratio of the first cascode transistor. The second control circuit is configured such that when the bias current when the third cascode transistor is on is 1, the bias current when the second cascode transistor is on is 1.5 or less. 4. The amplifier according to claim 1, wherein a bias current of the input stage transistor is controlled.   A wireless communication apparatus comprising a receiver using the amplifier according to any one of claims 1 to 5 as a low noise amplifier for amplifying a received signal. A receiver using the amplifier according to any one of claims 1 to 5 as a low-noise amplifier for amplifying a received signal;
Control means for generating a gain control signal for controlling the first control circuit based on a level measurement result of the received signal;
The control means turns on the first cascode transistor and the third cascode transistor if the level of the received signal is not less than a first threshold and not less than a second threshold greater than the first threshold. The second cascode transistor is turned off, and when the level of the received signal is less than the first threshold for a predetermined time, the first cascode transistor and the second cascode transistor are turned on, and the third cascode transistor is turned on. The gain control signal is generated so as to control the base potential or the gate potential of each of the first cascode transistor, the second cascode transistor, and the third cascode transistor so that the cascode transistor of the first cascode transistor is turned off. Wireless communication device.

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